xref: /netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/rs6000/sfp-exceptions.c (revision 8feb0f0b7eaff0608f8350bbfa3098827b4bb91b)
1*8feb0f0bSmrg /* Copyright (C) 2016-2020 Free Software Foundation, Inc.
236ac495dSmrg 
336ac495dSmrg    This file is free software; you can redistribute it and/or modify it
436ac495dSmrg    under the terms of the GNU General Public License as published by the
536ac495dSmrg    Free Software Foundation; either version 3, or (at your option) any
636ac495dSmrg    later version.
736ac495dSmrg 
836ac495dSmrg    This file is distributed in the hope that it will be useful, but
936ac495dSmrg    WITHOUT ANY WARRANTY; without even the implied warranty of
1036ac495dSmrg    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
1136ac495dSmrg    General Public License for more details.
1236ac495dSmrg 
1336ac495dSmrg    Under Section 7 of GPL version 3, you are granted additional
1436ac495dSmrg    permissions described in the GCC Runtime Library Exception, version
1536ac495dSmrg    3.1, as published by the Free Software Foundation.
1636ac495dSmrg 
1736ac495dSmrg    You should have received a copy of the GNU General Public License and
1836ac495dSmrg    a copy of the GCC Runtime Library Exception along with this program;
1936ac495dSmrg    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
2036ac495dSmrg    <http://www.gnu.org/licenses/>.  */
2136ac495dSmrg 
2236ac495dSmrg #include "sfp-machine.h"
2336ac495dSmrg 
2436ac495dSmrg /* Only provide exception support if we have hardware floating point and we can
2536ac495dSmrg    execute the mtfsf instruction.  This would only be true if we are using the
2636ac495dSmrg    emulation routines for IEEE 128-bit floating point on pre-ISA 3.0 machines
2736ac495dSmrg    without the IEEE 128-bit floating point support.  */
2836ac495dSmrg 
2936ac495dSmrg #ifndef __NO_FPRS__
3036ac495dSmrg 
3136ac495dSmrg void
__sfp_handle_exceptions(int _fex)3236ac495dSmrg __sfp_handle_exceptions (int _fex)
3336ac495dSmrg {
3436ac495dSmrg   const double fp_max = __DBL_MAX__;
3536ac495dSmrg   const double fp_min = __DBL_MIN__;
3636ac495dSmrg   const double fp_zero = (double) 0.0;
3736ac495dSmrg   const double fp_one = 1.0;
3836ac495dSmrg   double tmp;
3936ac495dSmrg 
4036ac495dSmrg   if (_fex & FP_EX_INVALID)
4136ac495dSmrg     {
4236ac495dSmrg       __asm__ __volatile__ ("fdiv %0, %1, %1"
4336ac495dSmrg 			    : "=f" (tmp)
4436ac495dSmrg 			    : "f" (fp_zero));
4536ac495dSmrg     }
4636ac495dSmrg   if (_fex & FP_EX_DIVZERO)
4736ac495dSmrg     {
4836ac495dSmrg       __asm__ __volatile__ ("fdiv %0, %1, %2"
4936ac495dSmrg 			    : "=f" (tmp)
5036ac495dSmrg 			    : "f" (fp_one), "f" (fp_zero));
5136ac495dSmrg     }
5236ac495dSmrg   if (_fex & FP_EX_OVERFLOW)
5336ac495dSmrg     {
5436ac495dSmrg       __asm__ __volatile__ ("fadd %0, %1, %1"
5536ac495dSmrg 			    : "=f" (tmp)
5636ac495dSmrg 			    : "f" (fp_max));
5736ac495dSmrg     }
5836ac495dSmrg   if (_fex & FP_EX_UNDERFLOW)
5936ac495dSmrg     {
6036ac495dSmrg       __asm__ __volatile__ ("fmul %0, %1, %1"
6136ac495dSmrg 			    : "=f" (tmp)
6236ac495dSmrg 			    : "f" (fp_min));
6336ac495dSmrg     }
6436ac495dSmrg   if (_fex & FP_EX_INEXACT)
6536ac495dSmrg     {
6636ac495dSmrg       __asm__ __volatile__ ("fsub %0, %1, %2"
6736ac495dSmrg 			    : "=f" (tmp)
6836ac495dSmrg 			    : "f" (fp_max), "f" (fp_one));
6936ac495dSmrg     }
7036ac495dSmrg }
7136ac495dSmrg 
7236ac495dSmrg #endif	/* !__NO_FPRS__   */
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