13ad841b2Smrg /* Prototypes of memory model helper functions.
2*4c3eb207Smrg Copyright (C) 2011-2020 Free Software Foundation, Inc.
33ad841b2Smrg
43ad841b2Smrg This file is part of GCC.
53ad841b2Smrg
63ad841b2Smrg GCC is free software; you can redistribute it and/or modify it under
73ad841b2Smrg the terms of the GNU General Public License as published by the Free
83ad841b2Smrg Software Foundation; either version 3, or (at your option) any later
93ad841b2Smrg version.
103ad841b2Smrg
113ad841b2Smrg GCC is distributed in the hope that it will be useful, but WITHOUT ANY
123ad841b2Smrg WARRANTY; without even the implied warranty of MERCHANTABILITY or
133ad841b2Smrg FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
143ad841b2Smrg for more details.
153ad841b2Smrg
163ad841b2Smrg You should have received a copy of the GNU General Public License
173ad841b2Smrg along with GCC; see the file COPYING3. If not see
183ad841b2Smrg <http://www.gnu.org/licenses/>. */
193ad841b2Smrg
203ad841b2Smrg #ifndef GCC_MEMMODEL_H
213ad841b2Smrg #define GCC_MEMMODEL_H
223ad841b2Smrg
233ad841b2Smrg /* Suppose that higher bits are target dependent. */
243ad841b2Smrg #define MEMMODEL_MASK ((1<<16)-1)
253ad841b2Smrg
263ad841b2Smrg /* Legacy sync operations set this upper flag in the memory model. This allows
273ad841b2Smrg targets that need to do something stronger for sync operations to
283ad841b2Smrg differentiate with their target patterns and issue a more appropriate insn
293ad841b2Smrg sequence. See bugzilla 65697 for background. */
303ad841b2Smrg #define MEMMODEL_SYNC (1<<15)
313ad841b2Smrg
323ad841b2Smrg /* Memory model without SYNC bit for targets/operations that do not care. */
333ad841b2Smrg #define MEMMODEL_BASE_MASK (MEMMODEL_SYNC-1)
343ad841b2Smrg
353ad841b2Smrg /* Memory model types for the __atomic* builtins.
363ad841b2Smrg This must match the order in libstdc++-v3/include/bits/atomic_base.h. */
373ad841b2Smrg enum memmodel
383ad841b2Smrg {
393ad841b2Smrg MEMMODEL_RELAXED = 0,
403ad841b2Smrg MEMMODEL_CONSUME = 1,
413ad841b2Smrg MEMMODEL_ACQUIRE = 2,
423ad841b2Smrg MEMMODEL_RELEASE = 3,
433ad841b2Smrg MEMMODEL_ACQ_REL = 4,
443ad841b2Smrg MEMMODEL_SEQ_CST = 5,
453ad841b2Smrg MEMMODEL_LAST = 6,
463ad841b2Smrg MEMMODEL_SYNC_ACQUIRE = MEMMODEL_ACQUIRE | MEMMODEL_SYNC,
473ad841b2Smrg MEMMODEL_SYNC_RELEASE = MEMMODEL_RELEASE | MEMMODEL_SYNC,
48cef8759bSmrg MEMMODEL_SYNC_SEQ_CST = MEMMODEL_SEQ_CST | MEMMODEL_SYNC,
49cef8759bSmrg /* Say that all the higher bits are valid target extensions. */
50cef8759bSmrg MEMMODEL_MAX = INTTYPE_MAXIMUM (int)
513ad841b2Smrg };
523ad841b2Smrg
533ad841b2Smrg /* Return the memory model from a host integer. */
543ad841b2Smrg static inline enum memmodel
memmodel_from_int(unsigned HOST_WIDE_INT val)553ad841b2Smrg memmodel_from_int (unsigned HOST_WIDE_INT val)
563ad841b2Smrg {
573ad841b2Smrg return (enum memmodel) (val & MEMMODEL_MASK);
583ad841b2Smrg }
593ad841b2Smrg
603ad841b2Smrg /* Return the base memory model from a host integer. */
613ad841b2Smrg static inline enum memmodel
memmodel_base(unsigned HOST_WIDE_INT val)623ad841b2Smrg memmodel_base (unsigned HOST_WIDE_INT val)
633ad841b2Smrg {
643ad841b2Smrg return (enum memmodel) (val & MEMMODEL_BASE_MASK);
653ad841b2Smrg }
663ad841b2Smrg
673ad841b2Smrg /* Return TRUE if the memory model is RELAXED. */
683ad841b2Smrg static inline bool
is_mm_relaxed(enum memmodel model)693ad841b2Smrg is_mm_relaxed (enum memmodel model)
703ad841b2Smrg {
713ad841b2Smrg return (model & MEMMODEL_BASE_MASK) == MEMMODEL_RELAXED;
723ad841b2Smrg }
733ad841b2Smrg
743ad841b2Smrg /* Return TRUE if the memory model is CONSUME. */
753ad841b2Smrg static inline bool
is_mm_consume(enum memmodel model)763ad841b2Smrg is_mm_consume (enum memmodel model)
773ad841b2Smrg {
783ad841b2Smrg return (model & MEMMODEL_BASE_MASK) == MEMMODEL_CONSUME;
793ad841b2Smrg }
803ad841b2Smrg
813ad841b2Smrg /* Return TRUE if the memory model is ACQUIRE. */
823ad841b2Smrg static inline bool
is_mm_acquire(enum memmodel model)833ad841b2Smrg is_mm_acquire (enum memmodel model)
843ad841b2Smrg {
853ad841b2Smrg return (model & MEMMODEL_BASE_MASK) == MEMMODEL_ACQUIRE;
863ad841b2Smrg }
873ad841b2Smrg
883ad841b2Smrg /* Return TRUE if the memory model is RELEASE. */
893ad841b2Smrg static inline bool
is_mm_release(enum memmodel model)903ad841b2Smrg is_mm_release (enum memmodel model)
913ad841b2Smrg {
923ad841b2Smrg return (model & MEMMODEL_BASE_MASK) == MEMMODEL_RELEASE;
933ad841b2Smrg }
943ad841b2Smrg
953ad841b2Smrg /* Return TRUE if the memory model is ACQ_REL. */
963ad841b2Smrg static inline bool
is_mm_acq_rel(enum memmodel model)973ad841b2Smrg is_mm_acq_rel (enum memmodel model)
983ad841b2Smrg {
993ad841b2Smrg return (model & MEMMODEL_BASE_MASK) == MEMMODEL_ACQ_REL;
1003ad841b2Smrg }
1013ad841b2Smrg
1023ad841b2Smrg /* Return TRUE if the memory model is SEQ_CST. */
1033ad841b2Smrg static inline bool
is_mm_seq_cst(enum memmodel model)1043ad841b2Smrg is_mm_seq_cst (enum memmodel model)
1053ad841b2Smrg {
1063ad841b2Smrg return (model & MEMMODEL_BASE_MASK) == MEMMODEL_SEQ_CST;
1073ad841b2Smrg }
1083ad841b2Smrg
1093ad841b2Smrg /* Return TRUE if the memory model is a SYNC variant. */
1103ad841b2Smrg static inline bool
is_mm_sync(enum memmodel model)1113ad841b2Smrg is_mm_sync (enum memmodel model)
1123ad841b2Smrg {
1133ad841b2Smrg return (model & MEMMODEL_SYNC);
1143ad841b2Smrg }
1153ad841b2Smrg
1163ad841b2Smrg #endif /* GCC_MEMMODEL_H */
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