xref: /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/netbsd-elf.h (revision 8feb0f0b7eaff0608f8350bbfa3098827b4bb91b)
11debfc3dSmrg /* Definitions of target machine for GNU compiler, NetBSD/arm ELF version.
2*8feb0f0bSmrg    Copyright (C) 2002-2020 Free Software Foundation, Inc.
31debfc3dSmrg    Contributed by Wasabi Systems, Inc.
41debfc3dSmrg 
51debfc3dSmrg    This file is part of GCC.
61debfc3dSmrg 
71debfc3dSmrg    GCC is free software; you can redistribute it and/or modify it
81debfc3dSmrg    under the terms of the GNU General Public License as published
91debfc3dSmrg    by the Free Software Foundation; either version 3, or (at your
101debfc3dSmrg    option) any later version.
111debfc3dSmrg 
121debfc3dSmrg    GCC is distributed in the hope that it will be useful, but WITHOUT
131debfc3dSmrg    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
141debfc3dSmrg    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
151debfc3dSmrg    License for more details.
161debfc3dSmrg 
171debfc3dSmrg    Under Section 7 of GPL version 3, you are granted additional
181debfc3dSmrg    permissions described in the GCC Runtime Library Exception, version
191debfc3dSmrg    3.1, as published by the Free Software Foundation.
201debfc3dSmrg 
211debfc3dSmrg    You should have received a copy of the GNU General Public License and
221debfc3dSmrg    a copy of the GCC Runtime Library Exception along with this program;
231debfc3dSmrg    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
241debfc3dSmrg    <http://www.gnu.org/licenses/>.  */
251debfc3dSmrg 
261debfc3dSmrg /* Run-time Target Specification.  */
271debfc3dSmrg 
281debfc3dSmrg /* arm.h defaults to ARM6 CPU.  */
291debfc3dSmrg 
301debfc3dSmrg /* Default EABI to armv5t so that thumb shared libraries work.
311debfc3dSmrg    The ARM926EH-S core is the default for armv5te, so set
321debfc3dSmrg    SUBTARGET_CPU_DEFAULT to achieve this.  */
331debfc3dSmrg 
341debfc3dSmrg #define SUBTARGET_CPU_DEFAULT \
351debfc3dSmrg 	(ARM_DEFAULT_ABI != ARM_ABI_APCS && ARM_DEFAULT_ABI != ARM_ABI_ATPCS \
361debfc3dSmrg 	    ? TARGET_CPU_arm926ejs : TARGET_CPU_arm6)
371debfc3dSmrg 
381debfc3dSmrg /* TARGET_BIG_ENDIAN_DEFAULT is set in
391debfc3dSmrg    config.gcc for big endian configurations.  */
401debfc3dSmrg #if TARGET_BIG_ENDIAN_DEFAULT
411debfc3dSmrg #define TARGET_ENDIAN_DEFAULT    MASK_BIG_END
421debfc3dSmrg #else
431debfc3dSmrg #define TARGET_ENDIAN_DEFAULT    0
441debfc3dSmrg #endif
451debfc3dSmrg 
461debfc3dSmrg #undef MULTILIB_DEFAULTS
471debfc3dSmrg 
481debfc3dSmrg /* Default it to use ATPCS with soft-VFP.  */
491debfc3dSmrg #undef TARGET_DEFAULT
501debfc3dSmrg #define TARGET_DEFAULT			\
511debfc3dSmrg   (MASK_APCS_FRAME			\
521debfc3dSmrg    | TARGET_ENDIAN_DEFAULT)
531debfc3dSmrg 
541debfc3dSmrg #undef ARM_DEFAULT_ABI
551debfc3dSmrg #define ARM_DEFAULT_ABI ARM_ABI_ATPCS
561debfc3dSmrg 
571debfc3dSmrg #undef TARGET_OS_CPP_BUILTINS
581debfc3dSmrg #define TARGET_OS_CPP_BUILTINS()	\
591debfc3dSmrg   do					\
601debfc3dSmrg     {					\
611debfc3dSmrg       NETBSD_OS_CPP_BUILTINS_ELF();	\
621debfc3dSmrg     }					\
631debfc3dSmrg   while (0)
641debfc3dSmrg 
651debfc3dSmrg #undef SUBTARGET_CPP_SPEC
661debfc3dSmrg #define SUBTARGET_CPP_SPEC NETBSD_CPP_SPEC
671debfc3dSmrg 
681debfc3dSmrg #undef SUBTARGET_EXTRA_ASM_SPEC
691debfc3dSmrg #define SUBTARGET_EXTRA_ASM_SPEC	\
70*8feb0f0bSmrg   "-matpcs %{mabi=aapcs*:-meabi=5} "	\
71*8feb0f0bSmrg   "%{" FPIE_OR_FPIC_SPEC ":-k}"
72*8feb0f0bSmrg 
73*8feb0f0bSmrg #undef SUBTARGET_EXTRA_SPECS
74*8feb0f0bSmrg #define SUBTARGET_EXTRA_SPECS					\
75*8feb0f0bSmrg   { "subtarget_extra_asm_spec",	SUBTARGET_EXTRA_ASM_SPEC },	\
76*8feb0f0bSmrg   { "subtarget_asm_float_spec", SUBTARGET_ASM_FLOAT_SPEC },	\
77*8feb0f0bSmrg   NETBSD_SUBTARGET_EXTRA_SPECS
781debfc3dSmrg 
791debfc3dSmrg /* Default to full VFP if -mfloat-abi=hard is specified.  */
801debfc3dSmrg #undef SUBTARGET_ASM_FLOAT_SPEC
811debfc3dSmrg #define SUBTARGET_ASM_FLOAT_SPEC		\
821debfc3dSmrg   "%{mhard-float:%{!mfpu=*:-mfpu=vfp}}		\
831debfc3dSmrg    %{mfloat-abi=hard:%{!mfpu=*:-mfpu=vfp}}"
841debfc3dSmrg 
851debfc3dSmrg #define NETBSD_ENTRY_POINT "__start"
861debfc3dSmrg 
871debfc3dSmrg #undef LINK_SPEC
881debfc3dSmrg #define LINK_SPEC \
891debfc3dSmrg   "-X \
901debfc3dSmrg    %{mbig-endian:-EB %{-mabi=aapcs*:-m armelfb_nbsd_eabi}} \
911debfc3dSmrg    %{mlittle-endian:-EL %{-mabi=aapcs*:-m armelf_nbsd_eabi}} \
921debfc3dSmrg    %(netbsd_link_spec)"
931debfc3dSmrg 
941debfc3dSmrg /* Make GCC agree with <machine/ansi.h>.  */
951debfc3dSmrg 
961debfc3dSmrg #undef SIZE_TYPE
971debfc3dSmrg #define SIZE_TYPE "long unsigned int"
981debfc3dSmrg 
991debfc3dSmrg #undef PTRDIFF_TYPE
1001debfc3dSmrg #define PTRDIFF_TYPE "long int"
1011debfc3dSmrg 
1021debfc3dSmrg #undef INTPTR_TYPE
1031debfc3dSmrg #define INTPTR_TYPE PTRDIFF_TYPE
1041debfc3dSmrg 
1051debfc3dSmrg #undef UINTPTR_TYPE
1061debfc3dSmrg #define UINTPTR_TYPE SIZE_TYPE
1071debfc3dSmrg 
1081debfc3dSmrg /* We don't have any limit on the length as out debugger is GDB.  */
1091debfc3dSmrg #undef DBX_CONTIN_LENGTH
1101debfc3dSmrg 
1111debfc3dSmrg /* NetBSD does its profiling differently to the Acorn compiler. We
1121debfc3dSmrg    don't need a word following the mcount call; and to skip it
1131debfc3dSmrg    requires either an assembly stub or use of fomit-frame-pointer when
1141debfc3dSmrg    compiling the profiling functions.  Since we break Acorn CC
1151debfc3dSmrg    compatibility below a little more won't hurt.  */
1161debfc3dSmrg 
1171debfc3dSmrg #undef ARM_FUNCTION_PROFILER
1181debfc3dSmrg #define ARM_FUNCTION_PROFILER(STREAM,LABELNO)		\
1191debfc3dSmrg {							\
1201debfc3dSmrg   asm_fprintf (STREAM, "\tmov\t%Rip, %Rlr\n");		\
1211debfc3dSmrg   asm_fprintf (STREAM, "\tbl\t__mcount%s\n",		\
1221debfc3dSmrg 	       (TARGET_ARM && NEED_PLT_RELOC)		\
1231debfc3dSmrg 	       ? "(PLT)" : "");				\
1241debfc3dSmrg }
1251debfc3dSmrg 
1261debfc3dSmrg /* VERY BIG NOTE: Change of structure alignment for NetBSD/arm.
1271debfc3dSmrg    There are consequences you should be aware of...
1281debfc3dSmrg 
1291debfc3dSmrg    Normally GCC/arm uses a structure alignment of 32 for compatibility
1301debfc3dSmrg    with armcc.  This means that structures are padded to a word
1311debfc3dSmrg    boundary.  However this causes problems with bugged NetBSD kernel
1321debfc3dSmrg    code (possibly userland code as well - I have not checked every
1331debfc3dSmrg    binary).  The nature of this bugged code is to rely on sizeof()
1341debfc3dSmrg    returning the correct size of various structures rounded to the
1351debfc3dSmrg    nearest byte (SCSI and ether code are two examples, the vm system
1361debfc3dSmrg    is another).  This code breaks when the structure alignment is 32
1371debfc3dSmrg    as sizeof() will report a word=rounded size.  By changing the
1381debfc3dSmrg    structure alignment to 8. GCC will conform to what is expected by
1391debfc3dSmrg    NetBSD.
1401debfc3dSmrg 
1411debfc3dSmrg    This has several side effects that should be considered.
1421debfc3dSmrg    1. Structures will only be aligned to the size of the largest member.
1431debfc3dSmrg       i.e. structures containing only bytes will be byte aligned.
1441debfc3dSmrg 	   structures containing shorts will be half word aligned.
1451debfc3dSmrg 	   structures containing ints will be word aligned.
1461debfc3dSmrg 
1471debfc3dSmrg       This means structures should be padded to a word boundary if
1481debfc3dSmrg       alignment of 32 is required for byte structures etc.
1491debfc3dSmrg 
1501debfc3dSmrg    2. A potential performance penalty may exist if strings are no longer
1511debfc3dSmrg       word aligned.  GCC will not be able to use word load/stores to copy
1521debfc3dSmrg       short strings.
1531debfc3dSmrg 
1541debfc3dSmrg    This modification is not encouraged but with the present state of the
1551debfc3dSmrg    NetBSD source tree it is currently the only solution that meets the
1561debfc3dSmrg    requirements.  */
1571debfc3dSmrg 
1581debfc3dSmrg #undef DEFAULT_STRUCTURE_SIZE_BOUNDARY
1591debfc3dSmrg #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 8
1601debfc3dSmrg 
161*8feb0f0bSmrg #define SYSARCH_ARM_SYNC_ICACHE	0
162*8feb0f0bSmrg 
1631debfc3dSmrg /* Clear the instruction cache from `BEG' to `END'.  This makes a
1641debfc3dSmrg    call to the ARM_SYNC_ICACHE architecture specific syscall.  */
1651debfc3dSmrg #define CLEAR_INSN_CACHE(BEG, END)					\
1661debfc3dSmrg do									\
1671debfc3dSmrg   {									\
1681debfc3dSmrg     extern int sysarch(int number, void *args);				\
1691debfc3dSmrg     struct								\
1701debfc3dSmrg       {									\
1711debfc3dSmrg 	unsigned int addr;						\
1721debfc3dSmrg 	int          len;						\
1731debfc3dSmrg       } s;								\
1741debfc3dSmrg     s.addr = (unsigned int)(BEG);					\
1751debfc3dSmrg     s.len = (END) - (BEG);						\
176*8feb0f0bSmrg     (void) sysarch (SYSARCH_ARM_SYNC_ICACHE, &s);			\
1771debfc3dSmrg   }									\
1781debfc3dSmrg while (0)
179