1 /* tc-m32c.c -- Assembler for the Renesas M32C.
2 Copyright (C) 2005-2022 Free Software Foundation, Inc.
3 Contributed by RedHat.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22 #include "as.h"
23 #include "subsegs.h"
24 #include "symcat.h"
25 #include "opcodes/m32c-desc.h"
26 #include "opcodes/m32c-opc.h"
27 #include "cgen.h"
28 #include "elf/common.h"
29 #include "elf/m32c.h"
30 #include "safe-ctype.h"
31
32 /* Structure to hold all of the different components
33 describing an individual instruction. */
34 typedef struct
35 {
36 const CGEN_INSN * insn;
37 const CGEN_INSN * orig_insn;
38 CGEN_FIELDS fields;
39 #if CGEN_INT_INSN_P
40 CGEN_INSN_INT buffer [1];
41 #define INSN_VALUE(buf) (*(buf))
42 #else
43 unsigned char buffer [CGEN_MAX_INSN_SIZE];
44 #define INSN_VALUE(buf) (buf)
45 #endif
46 char * addr;
47 fragS * frag;
48 int num_fixups;
49 fixS * fixups [GAS_CGEN_MAX_FIXUPS];
50 int indices [MAX_OPERAND_INSTANCES];
51 }
52 m32c_insn;
53
54 #define rl_for(_insn) (CGEN_ATTR_CGEN_INSN_RL_TYPE_VALUE (&((_insn).insn->base->attrs)))
55 #define relaxable(_insn) (CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE (&((_insn).insn->base->attrs)))
56
57 const char comment_chars[] = ";";
58 const char line_comment_chars[] = "#";
59 const char line_separator_chars[] = "|";
60 const char EXP_CHARS[] = "eE";
61 const char FLT_CHARS[] = "dD";
62
63 #define M32C_SHORTOPTS ""
64 const char * md_shortopts = M32C_SHORTOPTS;
65
66 /* assembler options */
67 #define OPTION_CPU_M16C (OPTION_MD_BASE)
68 #define OPTION_CPU_M32C (OPTION_MD_BASE + 1)
69 #define OPTION_LINKRELAX (OPTION_MD_BASE + 2)
70 #define OPTION_H_TICK_HEX (OPTION_MD_BASE + 3)
71
72 struct option md_longopts[] =
73 {
74 { "m16c", no_argument, NULL, OPTION_CPU_M16C },
75 { "m32c", no_argument, NULL, OPTION_CPU_M32C },
76 { "relax", no_argument, NULL, OPTION_LINKRELAX },
77 { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX },
78 {NULL, no_argument, NULL, 0}
79 };
80 size_t md_longopts_size = sizeof (md_longopts);
81
82 /* Default machine */
83
84 #define DEFAULT_MACHINE bfd_mach_m16c
85 #define DEFAULT_FLAGS EF_M32C_CPU_M16C
86
87 static unsigned long m32c_mach = bfd_mach_m16c;
88 static int cpu_mach = (1 << MACH_M16C);
89 static int m32c_relax = 0;
90
91 /* Flags to set in the elf header */
92 static flagword m32c_flags = DEFAULT_FLAGS;
93
94 static char default_isa = 1 << (7 - ISA_M16C);
95 static CGEN_BITSET m32c_isa = {1, & default_isa};
96
97 static void
set_isa(enum isa_attr isa_num)98 set_isa (enum isa_attr isa_num)
99 {
100 cgen_bitset_set (& m32c_isa, isa_num);
101 }
102
103 static void s_bss (int);
104
105 int
md_parse_option(int c,const char * arg ATTRIBUTE_UNUSED)106 md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
107 {
108 switch (c)
109 {
110 case OPTION_CPU_M16C:
111 m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M16C;
112 m32c_mach = bfd_mach_m16c;
113 cpu_mach = (1 << MACH_M16C);
114 set_isa (ISA_M16C);
115 break;
116
117 case OPTION_CPU_M32C:
118 m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M32C;
119 m32c_mach = bfd_mach_m32c;
120 cpu_mach = (1 << MACH_M32C);
121 set_isa (ISA_M32C);
122 break;
123
124 case OPTION_LINKRELAX:
125 m32c_relax = 1;
126 break;
127
128 case OPTION_H_TICK_HEX:
129 enable_h_tick_hex = 1;
130 break;
131
132 default:
133 return 0;
134 }
135 return 1;
136 }
137
138 void
md_show_usage(FILE * stream)139 md_show_usage (FILE * stream)
140 {
141 fprintf (stream, _(" M32C specific command line options:\n"));
142 }
143
144 static void
s_bss(int ignore ATTRIBUTE_UNUSED)145 s_bss (int ignore ATTRIBUTE_UNUSED)
146 {
147 int temp;
148
149 temp = get_absolute_expression ();
150 subseg_set (bss_section, (subsegT) temp);
151 demand_empty_rest_of_line ();
152 }
153
154 /* The target specific pseudo-ops which we support. */
155 const pseudo_typeS md_pseudo_table[] =
156 {
157 { "bss", s_bss, 0},
158 { "3byte", cons, 3 },
159 { "word", cons, 4 },
160 { NULL, NULL, 0 }
161 };
162
163
164 void
md_begin(void)165 md_begin (void)
166 {
167 /* Initialize the `cgen' interface. */
168
169 /* Set the machine number and endian. */
170 gas_cgen_cpu_desc = m32c_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, cpu_mach,
171 CGEN_CPU_OPEN_ENDIAN,
172 CGEN_ENDIAN_BIG,
173 CGEN_CPU_OPEN_ISAS, & m32c_isa,
174 CGEN_CPU_OPEN_END);
175
176 m32c_cgen_init_asm (gas_cgen_cpu_desc);
177
178 /* This is a callback from cgen to gas to parse operands. */
179 cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
180
181 /* Set the ELF flags if desired. */
182 if (m32c_flags)
183 bfd_set_private_flags (stdoutput, m32c_flags);
184
185 /* Set the machine type */
186 bfd_default_set_arch_mach (stdoutput, bfd_arch_m32c, m32c_mach);
187 }
188
189 void
m32c_start_line_hook(void)190 m32c_start_line_hook (void)
191 {
192 #if 0 /* not necessary....handled in the .cpu file */
193 char *s = input_line_pointer;
194 char *sg;
195
196 for (s = input_line_pointer ; s && s[0] != '\n'; s++)
197 {
198 if (s[0] == ':')
199 {
200 /* Remove :g suffix. Squeeze out blanks. */
201 if (s[1] == 'g')
202 {
203 for (sg = s - 1; sg && sg >= input_line_pointer; sg--)
204 {
205 sg[2] = sg[0];
206 }
207 sg[1] = ' ';
208 sg[2] = ' ';
209 input_line_pointer += 2;
210 }
211 }
212 }
213 #endif
214 }
215
216 /* Process [[indirect-operands]] in instruction str. */
217
218 static bool
m32c_indirect_operand(char * str)219 m32c_indirect_operand (char *str)
220 {
221 char *new_str;
222 char *s;
223 char *ns;
224 int ns_len;
225 char *ns_end;
226 enum indirect_type {none, relative, absolute} ;
227 enum indirect_type indirection [3] = { none, none, none };
228 int brace_n [3] = { 0, 0, 0 };
229 int operand;
230
231 s = str;
232 operand = 1;
233 for (s = str; *s; s++)
234 {
235 if (s[0] == ',')
236 operand = 2;
237 /* [abs] where abs is not a0 or a1 */
238 if (s[1] == '[' && ! (s[2] == 'a' && (s[3] == '0' || s[3] == '1'))
239 && (ISBLANK (s[0]) || s[0] == ','))
240 indirection[operand] = absolute;
241 if (s[0] == ']' && s[1] == ']')
242 indirection[operand] = relative;
243 if (s[0] == '[' && s[1] == '[')
244 indirection[operand] = relative;
245 }
246
247 if (indirection[1] == none && indirection[2] == none)
248 return false;
249
250 operand = 1;
251 ns_len = strlen (str);
252 new_str = XNEWVEC (char, ns_len);
253 ns = new_str;
254 ns_end = ns + ns_len;
255
256 for (s = str; *s; s++)
257 {
258 if (s[0] == ',')
259 operand = 2;
260
261 if (s[0] == '[' && ! brace_n[operand])
262 {
263 brace_n[operand] += 1;
264 /* Squeeze [[ to [ if this is an indirect operand. */
265 if (indirection[operand] != none)
266 continue;
267 }
268
269 else if (s[0] == '[' && brace_n[operand])
270 {
271 brace_n[operand] += 1;
272 }
273 else if (s[0] == ']' && s[1] == ']' && indirection[operand] == relative)
274 {
275 s += 1; /* skip one ]. */
276 brace_n[operand] -= 2; /* allow for 2 [. */
277 }
278 else if (s[0] == ']' && indirection[operand] == absolute)
279 {
280 brace_n[operand] -= 1;
281 continue; /* skip closing ]. */
282 }
283 else if (s[0] == ']')
284 {
285 brace_n[operand] -= 1;
286 }
287 *ns = s[0];
288 ns += 1;
289 if (ns >= ns_end)
290 return false;
291 if (s[0] == 0)
292 break;
293 }
294 *ns = '\0';
295 for (operand = 1; operand <= 2; operand++)
296 if (brace_n[operand])
297 {
298 fprintf (stderr, "Unmatched [[operand-%d]] %d\n", operand, brace_n[operand]);
299 }
300
301 if (indirection[1] != none && indirection[2] != none)
302 md_assemble ((char *) "src-dest-indirect");
303 else if (indirection[1] != none)
304 md_assemble ((char *) "src-indirect");
305 else if (indirection[2] != none)
306 md_assemble ((char *) "dest-indirect");
307
308 md_assemble (new_str);
309 free (new_str);
310 return true;
311 }
312
313 void
md_assemble(char * str)314 md_assemble (char * str)
315 {
316 static int last_insn_had_delay_slot = 0;
317 m32c_insn insn;
318 char * errmsg;
319 finished_insnS results;
320 int rl_type;
321 int insn_size;
322
323 if (m32c_mach == bfd_mach_m32c && m32c_indirect_operand (str))
324 return;
325
326 /* Initialize GAS's cgen interface for a new instruction. */
327 gas_cgen_init_parse ();
328
329 insn.insn = m32c_cgen_assemble_insn
330 (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
331
332 if (!insn.insn)
333 {
334 as_bad ("%s", errmsg);
335 return;
336 }
337
338 results.num_fixups = 0;
339 /* Doesn't really matter what we pass for RELAX_P here. */
340 gas_cgen_finish_insn (insn.insn, insn.buffer,
341 CGEN_FIELDS_BITSIZE (& insn.fields), 1, &results);
342
343 last_insn_had_delay_slot
344 = CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT);
345 (void) last_insn_had_delay_slot;
346 insn_size = CGEN_INSN_BITSIZE(insn.insn);
347
348 rl_type = rl_for (insn);
349
350 /* We have to mark all the jumps, because we need to adjust them
351 when we delete bytes, but we only need to mark the displacements
352 if they're symbolic - if they're not, we've already picked the
353 shortest opcode by now. The linker, however, will still have to
354 check any operands to see if they're the displacement type, since
355 we don't know (nor record) *which* operands are relaxable. */
356 if (m32c_relax
357 && rl_type != RL_TYPE_NONE
358 && (rl_type == RL_TYPE_JUMP || results.num_fixups)
359 && !relaxable (insn))
360 {
361 int reloc = 0;
362 int addend = results.num_fixups + 16 * insn_size/8;
363
364 switch (rl_for (insn))
365 {
366 case RL_TYPE_JUMP: reloc = BFD_RELOC_M32C_RL_JUMP; break;
367 case RL_TYPE_1ADDR: reloc = BFD_RELOC_M32C_RL_1ADDR; break;
368 case RL_TYPE_2ADDR: reloc = BFD_RELOC_M32C_RL_2ADDR; break;
369 }
370 if (insn.insn->base->num == M32C_INSN_JMP16_S
371 || insn.insn->base->num == M32C_INSN_JMP32_S)
372 addend = 0x10;
373
374 fix_new (results.frag,
375 results.addr - results.frag->fr_literal,
376 0, abs_section_sym, addend, 0,
377 reloc);
378 }
379 }
380
381 /* The syntax in the manual says constants begin with '#'.
382 We just ignore it. */
383
384 void
md_operand(expressionS * exp)385 md_operand (expressionS * exp)
386 {
387 /* In case of a syntax error, escape back to try next syntax combo. */
388 if (exp->X_op == O_absent)
389 gas_cgen_md_operand (exp);
390 }
391
392 valueT
md_section_align(segT segment,valueT size)393 md_section_align (segT segment, valueT size)
394 {
395 int align = bfd_section_alignment (segment);
396 return ((size + (1 << align) - 1) & -(1 << align));
397 }
398
399 symbolS *
md_undefined_symbol(char * name ATTRIBUTE_UNUSED)400 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
401 {
402 return 0;
403 }
404
405 const relax_typeS md_relax_table[] =
406 {
407 /* The fields are:
408 1) most positive reach of this state,
409 2) most negative reach of this state,
410 3) how many bytes this mode will have in the variable part of the frag
411 4) which index into the table to try if we can't fit into this one. */
412
413 /* 0 */ { 0, 0, 0, 0 }, /* unused */
414 /* 1 */ { 0, 0, 0, 0 }, /* marker for "don't know yet" */
415
416 /* 2 */ { 127, -128, 2, 3 }, /* jcnd16_5.b */
417 /* 3 */ { 32767, -32768, 5, 4 }, /* jcnd16_5.w */
418 /* 4 */ { 0, 0, 6, 0 }, /* jcnd16_5.a */
419
420 /* 5 */ { 127, -128, 2, 6 }, /* jcnd16.b */
421 /* 6 */ { 32767, -32768, 5, 7 }, /* jcnd16.w */
422 /* 7 */ { 0, 0, 6, 0 }, /* jcnd16.a */
423
424 /* 8 */ { 8, 1, 1, 9 }, /* jmp16.s */
425 /* 9 */ { 127, -128, 2, 10 }, /* jmp16.b */
426 /* 10 */ { 32767, -32768, 3, 11 }, /* jmp16.w */
427 /* 11 */ { 0, 0, 4, 0 }, /* jmp16.a */
428
429 /* 12 */ { 127, -128, 2, 13 }, /* jcnd32.b */
430 /* 13 */ { 32767, -32768, 5, 14 }, /* jcnd32.w */
431 /* 14 */ { 0, 0, 6, 0 }, /* jcnd32.a */
432
433 /* 15 */ { 8, 1, 1, 16 }, /* jmp32.s */
434 /* 16 */ { 127, -128, 2, 17 }, /* jmp32.b */
435 /* 17 */ { 32767, -32768, 3, 18 }, /* jmp32.w */
436 /* 18 */ { 0, 0, 4, 0 }, /* jmp32.a */
437
438 /* 19 */ { 32767, -32768, 3, 20 }, /* jsr16.w */
439 /* 20 */ { 0, 0, 4, 0 }, /* jsr16.a */
440 /* 21 */ { 32767, -32768, 3, 11 }, /* jsr32.w */
441 /* 22 */ { 0, 0, 4, 0 }, /* jsr32.a */
442
443 /* 23 */ { 0, 0, 3, 0 }, /* adjnz pc8 */
444 /* 24 */ { 0, 0, 4, 0 }, /* adjnz disp8 pc8 */
445 /* 25 */ { 0, 0, 5, 0 }, /* adjnz disp16 pc8 */
446 /* 26 */ { 0, 0, 6, 0 } /* adjnz disp24 pc8 */
447 };
448
449 enum {
450 M32C_MACRO_JCND16_5_W,
451 M32C_MACRO_JCND16_5_A,
452 M32C_MACRO_JCND16_W,
453 M32C_MACRO_JCND16_A,
454 M32C_MACRO_JCND32_W,
455 M32C_MACRO_JCND32_A,
456 /* the digit is the array index of the pcrel byte */
457 M32C_MACRO_ADJNZ_2,
458 M32C_MACRO_ADJNZ_3,
459 M32C_MACRO_ADJNZ_4,
460 M32C_MACRO_ADJNZ_5,
461 };
462
463 static struct {
464 int insn;
465 int bytes;
466 int insn_for_extern;
467 int pcrel_aim_offset;
468 } subtype_mappings[] = {
469 /* 0 */ { 0, 0, 0, 0 },
470 /* 1 */ { 0, 0, 0, 0 },
471
472 /* 2 */ { M32C_INSN_JCND16_5, 2, -M32C_MACRO_JCND16_5_A, 1 },
473 /* 3 */ { -M32C_MACRO_JCND16_5_W, 5, -M32C_MACRO_JCND16_5_A, 4 },
474 /* 4 */ { -M32C_MACRO_JCND16_5_A, 6, -M32C_MACRO_JCND16_5_A, 0 },
475
476 /* 5 */ { M32C_INSN_JCND16, 3, -M32C_MACRO_JCND16_A, 1 },
477 /* 6 */ { -M32C_MACRO_JCND16_W, 6, -M32C_MACRO_JCND16_A, 4 },
478 /* 7 */ { -M32C_MACRO_JCND16_A, 7, -M32C_MACRO_JCND16_A, 0 },
479
480 /* 8 */ { M32C_INSN_JMP16_S, 1, M32C_INSN_JMP16_A, 0 },
481 /* 9 */ { M32C_INSN_JMP16_B, 2, M32C_INSN_JMP16_A, 1 },
482 /* 10 */ { M32C_INSN_JMP16_W, 3, M32C_INSN_JMP16_A, 2 },
483 /* 11 */ { M32C_INSN_JMP16_A, 4, M32C_INSN_JMP16_A, 0 },
484
485 /* 12 */ { M32C_INSN_JCND32, 2, -M32C_MACRO_JCND32_A, 1 },
486 /* 13 */ { -M32C_MACRO_JCND32_W, 5, -M32C_MACRO_JCND32_A, 4 },
487 /* 14 */ { -M32C_MACRO_JCND32_A, 6, -M32C_MACRO_JCND32_A, 0 },
488
489 /* 15 */ { M32C_INSN_JMP32_S, 1, M32C_INSN_JMP32_A, 0 },
490 /* 16 */ { M32C_INSN_JMP32_B, 2, M32C_INSN_JMP32_A, 1 },
491 /* 17 */ { M32C_INSN_JMP32_W, 3, M32C_INSN_JMP32_A, 2 },
492 /* 18 */ { M32C_INSN_JMP32_A, 4, M32C_INSN_JMP32_A, 0 },
493
494 /* 19 */ { M32C_INSN_JSR16_W, 3, M32C_INSN_JSR16_A, 2 },
495 /* 20 */ { M32C_INSN_JSR16_A, 4, M32C_INSN_JSR16_A, 0 },
496 /* 21 */ { M32C_INSN_JSR32_W, 3, M32C_INSN_JSR32_A, 2 },
497 /* 22 */ { M32C_INSN_JSR32_A, 4, M32C_INSN_JSR32_A, 0 },
498
499 /* 23 */ { -M32C_MACRO_ADJNZ_2, 3, -M32C_MACRO_ADJNZ_2, 0 },
500 /* 24 */ { -M32C_MACRO_ADJNZ_3, 4, -M32C_MACRO_ADJNZ_3, 0 },
501 /* 25 */ { -M32C_MACRO_ADJNZ_4, 5, -M32C_MACRO_ADJNZ_4, 0 },
502 /* 26 */ { -M32C_MACRO_ADJNZ_5, 6, -M32C_MACRO_ADJNZ_5, 0 }
503 };
504 #define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))
505
506 void
m32c_prepare_relax_scan(fragS * fragP,offsetT * aim,relax_substateT this_state)507 m32c_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state)
508 {
509 symbolS *symbolP = fragP->fr_symbol;
510 if (symbolP && !S_IS_DEFINED (symbolP))
511 *aim = 0;
512 /* Adjust for m32c pcrel not being relative to the next opcode. */
513 *aim += subtype_mappings[this_state].pcrel_aim_offset;
514 }
515
516 static int
insn_to_subtype(int inum,const CGEN_INSN * insn)517 insn_to_subtype (int inum, const CGEN_INSN *insn)
518 {
519 unsigned int i;
520
521 if (insn
522 && (startswith (insn->base->mnemonic, "adjnz")
523 || startswith (insn->base->mnemonic, "sbjnz")))
524 {
525 i = 23 + insn->base->bitsize/8 - 3;
526 /*printf("mapping %d used for %s\n", i, insn->base->mnemonic);*/
527 return i;
528 }
529
530 for (i=0; i<NUM_MAPPINGS; i++)
531 if (inum == subtype_mappings[i].insn)
532 {
533 /*printf("mapping %d used\n", i);*/
534 return i;
535 }
536 abort ();
537 }
538
539 /* Return an initial guess of the length by which a fragment must grow to
540 hold a branch to reach its destination.
541 Also updates fr_type/fr_subtype as necessary.
542
543 Called just before doing relaxation.
544 Any symbol that is now undefined will not become defined.
545 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
546 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
547 Although it may not be explicit in the frag, pretend fr_var starts with a
548 0 value. */
549
550 int
md_estimate_size_before_relax(fragS * fragP,segT segment ATTRIBUTE_UNUSED)551 md_estimate_size_before_relax (fragS * fragP, segT segment ATTRIBUTE_UNUSED)
552 {
553 int where = fragP->fr_opcode - fragP->fr_literal;
554
555 if (fragP->fr_subtype == 1)
556 fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num, fragP->fr_cgen.insn);
557
558 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
559 {
560 int new_insn;
561
562 new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern;
563 fragP->fr_subtype = insn_to_subtype (new_insn, 0);
564 }
565
566 if (fragP->fr_cgen.insn->base
567 && fragP->fr_cgen.insn->base->num
568 != subtype_mappings[fragP->fr_subtype].insn
569 && subtype_mappings[fragP->fr_subtype].insn > 0)
570 {
571 int new_insn= subtype_mappings[fragP->fr_subtype].insn;
572 if (new_insn >= 0)
573 {
574 fragP->fr_cgen.insn = (fragP->fr_cgen.insn
575 - fragP->fr_cgen.insn->base->num
576 + new_insn);
577 }
578 }
579
580 return subtype_mappings[fragP->fr_subtype].bytes - (fragP->fr_fix - where);
581 }
582
583 /* *fragP has been relaxed to its final size, and now needs to have
584 the bytes inside it modified to conform to the new size.
585
586 Called after relaxation is finished.
587 fragP->fr_type == rs_machine_dependent.
588 fragP->fr_subtype is the subtype of what the address relaxed to. */
589
590 static int
target_address_for(fragS * frag)591 target_address_for (fragS *frag)
592 {
593 int rv = frag->fr_offset;
594 symbolS *sym = frag->fr_symbol;
595
596 if (sym)
597 rv += S_GET_VALUE (sym);
598
599 /*printf("target_address_for returns %d\n", rv);*/
600 return rv;
601 }
602
603 void
md_convert_frag(bfd * abfd ATTRIBUTE_UNUSED,segT sec ATTRIBUTE_UNUSED,fragS * fragP ATTRIBUTE_UNUSED)604 md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
605 segT sec ATTRIBUTE_UNUSED,
606 fragS * fragP ATTRIBUTE_UNUSED)
607 {
608 int addend;
609 int operand;
610 int where = fragP->fr_opcode - fragP->fr_literal;
611 int rl_where = fragP->fr_opcode - fragP->fr_literal;
612 unsigned char *op = (unsigned char *)fragP->fr_opcode;
613 int rl_addend = 0;
614
615 addend = target_address_for (fragP) - (fragP->fr_address + where);
616
617 fragP->fr_fix = where + subtype_mappings[fragP->fr_subtype].bytes;
618
619 switch (subtype_mappings[fragP->fr_subtype].insn)
620 {
621 case M32C_INSN_JCND16_5:
622 op[1] = addend - 1;
623 operand = M32C_OPERAND_LAB_8_8;
624 rl_addend = 0x21;
625 break;
626
627 case -M32C_MACRO_JCND16_5_W:
628 op[0] ^= 0x04;
629 op[1] = 4;
630 op[2] = 0xf4;
631 op[3] = addend - 3;
632 op[4] = (addend - 3) >> 8;
633 operand = M32C_OPERAND_LAB_8_16;
634 where += 2;
635 rl_addend = 0x51;
636 break;
637
638 case -M32C_MACRO_JCND16_5_A:
639 op[0] ^= 0x04;
640 op[1] = 5;
641 op[2] = 0xfc;
642 operand = M32C_OPERAND_LAB_8_24;
643 where += 2;
644 rl_addend = 0x61;
645 break;
646
647
648 case M32C_INSN_JCND16:
649 op[2] = addend - 2;
650 operand = M32C_OPERAND_LAB_16_8;
651 rl_addend = 0x31;
652 break;
653
654 case -M32C_MACRO_JCND16_W:
655 op[1] ^= 0x04;
656 op[2] = 4;
657 op[3] = 0xf4;
658 op[4] = addend - 4;
659 op[5] = (addend - 4) >> 8;
660 operand = M32C_OPERAND_LAB_8_16;
661 where += 3;
662 rl_addend = 0x61;
663 break;
664
665 case -M32C_MACRO_JCND16_A:
666 op[1] ^= 0x04;
667 op[2] = 5;
668 op[3] = 0xfc;
669 operand = M32C_OPERAND_LAB_8_24;
670 where += 3;
671 rl_addend = 0x71;
672 break;
673
674 case M32C_INSN_JMP16_S:
675 op[0] = 0x60 | ((addend-2) & 0x07);
676 operand = M32C_OPERAND_LAB_5_3;
677 rl_addend = 0x10;
678 break;
679
680 case M32C_INSN_JMP16_B:
681 op[0] = 0xfe;
682 op[1] = addend - 1;
683 operand = M32C_OPERAND_LAB_8_8;
684 rl_addend = 0x21;
685 break;
686
687 case M32C_INSN_JMP16_W:
688 op[0] = 0xf4;
689 op[1] = addend - 1;
690 op[2] = (addend - 1) >> 8;
691 operand = M32C_OPERAND_LAB_8_16;
692 rl_addend = 0x31;
693 break;
694
695 case M32C_INSN_JMP16_A:
696 op[0] = 0xfc;
697 op[1] = 0;
698 op[2] = 0;
699 op[3] = 0;
700 operand = M32C_OPERAND_LAB_8_24;
701 rl_addend = 0x41;
702 break;
703
704 case M32C_INSN_JCND32:
705 op[1] = addend - 1;
706 operand = M32C_OPERAND_LAB_8_8;
707 rl_addend = 0x21;
708 break;
709
710 case -M32C_MACRO_JCND32_W:
711 op[0] ^= 0x40;
712 op[1] = 4;
713 op[2] = 0xce;
714 op[3] = addend - 3;
715 op[4] = (addend - 3) >> 8;
716 operand = M32C_OPERAND_LAB_8_16;
717 where += 2;
718 rl_addend = 0x51;
719 break;
720
721 case -M32C_MACRO_JCND32_A:
722 op[0] ^= 0x40;
723 op[1] = 5;
724 op[2] = 0xcc;
725 operand = M32C_OPERAND_LAB_8_24;
726 where += 2;
727 rl_addend = 0x61;
728 break;
729
730 case M32C_INSN_JMP32_S:
731 addend = ((addend-2) & 0x07);
732 op[0] = 0x4a | (addend & 0x01) | ((addend << 3) & 0x30);
733 operand = M32C_OPERAND_LAB32_JMP_S;
734 rl_addend = 0x10;
735 break;
736
737 case M32C_INSN_JMP32_B:
738 op[0] = 0xbb;
739 op[1] = addend - 1;
740 operand = M32C_OPERAND_LAB_8_8;
741 rl_addend = 0x21;
742 break;
743
744 case M32C_INSN_JMP32_W:
745 op[0] = 0xce;
746 op[1] = addend - 1;
747 op[2] = (addend - 1) >> 8;
748 operand = M32C_OPERAND_LAB_8_16;
749 rl_addend = 0x31;
750 break;
751
752 case M32C_INSN_JMP32_A:
753 op[0] = 0xcc;
754 op[1] = 0;
755 op[2] = 0;
756 op[3] = 0;
757 operand = M32C_OPERAND_LAB_8_24;
758 rl_addend = 0x41;
759 break;
760
761
762 case M32C_INSN_JSR16_W:
763 op[0] = 0xf5;
764 op[1] = addend - 1;
765 op[2] = (addend - 1) >> 8;
766 operand = M32C_OPERAND_LAB_8_16;
767 rl_addend = 0x31;
768 break;
769
770 case M32C_INSN_JSR16_A:
771 op[0] = 0xfd;
772 op[1] = 0;
773 op[2] = 0;
774 op[3] = 0;
775 operand = M32C_OPERAND_LAB_8_24;
776 rl_addend = 0x41;
777 break;
778
779 case M32C_INSN_JSR32_W:
780 op[0] = 0xcf;
781 op[1] = addend - 1;
782 op[2] = (addend - 1) >> 8;
783 operand = M32C_OPERAND_LAB_8_16;
784 rl_addend = 0x31;
785 break;
786
787 case M32C_INSN_JSR32_A:
788 op[0] = 0xcd;
789 op[1] = 0;
790 op[2] = 0;
791 op[3] = 0;
792 operand = M32C_OPERAND_LAB_8_24;
793 rl_addend = 0x41;
794 break;
795
796 case -M32C_MACRO_ADJNZ_2:
797 rl_addend = 0x31;
798 op[2] = addend - 2;
799 operand = M32C_OPERAND_LAB_16_8;
800 break;
801 case -M32C_MACRO_ADJNZ_3:
802 rl_addend = 0x41;
803 op[3] = addend - 2;
804 operand = M32C_OPERAND_LAB_24_8;
805 break;
806 case -M32C_MACRO_ADJNZ_4:
807 rl_addend = 0x51;
808 op[4] = addend - 2;
809 operand = M32C_OPERAND_LAB_32_8;
810 break;
811 case -M32C_MACRO_ADJNZ_5:
812 rl_addend = 0x61;
813 op[5] = addend - 2;
814 operand = M32C_OPERAND_LAB_40_8;
815 break;
816
817 default:
818 printf("\nHey! Need more opcode converters! missing: %d %s\n\n",
819 fragP->fr_subtype,
820 fragP->fr_cgen.insn->base->name);
821 abort();
822 }
823
824 if (m32c_relax)
825 {
826 if (operand != M32C_OPERAND_LAB_8_24)
827 fragP->fr_offset = (fragP->fr_address + where);
828
829 fix_new (fragP,
830 rl_where,
831 0, abs_section_sym, rl_addend, 0,
832 BFD_RELOC_M32C_RL_JUMP);
833 }
834
835 if (S_GET_SEGMENT (fragP->fr_symbol) != sec
836 || operand == M32C_OPERAND_LAB_8_24
837 || (m32c_relax && (operand != M32C_OPERAND_LAB_5_3
838 && operand != M32C_OPERAND_LAB32_JMP_S)))
839 {
840 gas_assert (fragP->fr_cgen.insn != 0);
841 gas_cgen_record_fixup (fragP,
842 where,
843 fragP->fr_cgen.insn,
844 (fragP->fr_fix - where) * 8,
845 cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
846 operand),
847 fragP->fr_cgen.opinfo,
848 fragP->fr_symbol,
849 fragP->fr_offset);
850 }
851 }
852
853 /* Functions concerning relocs. */
854
855 /* The location from which a PC relative jump should be calculated,
856 given a PC relative reloc. */
857
858 long
md_pcrel_from_section(fixS * fixP,segT sec)859 md_pcrel_from_section (fixS * fixP, segT sec)
860 {
861 if (fixP->fx_addsy != (symbolS *) NULL
862 && (! S_IS_DEFINED (fixP->fx_addsy)
863 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
864 /* The symbol is undefined (or is defined but not in this section).
865 Let the linker figure it out. */
866 return 0;
867
868 return (fixP->fx_frag->fr_address + fixP->fx_where);
869 }
870
871 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
872 Returns BFD_RELOC_NONE if no reloc type can be found.
873 *FIXP may be modified if desired. */
874
875 bfd_reloc_code_real_type
md_cgen_lookup_reloc(const CGEN_INSN * insn ATTRIBUTE_UNUSED,const CGEN_OPERAND * operand,fixS * fixP ATTRIBUTE_UNUSED)876 md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED,
877 const CGEN_OPERAND * operand,
878 fixS * fixP ATTRIBUTE_UNUSED)
879 {
880 static const struct op_reloc {
881 /* A CGEN operand type that can be a relocatable expression. */
882 CGEN_OPERAND_TYPE operand;
883
884 /* The appropriate BFD reloc type to use for that. */
885 bfd_reloc_code_real_type reloc;
886
887 /* The offset from the start of the instruction to the field to be
888 relocated, in bytes. */
889 int offset;
890 } op_reloc_table[] = {
891
892 /* PC-REL relocs for 8-bit fields. */
893 { M32C_OPERAND_LAB_8_8, BFD_RELOC_8_PCREL, 1 },
894 { M32C_OPERAND_LAB_16_8, BFD_RELOC_8_PCREL, 2 },
895 { M32C_OPERAND_LAB_24_8, BFD_RELOC_8_PCREL, 3 },
896 { M32C_OPERAND_LAB_32_8, BFD_RELOC_8_PCREL, 4 },
897 { M32C_OPERAND_LAB_40_8, BFD_RELOC_8_PCREL, 5 },
898
899 /* PC-REL relocs for 16-bit fields. */
900 { M32C_OPERAND_LAB_8_16, BFD_RELOC_16_PCREL, 1 },
901
902 /* Absolute relocs for 8-bit fields. */
903 { M32C_OPERAND_IMM_8_QI, BFD_RELOC_8, 1 },
904 { M32C_OPERAND_IMM_16_QI, BFD_RELOC_8, 2 },
905 { M32C_OPERAND_IMM_24_QI, BFD_RELOC_8, 3 },
906 { M32C_OPERAND_IMM_32_QI, BFD_RELOC_8, 4 },
907 { M32C_OPERAND_IMM_40_QI, BFD_RELOC_8, 5 },
908 { M32C_OPERAND_IMM_48_QI, BFD_RELOC_8, 6 },
909 { M32C_OPERAND_IMM_56_QI, BFD_RELOC_8, 7 },
910 { M32C_OPERAND_DSP_8_S8, BFD_RELOC_8, 1 },
911 { M32C_OPERAND_DSP_16_S8, BFD_RELOC_8, 2 },
912 { M32C_OPERAND_DSP_24_S8, BFD_RELOC_8, 3 },
913 { M32C_OPERAND_DSP_32_S8, BFD_RELOC_8, 4 },
914 { M32C_OPERAND_DSP_40_S8, BFD_RELOC_8, 5 },
915 { M32C_OPERAND_DSP_48_S8, BFD_RELOC_8, 6 },
916 { M32C_OPERAND_DSP_8_U8, BFD_RELOC_8, 1 },
917 { M32C_OPERAND_DSP_16_U8, BFD_RELOC_8, 2 },
918 { M32C_OPERAND_DSP_24_U8, BFD_RELOC_8, 3 },
919 { M32C_OPERAND_DSP_32_U8, BFD_RELOC_8, 4 },
920 { M32C_OPERAND_DSP_40_U8, BFD_RELOC_8, 5 },
921 { M32C_OPERAND_DSP_48_U8, BFD_RELOC_8, 6 },
922 { M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, BFD_RELOC_8, 2 },
923 { M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, BFD_RELOC_8, 2 },
924 { M32C_OPERAND_BITBASE32_24_S11_PREFIXED, BFD_RELOC_8, 3 },
925 { M32C_OPERAND_BITBASE32_24_U11_PREFIXED, BFD_RELOC_8, 3 },
926
927 /* Absolute relocs for 16-bit fields. */
928 { M32C_OPERAND_IMM_8_HI, BFD_RELOC_16, 1 },
929 { M32C_OPERAND_IMM_16_HI, BFD_RELOC_16, 2 },
930 { M32C_OPERAND_IMM_24_HI, BFD_RELOC_16, 3 },
931 { M32C_OPERAND_IMM_32_HI, BFD_RELOC_16, 4 },
932 { M32C_OPERAND_IMM_40_HI, BFD_RELOC_16, 5 },
933 { M32C_OPERAND_IMM_48_HI, BFD_RELOC_16, 6 },
934 { M32C_OPERAND_IMM_56_HI, BFD_RELOC_16, 7 },
935 { M32C_OPERAND_IMM_64_HI, BFD_RELOC_16, 8 },
936 { M32C_OPERAND_DSP_16_S16, BFD_RELOC_16, 2 },
937 { M32C_OPERAND_DSP_24_S16, BFD_RELOC_16, 3 },
938 { M32C_OPERAND_DSP_32_S16, BFD_RELOC_16, 4 },
939 { M32C_OPERAND_DSP_40_S16, BFD_RELOC_16, 5 },
940 { M32C_OPERAND_DSP_8_U16, BFD_RELOC_16, 1 },
941 { M32C_OPERAND_DSP_16_U16, BFD_RELOC_16, 2 },
942 { M32C_OPERAND_DSP_24_U16, BFD_RELOC_16, 3 },
943 { M32C_OPERAND_DSP_32_U16, BFD_RELOC_16, 4 },
944 { M32C_OPERAND_DSP_40_U16, BFD_RELOC_16, 5 },
945 { M32C_OPERAND_DSP_48_U16, BFD_RELOC_16, 6 },
946 { M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, BFD_RELOC_16, 2 },
947 { M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, BFD_RELOC_16, 2 },
948 { M32C_OPERAND_BITBASE32_24_S19_PREFIXED, BFD_RELOC_16, 3 },
949 { M32C_OPERAND_BITBASE32_24_U19_PREFIXED, BFD_RELOC_16, 3 },
950
951 /* Absolute relocs for 24-bit fields. */
952 { M32C_OPERAND_LAB_8_24, BFD_RELOC_24, 1 },
953 { M32C_OPERAND_DSP_8_S24, BFD_RELOC_24, 1 },
954 { M32C_OPERAND_DSP_8_U24, BFD_RELOC_24, 1 },
955 { M32C_OPERAND_DSP_16_U24, BFD_RELOC_24, 2 },
956 { M32C_OPERAND_DSP_24_U24, BFD_RELOC_24, 3 },
957 { M32C_OPERAND_DSP_32_U24, BFD_RELOC_24, 4 },
958 { M32C_OPERAND_DSP_40_U24, BFD_RELOC_24, 5 },
959 { M32C_OPERAND_DSP_48_U24, BFD_RELOC_24, 6 },
960 { M32C_OPERAND_DSP_16_U20, BFD_RELOC_24, 2 },
961 { M32C_OPERAND_DSP_24_U20, BFD_RELOC_24, 3 },
962 { M32C_OPERAND_DSP_32_U20, BFD_RELOC_24, 4 },
963 { M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, BFD_RELOC_24, 2 },
964 { M32C_OPERAND_BITBASE32_24_U27_PREFIXED, BFD_RELOC_24, 3 },
965
966 /* Absolute relocs for 32-bit fields. */
967 { M32C_OPERAND_IMM_16_SI, BFD_RELOC_32, 2 },
968 { M32C_OPERAND_IMM_24_SI, BFD_RELOC_32, 3 },
969 { M32C_OPERAND_IMM_32_SI, BFD_RELOC_32, 4 },
970 { M32C_OPERAND_IMM_40_SI, BFD_RELOC_32, 5 },
971
972 };
973
974 int i;
975
976 for (i = ARRAY_SIZE (op_reloc_table); --i >= 0; )
977 {
978 const struct op_reloc *or = &op_reloc_table[i];
979
980 if (or->operand == operand->type)
981 {
982 fixP->fx_where += or->offset;
983 fixP->fx_size -= or->offset;
984
985 if (fixP->fx_cgen.opinfo
986 && fixP->fx_cgen.opinfo != BFD_RELOC_NONE)
987 return fixP->fx_cgen.opinfo;
988
989 return or->reloc;
990 }
991 }
992
993 fprintf
994 (stderr,
995 "Error: tc-m32c.c:md_cgen_lookup_reloc Unimplemented relocation for operand %s\n",
996 operand->name);
997
998 return BFD_RELOC_NONE;
999 }
1000
1001 void
m32c_cons_fix_new(fragS * frag,int where,int size,expressionS * exp,bfd_reloc_code_real_type type)1002 m32c_cons_fix_new (fragS * frag,
1003 int where,
1004 int size,
1005 expressionS *exp,
1006 bfd_reloc_code_real_type type)
1007 {
1008 switch (size)
1009 {
1010 case 1:
1011 type = BFD_RELOC_8;
1012 break;
1013 case 2:
1014 type = BFD_RELOC_16;
1015 break;
1016 case 3:
1017 type = BFD_RELOC_24;
1018 break;
1019 case 4:
1020 default:
1021 type = BFD_RELOC_32;
1022 break;
1023 case 8:
1024 type = BFD_RELOC_64;
1025 break;
1026 }
1027
1028 fix_new_exp (frag, where, (int) size, exp, 0, type);
1029 }
1030
1031 void
m32c_apply_fix(struct fix * f,valueT * t,segT s)1032 m32c_apply_fix (struct fix *f, valueT *t, segT s)
1033 {
1034 if (f->fx_r_type == BFD_RELOC_M32C_RL_JUMP
1035 || f->fx_r_type == BFD_RELOC_M32C_RL_1ADDR
1036 || f->fx_r_type == BFD_RELOC_M32C_RL_2ADDR)
1037 return;
1038 gas_cgen_md_apply_fix (f, t, s);
1039 }
1040
1041 arelent *
tc_gen_reloc(asection * sec,fixS * fx)1042 tc_gen_reloc (asection *sec, fixS *fx)
1043 {
1044 if (fx->fx_r_type == BFD_RELOC_M32C_RL_JUMP
1045 || fx->fx_r_type == BFD_RELOC_M32C_RL_1ADDR
1046 || fx->fx_r_type == BFD_RELOC_M32C_RL_2ADDR)
1047 {
1048 arelent * reloc;
1049
1050 reloc = XNEW (arelent);
1051
1052 reloc->sym_ptr_ptr = XNEW (asymbol *);
1053 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fx->fx_addsy);
1054 reloc->address = fx->fx_frag->fr_address + fx->fx_where;
1055 reloc->howto = bfd_reloc_type_lookup (stdoutput, fx->fx_r_type);
1056 reloc->addend = fx->fx_offset;
1057 return reloc;
1058
1059 }
1060 return gas_cgen_tc_gen_reloc (sec, fx);
1061 }
1062
1063 /* See whether we need to force a relocation into the output file.
1064 This is used to force out switch and PC relative relocations when
1065 relaxing. */
1066
1067 int
m32c_force_relocation(fixS * fixp)1068 m32c_force_relocation (fixS * fixp)
1069 {
1070 int reloc = fixp->fx_r_type;
1071
1072 if (reloc > (int)BFD_RELOC_UNUSED)
1073 {
1074 reloc -= (int)BFD_RELOC_UNUSED;
1075 switch (reloc)
1076 {
1077 case M32C_OPERAND_DSP_32_S16:
1078 case M32C_OPERAND_DSP_32_U16:
1079 case M32C_OPERAND_IMM_32_HI:
1080 case M32C_OPERAND_DSP_16_S16:
1081 case M32C_OPERAND_DSP_16_U16:
1082 case M32C_OPERAND_IMM_16_HI:
1083 case M32C_OPERAND_DSP_24_S16:
1084 case M32C_OPERAND_DSP_24_U16:
1085 case M32C_OPERAND_IMM_24_HI:
1086 return 1;
1087
1088 /* If we're doing linker relaxing, we need to keep all the
1089 pc-relative jumps in case we need to fix them due to
1090 deleted bytes between the jump and its destination. */
1091 case M32C_OPERAND_LAB_8_8:
1092 case M32C_OPERAND_LAB_8_16:
1093 case M32C_OPERAND_LAB_8_24:
1094 case M32C_OPERAND_LAB_16_8:
1095 case M32C_OPERAND_LAB_24_8:
1096 case M32C_OPERAND_LAB_32_8:
1097 case M32C_OPERAND_LAB_40_8:
1098 if (m32c_relax)
1099 return 1;
1100 default:
1101 break;
1102 }
1103 }
1104 else
1105 {
1106 switch (fixp->fx_r_type)
1107 {
1108 case BFD_RELOC_16:
1109 return 1;
1110
1111 case BFD_RELOC_M32C_RL_JUMP:
1112 case BFD_RELOC_M32C_RL_1ADDR:
1113 case BFD_RELOC_M32C_RL_2ADDR:
1114 case BFD_RELOC_8_PCREL:
1115 case BFD_RELOC_16_PCREL:
1116 if (m32c_relax)
1117 return 1;
1118 default:
1119 break;
1120 }
1121 }
1122
1123 return generic_force_reloc (fixp);
1124 }
1125
1126 /* Write a value out to the object file, using the appropriate endianness. */
1127
1128 void
md_number_to_chars(char * buf,valueT val,int n)1129 md_number_to_chars (char * buf, valueT val, int n)
1130 {
1131 number_to_chars_littleendian (buf, val, n);
1132 }
1133
1134 /* Turn a string in input_line_pointer into a floating point constant of type
1135 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1136 emitted is stored in *sizeP . An error message is returned, or NULL on OK. */
1137
1138 const char *
md_atof(int type,char * litP,int * sizeP)1139 md_atof (int type, char * litP, int * sizeP)
1140 {
1141 return ieee_md_atof (type, litP, sizeP, true);
1142 }
1143
1144 bool
m32c_fix_adjustable(fixS * fixP)1145 m32c_fix_adjustable (fixS * fixP)
1146 {
1147 int reloc;
1148 if (fixP->fx_addsy == NULL)
1149 return 1;
1150
1151 /* We need the symbol name for the VTABLE entries. */
1152 reloc = fixP->fx_r_type;
1153 if (reloc > (int)BFD_RELOC_UNUSED)
1154 {
1155 reloc -= (int)BFD_RELOC_UNUSED;
1156 switch (reloc)
1157 {
1158 case M32C_OPERAND_DSP_32_S16:
1159 case M32C_OPERAND_DSP_32_U16:
1160 case M32C_OPERAND_IMM_32_HI:
1161 case M32C_OPERAND_DSP_16_S16:
1162 case M32C_OPERAND_DSP_16_U16:
1163 case M32C_OPERAND_IMM_16_HI:
1164 case M32C_OPERAND_DSP_24_S16:
1165 case M32C_OPERAND_DSP_24_U16:
1166 case M32C_OPERAND_IMM_24_HI:
1167 return 0;
1168 }
1169 }
1170 else
1171 {
1172 if (fixP->fx_r_type == BFD_RELOC_16)
1173 return 0;
1174 }
1175
1176 /* Do not adjust relocations involving symbols in merged sections.
1177
1178 A reloc patching in the value of some symbol S plus some addend A
1179 can be produced in different ways:
1180
1181 1) It might simply be a reference to the data at S + A. Clearly,
1182 if linker merging shift that data around, the value patched in
1183 by the reloc needs to be adjusted accordingly.
1184
1185 2) Or, it might be a reference to S, with A added in as a constant
1186 bias. For example, given code like this:
1187
1188 static int S[100];
1189
1190 ... S[i - 8] ...
1191
1192 it would be reasonable for the compiler to rearrange the array
1193 reference to something like:
1194
1195 ... (S-8)[i] ...
1196
1197 and emit assembly code that refers to S - (8 * sizeof (int)),
1198 so the subtraction is done entirely at compile-time. In this
1199 case, the reloc's addend A would be -(8 * sizeof (int)), and
1200 shifting around code or data at S + A should not affect the
1201 reloc: the reloc isn't referring to that code or data at all.
1202
1203 The linker has no way of knowing which case it has in hand. So,
1204 to disambiguate, we have the linker always treat reloc addends as
1205 in case 2): they're constants that should be simply added to the
1206 symbol value, just like the reloc says. And we express case 1)
1207 in different way: we have the compiler place a label at the real
1208 target, and reference that label with an addend of zero. (The
1209 compiler is unlikely to reference code using a label plus an
1210 offset anyway, since it doesn't know the sizes of the
1211 instructions.)
1212
1213 The simplification being done by gas/write.c:adjust_reloc_syms,
1214 however, turns the explicit-label usage into the label-plus-
1215 offset usage, re-introducing the ambiguity the compiler avoided.
1216 So we need to disable that simplification for symbols referring
1217 to merged data.
1218
1219 This only affects object size a little bit. */
1220 if (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE)
1221 return 0;
1222
1223 if (m32c_relax)
1224 return 0;
1225
1226 return 1;
1227 }
1228
1229 /* Worker function for m32c_is_colon_insn(). */
1230 static int
restore_colon(char * next_i_l_p,char * nul_char)1231 restore_colon (char *next_i_l_p, char *nul_char)
1232 {
1233 /* Restore the colon, and advance input_line_pointer to
1234 the end of the new symbol. */
1235 *input_line_pointer = *nul_char;
1236 input_line_pointer = next_i_l_p;
1237 *nul_char = *next_i_l_p;
1238 *next_i_l_p = 0;
1239 return 1;
1240 }
1241
1242 /* Determines if the symbol starting at START and ending in
1243 a colon that was at the location pointed to by INPUT_LINE_POINTER
1244 (but which has now been replaced bu a NUL) is in fact an
1245 :Z, :S, :Q, or :G suffix.
1246 If it is, then it restores the colon, advances INPUT_LINE_POINTER
1247 to the real end of the instruction/symbol, saves the char there to
1248 NUL_CHAR and pokes a NUL, and returns 1. Otherwise it returns 0. */
1249 int
m32c_is_colon_insn(char * start ATTRIBUTE_UNUSED,char * nul_char)1250 m32c_is_colon_insn (char *start ATTRIBUTE_UNUSED, char *nul_char)
1251 {
1252 char * i_l_p = input_line_pointer;
1253
1254 if (*nul_char == '"')
1255 ++i_l_p;
1256
1257 /* Check to see if the text following the colon is 'G' */
1258 if (TOLOWER (i_l_p[1]) == 'g' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1259 return restore_colon (i_l_p + 2, nul_char);
1260
1261 /* Check to see if the text following the colon is 'Q' */
1262 if (TOLOWER (i_l_p[1]) == 'q' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1263 return restore_colon (i_l_p + 2, nul_char);
1264
1265 /* Check to see if the text following the colon is 'S' */
1266 if (TOLOWER (i_l_p[1]) == 's' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1267 return restore_colon (i_l_p + 2, nul_char);
1268
1269 /* Check to see if the text following the colon is 'Z' */
1270 if (TOLOWER (i_l_p[1]) == 'z' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1271 return restore_colon (i_l_p + 2, nul_char);
1272
1273 return 0;
1274 }
1275