17330f729Sjoerg//===-- X86InstrVMX.td - TSX Instruction Set Extension -----*- tablegen -*-===// 27330f729Sjoerg// 37330f729Sjoerg// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 47330f729Sjoerg// See https://llvm.org/LICENSE.txt for license information. 57330f729Sjoerg// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 67330f729Sjoerg// 77330f729Sjoerg//===----------------------------------------------------------------------===// 87330f729Sjoerg// 97330f729Sjoerg// This file describes the instructions that make up the Intel TSX instruction 107330f729Sjoerg// set. 117330f729Sjoerg// 127330f729Sjoerg//===----------------------------------------------------------------------===// 137330f729Sjoerg 147330f729Sjoerg//===----------------------------------------------------------------------===// 157330f729Sjoerg// TSX instructions 167330f729Sjoerg 177330f729Sjoergdef X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>, 187330f729Sjoerg [SDNPHasChain, SDNPSideEffect]>; 197330f729Sjoerg 207330f729Sjoerglet SchedRW = [WriteSystem] in { 217330f729Sjoerg 227330f729Sjoerglet usesCustomInserter = 1 in 237330f729Sjoergdef XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins), 247330f729Sjoerg "# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>, 257330f729Sjoerg Requires<[HasRTM]>; 267330f729Sjoerg 277330f729Sjoerglet isBranch = 1, isTerminator = 1, Defs = [EAX] in { 287330f729Sjoergdef XBEGIN_2 : Ii16PCRel<0xc7, MRM_F8, (outs), (ins brtarget16:$dst), 297330f729Sjoerg "xbegin\t$dst", []>, OpSize16; 307330f729Sjoergdef XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget32:$dst), 317330f729Sjoerg "xbegin\t$dst", []>, OpSize32; 327330f729Sjoerg} 337330f729Sjoerg 34*82d56013Sjoerg// Pseudo instruction to fake the definition of EAX on the fallback code path. 357330f729Sjoerglet isPseudo = 1, Defs = [EAX] in { 367330f729Sjoergdef XABORT_DEF : I<0, Pseudo, (outs), (ins), "# XABORT DEF", []>; 377330f729Sjoerg} 387330f729Sjoerg 397330f729Sjoergdef XEND : I<0x01, MRM_D5, (outs), (ins), 40*82d56013Sjoerg "xend", [(int_x86_xend)]>, PS, Requires<[HasRTM]>; 417330f729Sjoerg 427330f729Sjoerglet Defs = [EFLAGS] in 437330f729Sjoergdef XTEST : I<0x01, MRM_D6, (outs), (ins), 44*82d56013Sjoerg "xtest", [(set EFLAGS, (X86xtest))]>, PS, Requires<[HasRTM]>; 457330f729Sjoerg 467330f729Sjoergdef XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm), 477330f729Sjoerg "xabort\t$imm", 487330f729Sjoerg [(int_x86_xabort timm:$imm)]>, Requires<[HasRTM]>; 497330f729Sjoerg} // SchedRW 507330f729Sjoerg 517330f729Sjoerg// HLE prefixes 527330f729Sjoerglet SchedRW = [WriteSystem] in { 537330f729Sjoerg 547330f729Sjoerglet isAsmParserOnly = 1 in { 55*82d56013Sjoergdef XACQUIRE_PREFIX : I<0xF2, PrefixByte, (outs), (ins), "xacquire", []>; 56*82d56013Sjoergdef XRELEASE_PREFIX : I<0xF3, PrefixByte, (outs), (ins), "xrelease", []>; 577330f729Sjoerg} 587330f729Sjoerg 597330f729Sjoerg} // SchedRW 60