xref: /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp (revision 82d56013d7b633d116a93943de88e08335357a7c)
17330f729Sjoerg //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
27330f729Sjoerg //
37330f729Sjoerg // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
47330f729Sjoerg // See https://llvm.org/LICENSE.txt for license information.
57330f729Sjoerg // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
67330f729Sjoerg //
77330f729Sjoerg //===----------------------------------------------------------------------===//
87330f729Sjoerg //
97330f729Sjoerg /// \file
107330f729Sjoerg /// Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
117330f729Sjoerg //
127330f729Sjoerg //===----------------------------------------------------------------------===//
137330f729Sjoerg //
147330f729Sjoerg 
157330f729Sjoerg #include "AMDGPUAsmPrinter.h"
167330f729Sjoerg #include "AMDGPUTargetMachine.h"
177330f729Sjoerg #include "MCTargetDesc/AMDGPUInstPrinter.h"
187330f729Sjoerg #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
197330f729Sjoerg #include "R600AsmPrinter.h"
207330f729Sjoerg #include "llvm/CodeGen/MachineBasicBlock.h"
217330f729Sjoerg #include "llvm/CodeGen/MachineInstr.h"
227330f729Sjoerg #include "llvm/IR/Constants.h"
237330f729Sjoerg #include "llvm/IR/Function.h"
247330f729Sjoerg #include "llvm/IR/GlobalVariable.h"
257330f729Sjoerg #include "llvm/MC/MCCodeEmitter.h"
267330f729Sjoerg #include "llvm/MC/MCContext.h"
277330f729Sjoerg #include "llvm/MC/MCExpr.h"
287330f729Sjoerg #include "llvm/MC/MCInst.h"
297330f729Sjoerg #include "llvm/MC/MCObjectStreamer.h"
307330f729Sjoerg #include "llvm/MC/MCStreamer.h"
317330f729Sjoerg #include "llvm/Support/ErrorHandling.h"
327330f729Sjoerg #include "llvm/Support/Format.h"
337330f729Sjoerg #include <algorithm>
347330f729Sjoerg 
357330f729Sjoerg using namespace llvm;
367330f729Sjoerg 
377330f729Sjoerg namespace {
387330f729Sjoerg 
397330f729Sjoerg class AMDGPUMCInstLower {
407330f729Sjoerg   MCContext &Ctx;
417330f729Sjoerg   const TargetSubtargetInfo &ST;
427330f729Sjoerg   const AsmPrinter &AP;
437330f729Sjoerg 
447330f729Sjoerg   const MCExpr *getLongBranchBlockExpr(const MachineBasicBlock &SrcBB,
457330f729Sjoerg                                        const MachineOperand &MO) const;
467330f729Sjoerg 
477330f729Sjoerg public:
487330f729Sjoerg   AMDGPUMCInstLower(MCContext &ctx, const TargetSubtargetInfo &ST,
497330f729Sjoerg                     const AsmPrinter &AP);
507330f729Sjoerg 
517330f729Sjoerg   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
527330f729Sjoerg 
537330f729Sjoerg   /// Lower a MachineInstr to an MCInst
547330f729Sjoerg   void lower(const MachineInstr *MI, MCInst &OutMI) const;
557330f729Sjoerg 
567330f729Sjoerg };
577330f729Sjoerg 
587330f729Sjoerg class R600MCInstLower : public AMDGPUMCInstLower {
597330f729Sjoerg public:
607330f729Sjoerg   R600MCInstLower(MCContext &ctx, const R600Subtarget &ST,
617330f729Sjoerg                   const AsmPrinter &AP);
627330f729Sjoerg 
637330f729Sjoerg   /// Lower a MachineInstr to an MCInst
647330f729Sjoerg   void lower(const MachineInstr *MI, MCInst &OutMI) const;
657330f729Sjoerg };
667330f729Sjoerg 
677330f729Sjoerg 
687330f729Sjoerg } // End anonymous namespace
697330f729Sjoerg 
707330f729Sjoerg #include "AMDGPUGenMCPseudoLowering.inc"
717330f729Sjoerg 
AMDGPUMCInstLower(MCContext & ctx,const TargetSubtargetInfo & st,const AsmPrinter & ap)727330f729Sjoerg AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx,
737330f729Sjoerg                                      const TargetSubtargetInfo &st,
747330f729Sjoerg                                      const AsmPrinter &ap):
757330f729Sjoerg   Ctx(ctx), ST(st), AP(ap) { }
767330f729Sjoerg 
getVariantKind(unsigned MOFlags)777330f729Sjoerg static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) {
787330f729Sjoerg   switch (MOFlags) {
797330f729Sjoerg   default:
807330f729Sjoerg     return MCSymbolRefExpr::VK_None;
817330f729Sjoerg   case SIInstrInfo::MO_GOTPCREL:
827330f729Sjoerg     return MCSymbolRefExpr::VK_GOTPCREL;
837330f729Sjoerg   case SIInstrInfo::MO_GOTPCREL32_LO:
847330f729Sjoerg     return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_LO;
857330f729Sjoerg   case SIInstrInfo::MO_GOTPCREL32_HI:
867330f729Sjoerg     return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_HI;
877330f729Sjoerg   case SIInstrInfo::MO_REL32_LO:
887330f729Sjoerg     return MCSymbolRefExpr::VK_AMDGPU_REL32_LO;
897330f729Sjoerg   case SIInstrInfo::MO_REL32_HI:
907330f729Sjoerg     return MCSymbolRefExpr::VK_AMDGPU_REL32_HI;
917330f729Sjoerg   case SIInstrInfo::MO_ABS32_LO:
927330f729Sjoerg     return MCSymbolRefExpr::VK_AMDGPU_ABS32_LO;
937330f729Sjoerg   case SIInstrInfo::MO_ABS32_HI:
947330f729Sjoerg     return MCSymbolRefExpr::VK_AMDGPU_ABS32_HI;
957330f729Sjoerg   }
967330f729Sjoerg }
977330f729Sjoerg 
getLongBranchBlockExpr(const MachineBasicBlock & SrcBB,const MachineOperand & MO) const987330f729Sjoerg const MCExpr *AMDGPUMCInstLower::getLongBranchBlockExpr(
997330f729Sjoerg   const MachineBasicBlock &SrcBB,
1007330f729Sjoerg   const MachineOperand &MO) const {
1017330f729Sjoerg   const MCExpr *DestBBSym
1027330f729Sjoerg     = MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx);
1037330f729Sjoerg   const MCExpr *SrcBBSym = MCSymbolRefExpr::create(SrcBB.getSymbol(), Ctx);
1047330f729Sjoerg 
1057330f729Sjoerg   // FIXME: The first half of this assert should be removed. This should
1067330f729Sjoerg   // probably be PC relative instead of using the source block symbol, and
1077330f729Sjoerg   // therefore the indirect branch expansion should use a bundle.
1087330f729Sjoerg   assert(
1097330f729Sjoerg       skipDebugInstructionsForward(SrcBB.begin(), SrcBB.end())->getOpcode() ==
1107330f729Sjoerg           AMDGPU::S_GETPC_B64 &&
1117330f729Sjoerg       ST.getInstrInfo()->get(AMDGPU::S_GETPC_B64).Size == 4);
1127330f729Sjoerg 
1137330f729Sjoerg   // s_getpc_b64 returns the address of next instruction.
1147330f729Sjoerg   const MCConstantExpr *One = MCConstantExpr::create(4, Ctx);
1157330f729Sjoerg   SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx);
1167330f729Sjoerg 
1177330f729Sjoerg   if (MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_FORWARD)
1187330f729Sjoerg     return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx);
1197330f729Sjoerg 
1207330f729Sjoerg   assert(MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_BACKWARD);
1217330f729Sjoerg   return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx);
1227330f729Sjoerg }
1237330f729Sjoerg 
lowerOperand(const MachineOperand & MO,MCOperand & MCOp) const1247330f729Sjoerg bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
1257330f729Sjoerg                                      MCOperand &MCOp) const {
1267330f729Sjoerg   switch (MO.getType()) {
1277330f729Sjoerg   default:
1287330f729Sjoerg     llvm_unreachable("unknown operand type");
1297330f729Sjoerg   case MachineOperand::MO_Immediate:
1307330f729Sjoerg     MCOp = MCOperand::createImm(MO.getImm());
1317330f729Sjoerg     return true;
1327330f729Sjoerg   case MachineOperand::MO_Register:
1337330f729Sjoerg     MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
1347330f729Sjoerg     return true;
1357330f729Sjoerg   case MachineOperand::MO_MachineBasicBlock: {
1367330f729Sjoerg     if (MO.getTargetFlags() != 0) {
1377330f729Sjoerg       MCOp = MCOperand::createExpr(
1387330f729Sjoerg         getLongBranchBlockExpr(*MO.getParent()->getParent(), MO));
1397330f729Sjoerg     } else {
1407330f729Sjoerg       MCOp = MCOperand::createExpr(
1417330f729Sjoerg         MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx));
1427330f729Sjoerg     }
1437330f729Sjoerg 
1447330f729Sjoerg     return true;
1457330f729Sjoerg   }
1467330f729Sjoerg   case MachineOperand::MO_GlobalAddress: {
1477330f729Sjoerg     const GlobalValue *GV = MO.getGlobal();
1487330f729Sjoerg     SmallString<128> SymbolName;
1497330f729Sjoerg     AP.getNameWithPrefix(SymbolName, GV);
1507330f729Sjoerg     MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
1517330f729Sjoerg     const MCExpr *Expr =
1527330f729Sjoerg       MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx);
1537330f729Sjoerg     int64_t Offset = MO.getOffset();
1547330f729Sjoerg     if (Offset != 0) {
1557330f729Sjoerg       Expr = MCBinaryExpr::createAdd(Expr,
1567330f729Sjoerg                                      MCConstantExpr::create(Offset, Ctx), Ctx);
1577330f729Sjoerg     }
1587330f729Sjoerg     MCOp = MCOperand::createExpr(Expr);
1597330f729Sjoerg     return true;
1607330f729Sjoerg   }
1617330f729Sjoerg   case MachineOperand::MO_ExternalSymbol: {
1627330f729Sjoerg     MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
1637330f729Sjoerg     Sym->setExternal(true);
1647330f729Sjoerg     const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
1657330f729Sjoerg     MCOp = MCOperand::createExpr(Expr);
1667330f729Sjoerg     return true;
1677330f729Sjoerg   }
1687330f729Sjoerg   case MachineOperand::MO_RegisterMask:
1697330f729Sjoerg     // Regmasks are like implicit defs.
1707330f729Sjoerg     return false;
1717330f729Sjoerg   }
1727330f729Sjoerg }
1737330f729Sjoerg 
lower(const MachineInstr * MI,MCInst & OutMI) const1747330f729Sjoerg void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
1757330f729Sjoerg   unsigned Opcode = MI->getOpcode();
1767330f729Sjoerg   const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
1777330f729Sjoerg 
1787330f729Sjoerg   // FIXME: Should be able to handle this with emitPseudoExpansionLowering. We
1797330f729Sjoerg   // need to select it to the subtarget specific version, and there's no way to
1807330f729Sjoerg   // do that with a single pseudo source operation.
1817330f729Sjoerg   if (Opcode == AMDGPU::S_SETPC_B64_return)
1827330f729Sjoerg     Opcode = AMDGPU::S_SETPC_B64;
1837330f729Sjoerg   else if (Opcode == AMDGPU::SI_CALL) {
1847330f729Sjoerg     // SI_CALL is just S_SWAPPC_B64 with an additional operand to track the
1857330f729Sjoerg     // called function (which we need to remove here).
1867330f729Sjoerg     OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
1877330f729Sjoerg     MCOperand Dest, Src;
1887330f729Sjoerg     lowerOperand(MI->getOperand(0), Dest);
1897330f729Sjoerg     lowerOperand(MI->getOperand(1), Src);
1907330f729Sjoerg     OutMI.addOperand(Dest);
1917330f729Sjoerg     OutMI.addOperand(Src);
1927330f729Sjoerg     return;
1937330f729Sjoerg   } else if (Opcode == AMDGPU::SI_TCRETURN) {
1947330f729Sjoerg     // TODO: How to use branch immediate and avoid register+add?
1957330f729Sjoerg     Opcode = AMDGPU::S_SETPC_B64;
1967330f729Sjoerg   }
1977330f729Sjoerg 
1987330f729Sjoerg   int MCOpcode = TII->pseudoToMCOpcode(Opcode);
1997330f729Sjoerg   if (MCOpcode == -1) {
2007330f729Sjoerg     LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
2017330f729Sjoerg     C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
2027330f729Sjoerg                 "a target-specific version: " + Twine(MI->getOpcode()));
2037330f729Sjoerg   }
2047330f729Sjoerg 
2057330f729Sjoerg   OutMI.setOpcode(MCOpcode);
2067330f729Sjoerg 
2077330f729Sjoerg   for (const MachineOperand &MO : MI->explicit_operands()) {
2087330f729Sjoerg     MCOperand MCOp;
2097330f729Sjoerg     lowerOperand(MO, MCOp);
2107330f729Sjoerg     OutMI.addOperand(MCOp);
2117330f729Sjoerg   }
2127330f729Sjoerg 
2137330f729Sjoerg   int FIIdx = AMDGPU::getNamedOperandIdx(MCOpcode, AMDGPU::OpName::fi);
2147330f729Sjoerg   if (FIIdx >= (int)OutMI.getNumOperands())
2157330f729Sjoerg     OutMI.addOperand(MCOperand::createImm(0));
2167330f729Sjoerg }
2177330f729Sjoerg 
lowerOperand(const MachineOperand & MO,MCOperand & MCOp) const2187330f729Sjoerg bool AMDGPUAsmPrinter::lowerOperand(const MachineOperand &MO,
2197330f729Sjoerg                                     MCOperand &MCOp) const {
2207330f729Sjoerg   const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
2217330f729Sjoerg   AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
2227330f729Sjoerg   return MCInstLowering.lowerOperand(MO, MCOp);
2237330f729Sjoerg }
2247330f729Sjoerg 
lowerAddrSpaceCast(const TargetMachine & TM,const Constant * CV,MCContext & OutContext)2257330f729Sjoerg static const MCExpr *lowerAddrSpaceCast(const TargetMachine &TM,
2267330f729Sjoerg                                         const Constant *CV,
2277330f729Sjoerg                                         MCContext &OutContext) {
2287330f729Sjoerg   // TargetMachine does not support llvm-style cast. Use C++-style cast.
2297330f729Sjoerg   // This is safe since TM is always of type AMDGPUTargetMachine or its
2307330f729Sjoerg   // derived class.
2317330f729Sjoerg   auto &AT = static_cast<const AMDGPUTargetMachine&>(TM);
2327330f729Sjoerg   auto *CE = dyn_cast<ConstantExpr>(CV);
2337330f729Sjoerg 
2347330f729Sjoerg   // Lower null pointers in private and local address space.
2357330f729Sjoerg   // Clang generates addrspacecast for null pointers in private and local
2367330f729Sjoerg   // address space, which needs to be lowered.
2377330f729Sjoerg   if (CE && CE->getOpcode() == Instruction::AddrSpaceCast) {
2387330f729Sjoerg     auto Op = CE->getOperand(0);
2397330f729Sjoerg     auto SrcAddr = Op->getType()->getPointerAddressSpace();
2407330f729Sjoerg     if (Op->isNullValue() && AT.getNullPointerValue(SrcAddr) == 0) {
2417330f729Sjoerg       auto DstAddr = CE->getType()->getPointerAddressSpace();
2427330f729Sjoerg       return MCConstantExpr::create(AT.getNullPointerValue(DstAddr),
2437330f729Sjoerg         OutContext);
2447330f729Sjoerg     }
2457330f729Sjoerg   }
2467330f729Sjoerg   return nullptr;
2477330f729Sjoerg }
2487330f729Sjoerg 
lowerConstant(const Constant * CV)2497330f729Sjoerg const MCExpr *AMDGPUAsmPrinter::lowerConstant(const Constant *CV) {
2507330f729Sjoerg   if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
2517330f729Sjoerg     return E;
2527330f729Sjoerg   return AsmPrinter::lowerConstant(CV);
2537330f729Sjoerg }
2547330f729Sjoerg 
emitInstruction(const MachineInstr * MI)255*82d56013Sjoerg void AMDGPUAsmPrinter::emitInstruction(const MachineInstr *MI) {
2567330f729Sjoerg   if (emitPseudoExpansionLowering(*OutStreamer, MI))
2577330f729Sjoerg     return;
2587330f729Sjoerg 
2597330f729Sjoerg   const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
2607330f729Sjoerg   AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
2617330f729Sjoerg 
2627330f729Sjoerg   StringRef Err;
2637330f729Sjoerg   if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
2647330f729Sjoerg     LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
2657330f729Sjoerg     C.emitError("Illegal instruction detected: " + Err);
2667330f729Sjoerg     MI->print(errs());
2677330f729Sjoerg   }
2687330f729Sjoerg 
2697330f729Sjoerg   if (MI->isBundle()) {
2707330f729Sjoerg     const MachineBasicBlock *MBB = MI->getParent();
2717330f729Sjoerg     MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
2727330f729Sjoerg     while (I != MBB->instr_end() && I->isInsideBundle()) {
273*82d56013Sjoerg       emitInstruction(&*I);
2747330f729Sjoerg       ++I;
2757330f729Sjoerg     }
2767330f729Sjoerg   } else {
277*82d56013Sjoerg     // We don't want these pseudo instructions encoded. They are
2787330f729Sjoerg     // placeholder terminator instructions and should only be printed as
2797330f729Sjoerg     // comments.
2807330f729Sjoerg     if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
2817330f729Sjoerg       if (isVerbose())
2827330f729Sjoerg         OutStreamer->emitRawComment(" return to shader part epilog");
2837330f729Sjoerg       return;
2847330f729Sjoerg     }
2857330f729Sjoerg 
2867330f729Sjoerg     if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
2877330f729Sjoerg       if (isVerbose())
2887330f729Sjoerg         OutStreamer->emitRawComment(" wave barrier");
2897330f729Sjoerg       return;
2907330f729Sjoerg     }
2917330f729Sjoerg 
2927330f729Sjoerg     if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
2937330f729Sjoerg       if (isVerbose())
2947330f729Sjoerg         OutStreamer->emitRawComment(" divergent unreachable");
2957330f729Sjoerg       return;
2967330f729Sjoerg     }
2977330f729Sjoerg 
2987330f729Sjoerg     MCInst TmpInst;
2997330f729Sjoerg     MCInstLowering.lower(MI, TmpInst);
3007330f729Sjoerg     EmitToStreamer(*OutStreamer, TmpInst);
3017330f729Sjoerg 
3027330f729Sjoerg #ifdef EXPENSIVE_CHECKS
3037330f729Sjoerg     // Sanity-check getInstSizeInBytes on explicitly specified CPUs (it cannot
3047330f729Sjoerg     // work correctly for the generic CPU).
3057330f729Sjoerg     //
3067330f729Sjoerg     // The isPseudo check really shouldn't be here, but unfortunately there are
3077330f729Sjoerg     // some negative lit tests that depend on being able to continue through
3087330f729Sjoerg     // here even when pseudo instructions haven't been lowered.
309*82d56013Sjoerg     //
310*82d56013Sjoerg     // We also overestimate branch sizes with the offset bug.
311*82d56013Sjoerg     if (!MI->isPseudo() && STI.isCPUStringValid(STI.getCPU()) &&
312*82d56013Sjoerg         (!STI.hasOffset3fBug() || !MI->isBranch())) {
3137330f729Sjoerg       SmallVector<MCFixup, 4> Fixups;
3147330f729Sjoerg       SmallVector<char, 16> CodeBytes;
3157330f729Sjoerg       raw_svector_ostream CodeStream(CodeBytes);
3167330f729Sjoerg 
3177330f729Sjoerg       std::unique_ptr<MCCodeEmitter> InstEmitter(createSIMCCodeEmitter(
3187330f729Sjoerg           *STI.getInstrInfo(), *OutContext.getRegisterInfo(), OutContext));
3197330f729Sjoerg       InstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups, STI);
3207330f729Sjoerg 
3217330f729Sjoerg       assert(CodeBytes.size() == STI.getInstrInfo()->getInstSizeInBytes(*MI));
3227330f729Sjoerg     }
3237330f729Sjoerg #endif
3247330f729Sjoerg 
3257330f729Sjoerg     if (DumpCodeInstEmitter) {
3267330f729Sjoerg       // Disassemble instruction/operands to text
3277330f729Sjoerg       DisasmLines.resize(DisasmLines.size() + 1);
3287330f729Sjoerg       std::string &DisasmLine = DisasmLines.back();
3297330f729Sjoerg       raw_string_ostream DisasmStream(DisasmLine);
3307330f729Sjoerg 
3317330f729Sjoerg       AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *STI.getInstrInfo(),
3327330f729Sjoerg                                     *STI.getRegisterInfo());
333*82d56013Sjoerg       InstPrinter.printInst(&TmpInst, 0, StringRef(), STI, DisasmStream);
3347330f729Sjoerg 
3357330f729Sjoerg       // Disassemble instruction/operands to hex representation.
3367330f729Sjoerg       SmallVector<MCFixup, 4> Fixups;
3377330f729Sjoerg       SmallVector<char, 16> CodeBytes;
3387330f729Sjoerg       raw_svector_ostream CodeStream(CodeBytes);
3397330f729Sjoerg 
3407330f729Sjoerg       DumpCodeInstEmitter->encodeInstruction(
3417330f729Sjoerg           TmpInst, CodeStream, Fixups, MF->getSubtarget<MCSubtargetInfo>());
3427330f729Sjoerg       HexLines.resize(HexLines.size() + 1);
3437330f729Sjoerg       std::string &HexLine = HexLines.back();
3447330f729Sjoerg       raw_string_ostream HexStream(HexLine);
3457330f729Sjoerg 
3467330f729Sjoerg       for (size_t i = 0; i < CodeBytes.size(); i += 4) {
3477330f729Sjoerg         unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
3487330f729Sjoerg         HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
3497330f729Sjoerg       }
3507330f729Sjoerg 
3517330f729Sjoerg       DisasmStream.flush();
3527330f729Sjoerg       DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
3537330f729Sjoerg     }
3547330f729Sjoerg   }
3557330f729Sjoerg }
3567330f729Sjoerg 
R600MCInstLower(MCContext & Ctx,const R600Subtarget & ST,const AsmPrinter & AP)3577330f729Sjoerg R600MCInstLower::R600MCInstLower(MCContext &Ctx, const R600Subtarget &ST,
3587330f729Sjoerg                                  const AsmPrinter &AP) :
3597330f729Sjoerg         AMDGPUMCInstLower(Ctx, ST, AP) { }
3607330f729Sjoerg 
lower(const MachineInstr * MI,MCInst & OutMI) const3617330f729Sjoerg void R600MCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
3627330f729Sjoerg   OutMI.setOpcode(MI->getOpcode());
3637330f729Sjoerg   for (const MachineOperand &MO : MI->explicit_operands()) {
3647330f729Sjoerg     MCOperand MCOp;
3657330f729Sjoerg     lowerOperand(MO, MCOp);
3667330f729Sjoerg     OutMI.addOperand(MCOp);
3677330f729Sjoerg   }
3687330f729Sjoerg }
3697330f729Sjoerg 
emitInstruction(const MachineInstr * MI)370*82d56013Sjoerg void R600AsmPrinter::emitInstruction(const MachineInstr *MI) {
3717330f729Sjoerg   const R600Subtarget &STI = MF->getSubtarget<R600Subtarget>();
3727330f729Sjoerg   R600MCInstLower MCInstLowering(OutContext, STI, *this);
3737330f729Sjoerg 
3747330f729Sjoerg   StringRef Err;
3757330f729Sjoerg   if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
3767330f729Sjoerg     LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
3777330f729Sjoerg     C.emitError("Illegal instruction detected: " + Err);
3787330f729Sjoerg     MI->print(errs());
3797330f729Sjoerg   }
3807330f729Sjoerg 
3817330f729Sjoerg   if (MI->isBundle()) {
3827330f729Sjoerg     const MachineBasicBlock *MBB = MI->getParent();
3837330f729Sjoerg     MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
3847330f729Sjoerg     while (I != MBB->instr_end() && I->isInsideBundle()) {
385*82d56013Sjoerg       emitInstruction(&*I);
3867330f729Sjoerg       ++I;
3877330f729Sjoerg     }
3887330f729Sjoerg   } else {
3897330f729Sjoerg     MCInst TmpInst;
3907330f729Sjoerg     MCInstLowering.lower(MI, TmpInst);
3917330f729Sjoerg     EmitToStreamer(*OutStreamer, TmpInst);
3927330f729Sjoerg  }
3937330f729Sjoerg }
3947330f729Sjoerg 
lowerConstant(const Constant * CV)3957330f729Sjoerg const MCExpr *R600AsmPrinter::lowerConstant(const Constant *CV) {
3967330f729Sjoerg   if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
3977330f729Sjoerg     return E;
3987330f729Sjoerg   return AsmPrinter::lowerConstant(CV);
3997330f729Sjoerg }
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