1*7330f729Sjoerg /*===---- prfchwintrin.h - PREFETCHW intrinsic -----------------------------=== 2*7330f729Sjoerg * 3*7330f729Sjoerg * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*7330f729Sjoerg * See https://llvm.org/LICENSE.txt for license information. 5*7330f729Sjoerg * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*7330f729Sjoerg * 7*7330f729Sjoerg *===-----------------------------------------------------------------------=== 8*7330f729Sjoerg */ 9*7330f729Sjoerg 10*7330f729Sjoerg #if !defined(__X86INTRIN_H) && !defined(_MM3DNOW_H_INCLUDED) 11*7330f729Sjoerg #error "Never use <prfchwintrin.h> directly; include <x86intrin.h> or <mm3dnow.h> instead." 12*7330f729Sjoerg #endif 13*7330f729Sjoerg 14*7330f729Sjoerg #ifndef __PRFCHWINTRIN_H 15*7330f729Sjoerg #define __PRFCHWINTRIN_H 16*7330f729Sjoerg 17*7330f729Sjoerg /// Loads a memory sequence containing the specified memory address into 18*7330f729Sjoerg /// all data cache levels. The cache-coherency state is set to exclusive. 19*7330f729Sjoerg /// Data can be read from and written to the cache line without additional 20*7330f729Sjoerg /// delay. 21*7330f729Sjoerg /// 22*7330f729Sjoerg /// \headerfile <x86intrin.h> 23*7330f729Sjoerg /// 24*7330f729Sjoerg /// This intrinsic corresponds to the \c PREFETCHT0 instruction. 25*7330f729Sjoerg /// 26*7330f729Sjoerg /// \param __P 27*7330f729Sjoerg /// A pointer specifying the memory address to be prefetched. 28*7330f729Sjoerg static __inline__ void __attribute__((__always_inline__, __nodebug__)) _m_prefetch(void * __P)29*7330f729Sjoerg_m_prefetch(void *__P) 30*7330f729Sjoerg { 31*7330f729Sjoerg __builtin_prefetch (__P, 0, 3 /* _MM_HINT_T0 */); 32*7330f729Sjoerg } 33*7330f729Sjoerg 34*7330f729Sjoerg /// Loads a memory sequence containing the specified memory address into 35*7330f729Sjoerg /// the L1 data cache and sets the cache-coherency to modified. This 36*7330f729Sjoerg /// provides a hint to the processor that the cache line will be modified. 37*7330f729Sjoerg /// It is intended for use when the cache line will be written to shortly 38*7330f729Sjoerg /// after the prefetch is performed. 39*7330f729Sjoerg /// 40*7330f729Sjoerg /// Note that the effect of this intrinsic is dependent on the processor 41*7330f729Sjoerg /// implementation. 42*7330f729Sjoerg /// 43*7330f729Sjoerg /// \headerfile <x86intrin.h> 44*7330f729Sjoerg /// 45*7330f729Sjoerg /// This intrinsic corresponds to the \c PREFETCHW instruction. 46*7330f729Sjoerg /// 47*7330f729Sjoerg /// \param __P 48*7330f729Sjoerg /// A pointer specifying the memory address to be prefetched. 49*7330f729Sjoerg static __inline__ void __attribute__((__always_inline__, __nodebug__)) _m_prefetchw(void * __P)50*7330f729Sjoerg_m_prefetchw(void *__P) 51*7330f729Sjoerg { 52*7330f729Sjoerg __builtin_prefetch (__P, 1, 3 /* _MM_HINT_T0 */); 53*7330f729Sjoerg } 54*7330f729Sjoerg 55*7330f729Sjoerg #endif /* __PRFCHWINTRIN_H */ 56