xref: /netbsd-src/common/lib/libc/arch/mips/gen/byte_swap_8.S (revision 8daf714e68d332607ba2c61d8c1ff3868c564c61)
1*8daf714eSmatt/*	$NetBSD: byte_swap_8.S,v 1.2 2009/12/14 00:39:00 matt Exp $	*/
2*8daf714eSmatt
3*8daf714eSmatt/*-
4*8daf714eSmatt * Copyright (c) 1991, 1993
5*8daf714eSmatt *	The Regents of the University of California.  All rights reserved.
6*8daf714eSmatt *
7*8daf714eSmatt * This code is derived from software contributed to Berkeley by
8*8daf714eSmatt * Ralph Campbell.
9*8daf714eSmatt *
10*8daf714eSmatt * Redistribution and use in source and binary forms, with or without
11*8daf714eSmatt * modification, are permitted provided that the following conditions
12*8daf714eSmatt * are met:
13*8daf714eSmatt * 1. Redistributions of source code must retain the above copyright
14*8daf714eSmatt *    notice, this list of conditions and the following disclaimer.
15*8daf714eSmatt * 2. Redistributions in binary form must reproduce the above copyright
16*8daf714eSmatt *    notice, this list of conditions and the following disclaimer in the
17*8daf714eSmatt *    documentation and/or other materials provided with the distribution.
18*8daf714eSmatt * 3. Neither the name of the University nor the names of its contributors
19*8daf714eSmatt *    may be used to endorse or promote products derived from this software
20*8daf714eSmatt *    without specific prior written permission.
21*8daf714eSmatt *
22*8daf714eSmatt * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23*8daf714eSmatt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24*8daf714eSmatt * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25*8daf714eSmatt * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26*8daf714eSmatt * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27*8daf714eSmatt * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28*8daf714eSmatt * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29*8daf714eSmatt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30*8daf714eSmatt * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31*8daf714eSmatt * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32*8daf714eSmatt * SUCH DAMAGE.
33*8daf714eSmatt */
34*8daf714eSmatt
35*8daf714eSmatt#include <mips/asm.h>
36*8daf714eSmatt
37*8daf714eSmatt#if defined(LIBC_SCCS) && !defined(lint)
38*8daf714eSmatt	RCSID("$NetBSD: byte_swap_8.S,v 1.2 2009/12/14 00:39:00 matt Exp $")
39*8daf714eSmatt#endif /* LIBC_SCCS and not lint */
40*8daf714eSmatt
41*8daf714eSmatt#undef _LOCORE
42*8daf714eSmatt#define _LOCORE		/* XXX not really, just assembly-code source */
43*8daf714eSmatt#include <machine/endian.h>
44*8daf714eSmatt
45*8daf714eSmattNLEAF(bswap64)	# a0 = 0xffeeddccbbaa9988 return 0x8899aabbccddeeff
46*8daf714eSmatt#if (__mips == 32 || __mips == 64) && __mips_isa_rev == 2
47*8daf714eSmatt#if !defined(__mips_o32)
48*8daf714eSmatt	/*
49*8daf714eSmatt	 * If we are on MIPS32r2 or MIPS64r2 use the new instructions.
50*8daf714eSmatt	 */
51*8daf714eSmatt	dsbh	v0, a0			# dwords swap bytes within halfwords
52*8daf714eSmatt	dshd	v0, v0			# dwords swap halwords within dwords
53*8daf714eSmatt	j	ra
54*8daf714eSmatt#else /* defined(__mips_o32) */
55*8daf714eSmatt	/*
56*8daf714eSmatt	 * If we are on MIPS32r2 or MIPS64r2 use the new instructions.
57*8daf714eSmatt	 * (except we must use the 32bit versions)
58*8daf714eSmatt	 */
59*8daf714eSmatt	wsbh	v1, a0			# word swap bytes within halfwords
60*8daf714eSmatt	wsbh	v0, a1			# word swap bytes within halfwords
61*8daf714eSmatt	rotr	v1, v1, 16		# rotate word 16bits and swap word
62*8daf714eSmatt	rotr	v0, v0, 16		# rotate word 16bits and swap word
63*8daf714eSmatt	j	ra
64*8daf714eSmatt#endif /* defined(__mips_o32) */
65*8daf714eSmatt#elif !defined(__mips_o32)
66*8daf714eSmatt					# a0  = 0xffeeddccbbaa9988
67*8daf714eSmatt	li	t0, 0xffff		# t0  = 0x000000000000ffff
68*8daf714eSmatt	dsll	t1, t0, 32		# t1  = 0x0000ffff00000000
69*8daf714eSmatt	or	t0, t1			# t0  = 0x0000ffff0000ffff
70*8daf714eSmatt	dsll	t2, t0, 8		# t2  = 0x00ffff0000ffff00
71*8daf714eSmatt	xor	t2, t0			# t2  = 0x00ff00ff00ff00ff
72*8daf714eSmatt	/*
73*8daf714eSmatt	 * We could swap by halfword, but that would be one instruction longer.
74*8daf714eSmatt	 */
75*8daf714eSmatt	dsrl	ta0, a0, 32		# ta0 = 0x00000000ffeeddcc
76*8daf714eSmatt	dsll	ta1, a0, 32		# ta1 = 0xbbaa998800000000
77*8daf714eSmatt	or	a1, ta0, ta1		# a1  = 0xbbaa9988ffeeddcc
78*8daf714eSmatt					# words swapped
79*8daf714eSmatt	and	ta0, a1, t0		# ta0 = 0x000099880000ddcc
80*8daf714eSmatt	dsrl	ta1, a1, 16		# ta1 = 0x0000bbaa9988ffee
81*8daf714eSmatt	and	ta1, t0			# ta1 = 0x0000bbaa0000ffee
82*8daf714eSmatt	dsll	a2, ta0, 16		# a2  = 0x99880000ddcc0000
83*8daf714eSmatt	or	a2, ta1			# a2  = 0x9988bbaaddccffee
84*8daf714eSmatt					# halfwords swapped
85*8daf714eSmatt	and	ta0, a2, t2		# ta0 = 0x008800aa00cc00ee
86*8daf714eSmatt	dsrl	ta1, a2, 8		# ta1 = 0x009988bbaaddccff
87*8daf714eSmatt	and	ta1, t2			# ta1 = 0x009900bb00dd00ff
88*8daf714eSmatt	dsll	v0, ta0, 8		# v0  = 0x8800aa00cc00ee00
89*8daf714eSmatt	or	v0, ta1			# v0  = 0x8899aabbccddeeff
90*8daf714eSmatt					# bytes swapped
91*8daf714eSmatt	j	ra
92*8daf714eSmatt#else /* defined(__mips_o32) */
93*8daf714eSmatt	/*
94*8daf714eSmatt	 * 32bit ABI.
95*8daf714eSmatt	 */
96*8daf714eSmatt					# a0  = 0xccddeeff
97*8daf714eSmatt					# a1  = 0x8899aabb
98*8daf714eSmatt	srl	t0, a0, 24		# t0  = 0x000000cc
99*8daf714eSmatt	srl	t1, a1, 24		# t1  = 0x00000088
100*8daf714eSmatt	sll	ta0, a0, 24		# ta0 = 0xff000000
101*8daf714eSmatt	sll	ta1, a1, 24		# ta1 = 0xbb000000
102*8daf714eSmatt	or	ta0, ta0, t0		# ta0 = 0xff0000cc
103*8daf714eSmatt	or	ta1, ta1, t1		# ta1 = 0xbb000088
104*8daf714eSmatt	and	t0, a0, 0xff00		# t0  = 0x0000ee00
105*8daf714eSmatt	and	t1, a1, 0xff00		# t1  = 0x0000aa00
106*8daf714eSmatt	sll	t0, t0, 8		# t0  = 0x00ee0000
107*8daf714eSmatt	sll	t1, t1, 8		# t1  = 0x00aa0000
108*8daf714eSmatt	or	ta0, ta0, t0		# ta0 = 0xffee00cc
109*8daf714eSmatt	or	ta1, ta1, t1		# ta1 = 0xbbaa0088
110*8daf714eSmatt	srl	t0, a0, 8		# t0  = 0x00ccddee
111*8daf714eSmatt	srl	t1, a1, 8		# t1  = 0x008899aa
112*8daf714eSmatt	and	t0, t0, 0xff00		# t0  = 0x0000dd00
113*8daf714eSmatt	and	t1, t1, 0xff00		# t1  = 0x00009900
114*8daf714eSmatt	or	v1, ta0, t0		# v1  = 0xffeeddcc
115*8daf714eSmatt	or	v0, ta1, t1		# v0  = 0xbbaa9988
116*8daf714eSmatt	j	ra
117*8daf714eSmatt#endif /* defined(__mips_o32) */
118*8daf714eSmattEND(bswap64)
119