xref: /minix3/sys/dev/pci/pci_subr.c (revision b2ee0702ff8e8e556f7fe39b81f43e413070dc59)
10a6a1f1dSLionel Sambuc /*	$NetBSD: pci_subr.c,v 1.137 2015/10/03 15:22:14 joerg Exp $	*/
27eb99bdaSLionel Sambuc 
37eb99bdaSLionel Sambuc /*
47eb99bdaSLionel Sambuc  * Copyright (c) 1997 Zubin D. Dittia.  All rights reserved.
57eb99bdaSLionel Sambuc  * Copyright (c) 1995, 1996, 1998, 2000
67eb99bdaSLionel Sambuc  *	Christopher G. Demetriou.  All rights reserved.
77eb99bdaSLionel Sambuc  * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
87eb99bdaSLionel Sambuc  *
97eb99bdaSLionel Sambuc  * Redistribution and use in source and binary forms, with or without
107eb99bdaSLionel Sambuc  * modification, are permitted provided that the following conditions
117eb99bdaSLionel Sambuc  * are met:
127eb99bdaSLionel Sambuc  * 1. Redistributions of source code must retain the above copyright
137eb99bdaSLionel Sambuc  *    notice, this list of conditions and the following disclaimer.
147eb99bdaSLionel Sambuc  * 2. Redistributions in binary form must reproduce the above copyright
157eb99bdaSLionel Sambuc  *    notice, this list of conditions and the following disclaimer in the
167eb99bdaSLionel Sambuc  *    documentation and/or other materials provided with the distribution.
177eb99bdaSLionel Sambuc  * 3. All advertising materials mentioning features or use of this software
187eb99bdaSLionel Sambuc  *    must display the following acknowledgement:
197eb99bdaSLionel Sambuc  *	This product includes software developed by Charles M. Hannum.
207eb99bdaSLionel Sambuc  * 4. The name of the author may not be used to endorse or promote products
217eb99bdaSLionel Sambuc  *    derived from this software without specific prior written permission.
227eb99bdaSLionel Sambuc  *
237eb99bdaSLionel Sambuc  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
247eb99bdaSLionel Sambuc  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
257eb99bdaSLionel Sambuc  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
267eb99bdaSLionel Sambuc  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
277eb99bdaSLionel Sambuc  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
287eb99bdaSLionel Sambuc  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
297eb99bdaSLionel Sambuc  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
307eb99bdaSLionel Sambuc  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
317eb99bdaSLionel Sambuc  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
327eb99bdaSLionel Sambuc  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
337eb99bdaSLionel Sambuc  */
347eb99bdaSLionel Sambuc 
353641562fSLionel Sambuc #if defined(__minix) && defined(_PCI_SERVER)
363641562fSLionel Sambuc /* This is a quick hack, simple copy of the file, until we can use it as is. */
373641562fSLionel Sambuc #include <sys/types.h>
383641562fSLionel Sambuc 
393641562fSLionel Sambuc #include <stdint.h>
403641562fSLionel Sambuc #include <stdbool.h>
413641562fSLionel Sambuc #include <stdio.h>
423641562fSLionel Sambuc 
433641562fSLionel Sambuc #include <pci.h>
443641562fSLionel Sambuc #include <dev/pci/pcireg.h>
450a6a1f1dSLionel Sambuc #include <dev/pci/pci_verbose.h>
460a6a1f1dSLionel Sambuc #include <dev/pci/pcidevs.h>
470a6a1f1dSLionel Sambuc #include <dev/pci/pcidevs_data.h>
483641562fSLionel Sambuc 
493641562fSLionel Sambuc const char *pci_baseclass_name(pcireg_t reg);
503641562fSLionel Sambuc const char *pci_subclass_name(pcireg_t reg);
513641562fSLionel Sambuc #else
527eb99bdaSLionel Sambuc /*
537eb99bdaSLionel Sambuc  * PCI autoconfiguration support functions.
547eb99bdaSLionel Sambuc  *
557eb99bdaSLionel Sambuc  * Note: This file is also built into a userland library (libpci).
567eb99bdaSLionel Sambuc  * Pay attention to this when you make modifications.
577eb99bdaSLionel Sambuc  */
587eb99bdaSLionel Sambuc 
597eb99bdaSLionel Sambuc #include <sys/cdefs.h>
600a6a1f1dSLionel Sambuc __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.137 2015/10/03 15:22:14 joerg Exp $");
617eb99bdaSLionel Sambuc 
627eb99bdaSLionel Sambuc #ifdef _KERNEL_OPT
637eb99bdaSLionel Sambuc #include "opt_pci.h"
647eb99bdaSLionel Sambuc #endif
657eb99bdaSLionel Sambuc 
667eb99bdaSLionel Sambuc #include <sys/param.h>
677eb99bdaSLionel Sambuc 
687eb99bdaSLionel Sambuc #ifdef _KERNEL
697eb99bdaSLionel Sambuc #include <sys/systm.h>
707eb99bdaSLionel Sambuc #include <sys/intr.h>
717eb99bdaSLionel Sambuc #include <sys/module.h>
727eb99bdaSLionel Sambuc #else
737eb99bdaSLionel Sambuc #include <pci.h>
747eb99bdaSLionel Sambuc #include <stdbool.h>
757eb99bdaSLionel Sambuc #include <stdio.h>
760a6a1f1dSLionel Sambuc #include <stdlib.h>
770a6a1f1dSLionel Sambuc #include <string.h>
787eb99bdaSLionel Sambuc #endif
797eb99bdaSLionel Sambuc 
807eb99bdaSLionel Sambuc #include <dev/pci/pcireg.h>
817eb99bdaSLionel Sambuc #ifdef _KERNEL
827eb99bdaSLionel Sambuc #include <dev/pci/pcivar.h>
830a6a1f1dSLionel Sambuc #else
840a6a1f1dSLionel Sambuc #include <dev/pci/pci_verbose.h>
850a6a1f1dSLionel Sambuc #include <dev/pci/pcidevs.h>
860a6a1f1dSLionel Sambuc #include <dev/pci/pcidevs_data.h>
877eb99bdaSLionel Sambuc #endif
883641562fSLionel Sambuc #endif /* defined(__minix) && defined(_PCI_SERVER) */
897eb99bdaSLionel Sambuc 
907eb99bdaSLionel Sambuc /*
917eb99bdaSLionel Sambuc  * Descriptions of known PCI classes and subclasses.
927eb99bdaSLionel Sambuc  *
937eb99bdaSLionel Sambuc  * Subclasses are described in the same way as classes, but have a
947eb99bdaSLionel Sambuc  * NULL subclass pointer.
957eb99bdaSLionel Sambuc  */
967eb99bdaSLionel Sambuc struct pci_class {
977eb99bdaSLionel Sambuc 	const char	*name;
987eb99bdaSLionel Sambuc 	u_int		val;		/* as wide as pci_{,sub}class_t */
997eb99bdaSLionel Sambuc 	const struct pci_class *subclasses;
1007eb99bdaSLionel Sambuc };
1017eb99bdaSLionel Sambuc 
1020a6a1f1dSLionel Sambuc /*
1030a6a1f1dSLionel Sambuc  * Class 0x00.
1040a6a1f1dSLionel Sambuc  * Before rev. 2.0.
1050a6a1f1dSLionel Sambuc  */
1067eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_prehistoric[] = {
1077eb99bdaSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_PREHISTORIC_MISC,	NULL,	},
1087eb99bdaSLionel Sambuc 	{ "VGA",		PCI_SUBCLASS_PREHISTORIC_VGA,	NULL,	},
1097eb99bdaSLionel Sambuc 	{ NULL,			0,				NULL,	},
1107eb99bdaSLionel Sambuc };
1117eb99bdaSLionel Sambuc 
1120a6a1f1dSLionel Sambuc /*
1130a6a1f1dSLionel Sambuc  * Class 0x01.
1140a6a1f1dSLionel Sambuc  * Mass storage controller
1150a6a1f1dSLionel Sambuc  */
1160a6a1f1dSLionel Sambuc 
1170a6a1f1dSLionel Sambuc /* ATA programming interface */
1180a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_ata[] = {
1190a6a1f1dSLionel Sambuc 	{ "with single DMA",	PCI_INTERFACE_ATA_SINGLEDMA,	NULL,	},
1200a6a1f1dSLionel Sambuc 	{ "with chained DMA",	PCI_INTERFACE_ATA_CHAINEDDMA,	NULL,	},
1210a6a1f1dSLionel Sambuc 	{ NULL,			0,				NULL,	},
1220a6a1f1dSLionel Sambuc };
1230a6a1f1dSLionel Sambuc 
1240a6a1f1dSLionel Sambuc /* SATA programming interface */
1250a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_sata[] = {
1260a6a1f1dSLionel Sambuc 	{ "vendor specific",	PCI_INTERFACE_SATA_VND,		NULL,	},
1270a6a1f1dSLionel Sambuc 	{ "AHCI 1.0",		PCI_INTERFACE_SATA_AHCI10,	NULL,	},
1280a6a1f1dSLionel Sambuc 	{ "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, },
1290a6a1f1dSLionel Sambuc 	{ NULL,			0,				NULL,	},
1300a6a1f1dSLionel Sambuc };
1310a6a1f1dSLionel Sambuc 
1320a6a1f1dSLionel Sambuc /* Flash programming interface */
1330a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_nvm[] = {
1340a6a1f1dSLionel Sambuc 	{ "vendor specific",	PCI_INTERFACE_NVM_VND,		NULL,	},
1350a6a1f1dSLionel Sambuc 	{ "NVMHCI 1.0",		PCI_INTERFACE_NVM_NVMHCI10,	NULL,	},
1360a6a1f1dSLionel Sambuc 	{ "NVMe",		PCI_INTERFACE_NVM_NVME,		NULL,	},
1370a6a1f1dSLionel Sambuc 	{ NULL,			0,				NULL,	},
1380a6a1f1dSLionel Sambuc };
1390a6a1f1dSLionel Sambuc 
1400a6a1f1dSLionel Sambuc /* Subclasses */
1417eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_mass_storage[] = {
1427eb99bdaSLionel Sambuc 	{ "SCSI",		PCI_SUBCLASS_MASS_STORAGE_SCSI,	NULL,	},
1437eb99bdaSLionel Sambuc 	{ "IDE",		PCI_SUBCLASS_MASS_STORAGE_IDE,	NULL,	},
1447eb99bdaSLionel Sambuc 	{ "floppy",		PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, },
1457eb99bdaSLionel Sambuc 	{ "IPI",		PCI_SUBCLASS_MASS_STORAGE_IPI,	NULL,	},
1467eb99bdaSLionel Sambuc 	{ "RAID",		PCI_SUBCLASS_MASS_STORAGE_RAID,	NULL,	},
1470a6a1f1dSLionel Sambuc 	{ "ATA",		PCI_SUBCLASS_MASS_STORAGE_ATA,
1480a6a1f1dSLionel Sambuc 	  pci_interface_ata, },
1490a6a1f1dSLionel Sambuc 	{ "SATA",		PCI_SUBCLASS_MASS_STORAGE_SATA,
1500a6a1f1dSLionel Sambuc 	  pci_interface_sata, },
1517eb99bdaSLionel Sambuc 	{ "SAS",		PCI_SUBCLASS_MASS_STORAGE_SAS,	NULL,	},
1520a6a1f1dSLionel Sambuc 	{ "Flash",		PCI_SUBCLASS_MASS_STORAGE_NVM,
1530a6a1f1dSLionel Sambuc 	  pci_interface_nvm,	},
1547eb99bdaSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_MASS_STORAGE_MISC,	NULL,	},
1557eb99bdaSLionel Sambuc 	{ NULL,			0,				NULL,	},
1567eb99bdaSLionel Sambuc };
1577eb99bdaSLionel Sambuc 
1580a6a1f1dSLionel Sambuc /*
1590a6a1f1dSLionel Sambuc  * Class 0x02.
1600a6a1f1dSLionel Sambuc  * Network controller.
1610a6a1f1dSLionel Sambuc  */
1627eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_network[] = {
1637eb99bdaSLionel Sambuc 	{ "ethernet",		PCI_SUBCLASS_NETWORK_ETHERNET,	NULL,	},
1647eb99bdaSLionel Sambuc 	{ "token ring",		PCI_SUBCLASS_NETWORK_TOKENRING,	NULL,	},
1657eb99bdaSLionel Sambuc 	{ "FDDI",		PCI_SUBCLASS_NETWORK_FDDI,	NULL,	},
1667eb99bdaSLionel Sambuc 	{ "ATM",		PCI_SUBCLASS_NETWORK_ATM,	NULL,	},
1677eb99bdaSLionel Sambuc 	{ "ISDN",		PCI_SUBCLASS_NETWORK_ISDN,	NULL,	},
1687eb99bdaSLionel Sambuc 	{ "WorldFip",		PCI_SUBCLASS_NETWORK_WORLDFIP,	NULL,	},
1697eb99bdaSLionel Sambuc 	{ "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, },
1707eb99bdaSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_NETWORK_MISC,	NULL,	},
1717eb99bdaSLionel Sambuc 	{ NULL,			0,				NULL,	},
1727eb99bdaSLionel Sambuc };
1737eb99bdaSLionel Sambuc 
1740a6a1f1dSLionel Sambuc /*
1750a6a1f1dSLionel Sambuc  * Class 0x03.
1760a6a1f1dSLionel Sambuc  * Display controller.
1770a6a1f1dSLionel Sambuc  */
1780a6a1f1dSLionel Sambuc 
1790a6a1f1dSLionel Sambuc /* VGA programming interface */
1800a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_vga[] = {
1810a6a1f1dSLionel Sambuc 	{ "",			PCI_INTERFACE_VGA_VGA,		NULL,	},
1820a6a1f1dSLionel Sambuc 	{ "8514-compat",	PCI_INTERFACE_VGA_8514,		NULL,	},
1830a6a1f1dSLionel Sambuc 	{ NULL,			0,				NULL,	},
1840a6a1f1dSLionel Sambuc };
1850a6a1f1dSLionel Sambuc /* Subclasses */
1867eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_display[] = {
1870a6a1f1dSLionel Sambuc 	{ "VGA",		PCI_SUBCLASS_DISPLAY_VGA,  pci_interface_vga,},
1887eb99bdaSLionel Sambuc 	{ "XGA",		PCI_SUBCLASS_DISPLAY_XGA,	NULL,	},
1897eb99bdaSLionel Sambuc 	{ "3D",			PCI_SUBCLASS_DISPLAY_3D,	NULL,	},
1907eb99bdaSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_DISPLAY_MISC,	NULL,	},
1917eb99bdaSLionel Sambuc 	{ NULL,			0,				NULL,	},
1927eb99bdaSLionel Sambuc };
1937eb99bdaSLionel Sambuc 
1940a6a1f1dSLionel Sambuc /*
1950a6a1f1dSLionel Sambuc  * Class 0x04.
1960a6a1f1dSLionel Sambuc  * Multimedia device.
1970a6a1f1dSLionel Sambuc  */
1987eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_multimedia[] = {
1997eb99bdaSLionel Sambuc 	{ "video",		PCI_SUBCLASS_MULTIMEDIA_VIDEO,	NULL,	},
2007eb99bdaSLionel Sambuc 	{ "audio",		PCI_SUBCLASS_MULTIMEDIA_AUDIO,	NULL,	},
2017eb99bdaSLionel Sambuc 	{ "telephony",		PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,},
2020a6a1f1dSLionel Sambuc 	{ "mixed mode",		PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, },
2037eb99bdaSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_MULTIMEDIA_MISC,	NULL,	},
2047eb99bdaSLionel Sambuc 	{ NULL,			0,				NULL,	},
2057eb99bdaSLionel Sambuc };
2067eb99bdaSLionel Sambuc 
2070a6a1f1dSLionel Sambuc /*
2080a6a1f1dSLionel Sambuc  * Class 0x05.
2090a6a1f1dSLionel Sambuc  * Memory controller.
2100a6a1f1dSLionel Sambuc  */
2117eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_memory[] = {
2127eb99bdaSLionel Sambuc 	{ "RAM",		PCI_SUBCLASS_MEMORY_RAM,	NULL,	},
2137eb99bdaSLionel Sambuc 	{ "flash",		PCI_SUBCLASS_MEMORY_FLASH,	NULL,	},
2147eb99bdaSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_MEMORY_MISC,	NULL,	},
2157eb99bdaSLionel Sambuc 	{ NULL,			0,				NULL,	},
2167eb99bdaSLionel Sambuc };
2177eb99bdaSLionel Sambuc 
2180a6a1f1dSLionel Sambuc /*
2190a6a1f1dSLionel Sambuc  * Class 0x06.
2200a6a1f1dSLionel Sambuc  * Bridge device.
2210a6a1f1dSLionel Sambuc  */
2220a6a1f1dSLionel Sambuc 
2230a6a1f1dSLionel Sambuc /* PCI bridge programming interface */
2240a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_pcibridge[] = {
2250a6a1f1dSLionel Sambuc 	{ "",			PCI_INTERFACE_BRIDGE_PCI_PCI, NULL,	},
2260a6a1f1dSLionel Sambuc 	{ "subtractive decode",	PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL,	},
2270a6a1f1dSLionel Sambuc 	{ NULL,			0,				NULL,	},
2280a6a1f1dSLionel Sambuc };
2290a6a1f1dSLionel Sambuc 
2300a6a1f1dSLionel Sambuc /* Semi-transparent PCI-to-PCI bridge programming interface */
2310a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_stpci[] = {
2320a6a1f1dSLionel Sambuc 	{ "primary side facing host",	PCI_INTERFACE_STPCI_PRIMARY, NULL, },
2330a6a1f1dSLionel Sambuc 	{ "secondary side facing host",	PCI_INTERFACE_STPCI_SECONDARY, NULL, },
2340a6a1f1dSLionel Sambuc 	{ NULL,			0,				NULL,	},
2350a6a1f1dSLionel Sambuc };
2360a6a1f1dSLionel Sambuc 
2370a6a1f1dSLionel Sambuc /* Advanced Switching programming interface */
2380a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_advsw[] = {
2390a6a1f1dSLionel Sambuc 	{ "custom interface",	PCI_INTERFACE_ADVSW_CUSTOM, NULL, },
2400a6a1f1dSLionel Sambuc 	{ "ASI-SIG",		PCI_INTERFACE_ADVSW_ASISIG, NULL, },
2410a6a1f1dSLionel Sambuc 	{ NULL,			0,				NULL,	},
2420a6a1f1dSLionel Sambuc };
2430a6a1f1dSLionel Sambuc 
2440a6a1f1dSLionel Sambuc /* Subclasses */
2457eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_bridge[] = {
2467eb99bdaSLionel Sambuc 	{ "host",		PCI_SUBCLASS_BRIDGE_HOST,	NULL,	},
2477eb99bdaSLionel Sambuc 	{ "ISA",		PCI_SUBCLASS_BRIDGE_ISA,	NULL,	},
2487eb99bdaSLionel Sambuc 	{ "EISA",		PCI_SUBCLASS_BRIDGE_EISA,	NULL,	},
2497eb99bdaSLionel Sambuc 	{ "MicroChannel",	PCI_SUBCLASS_BRIDGE_MC,		NULL,	},
2500a6a1f1dSLionel Sambuc 	{ "PCI",		PCI_SUBCLASS_BRIDGE_PCI,
2510a6a1f1dSLionel Sambuc 	  pci_interface_pcibridge,	},
2527eb99bdaSLionel Sambuc 	{ "PCMCIA",		PCI_SUBCLASS_BRIDGE_PCMCIA,	NULL,	},
2537eb99bdaSLionel Sambuc 	{ "NuBus",		PCI_SUBCLASS_BRIDGE_NUBUS,	NULL,	},
2547eb99bdaSLionel Sambuc 	{ "CardBus",		PCI_SUBCLASS_BRIDGE_CARDBUS,	NULL,	},
2557eb99bdaSLionel Sambuc 	{ "RACEway",		PCI_SUBCLASS_BRIDGE_RACEWAY,	NULL,	},
2560a6a1f1dSLionel Sambuc 	{ "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI,
2570a6a1f1dSLionel Sambuc 	  pci_interface_stpci,	},
2587eb99bdaSLionel Sambuc 	{ "InfiniBand",		PCI_SUBCLASS_BRIDGE_INFINIBAND,	NULL,	},
2590a6a1f1dSLionel Sambuc 	{ "advanced switching",	PCI_SUBCLASS_BRIDGE_ADVSW,
2600a6a1f1dSLionel Sambuc 	  pci_interface_advsw,	},
2617eb99bdaSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_BRIDGE_MISC,	NULL,	},
2627eb99bdaSLionel Sambuc 	{ NULL,			0,				NULL,	},
2637eb99bdaSLionel Sambuc };
2647eb99bdaSLionel Sambuc 
2650a6a1f1dSLionel Sambuc /*
2660a6a1f1dSLionel Sambuc  * Class 0x07.
2670a6a1f1dSLionel Sambuc  * Simple communications controller.
2680a6a1f1dSLionel Sambuc  */
2690a6a1f1dSLionel Sambuc 
2700a6a1f1dSLionel Sambuc /* Serial controller programming interface */
2710a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_serial[] = {
2720a6a1f1dSLionel Sambuc 	{ "generic XT-compat",	PCI_INTERFACE_SERIAL_XT,	NULL,	},
2730a6a1f1dSLionel Sambuc 	{ "16450-compat",	PCI_INTERFACE_SERIAL_16450,	NULL,	},
2740a6a1f1dSLionel Sambuc 	{ "16550-compat",	PCI_INTERFACE_SERIAL_16550,	NULL,	},
2750a6a1f1dSLionel Sambuc 	{ "16650-compat",	PCI_INTERFACE_SERIAL_16650,	NULL,	},
2760a6a1f1dSLionel Sambuc 	{ "16750-compat",	PCI_INTERFACE_SERIAL_16750,	NULL,	},
2770a6a1f1dSLionel Sambuc 	{ "16850-compat",	PCI_INTERFACE_SERIAL_16850,	NULL,	},
2780a6a1f1dSLionel Sambuc 	{ "16950-compat",	PCI_INTERFACE_SERIAL_16950,	NULL,	},
2790a6a1f1dSLionel Sambuc 	{ NULL,			0,				NULL,	},
2800a6a1f1dSLionel Sambuc };
2810a6a1f1dSLionel Sambuc 
2820a6a1f1dSLionel Sambuc /* Parallel controller programming interface */
2830a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_parallel[] = {
2840a6a1f1dSLionel Sambuc 	{ "",			PCI_INTERFACE_PARALLEL,			NULL,},
2850a6a1f1dSLionel Sambuc 	{ "bi-directional",	PCI_INTERFACE_PARALLEL_BIDIRECTIONAL,	NULL,},
2860a6a1f1dSLionel Sambuc 	{ "ECP 1.X-compat",	PCI_INTERFACE_PARALLEL_ECP1X,		NULL,},
2870a6a1f1dSLionel Sambuc 	{ "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL,	NULL,},
2880a6a1f1dSLionel Sambuc 	{ "IEEE1284 target",	PCI_INTERFACE_PARALLEL_IEEE1284_TGT,	NULL,},
2890a6a1f1dSLionel Sambuc 	{ NULL,			0,					NULL,},
2900a6a1f1dSLionel Sambuc };
2910a6a1f1dSLionel Sambuc 
2920a6a1f1dSLionel Sambuc /* Modem programming interface */
2930a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_modem[] = {
2940a6a1f1dSLionel Sambuc 	{ "",			PCI_INTERFACE_MODEM,			NULL,},
2950a6a1f1dSLionel Sambuc 	{ "Hayes&16450-compat",	PCI_INTERFACE_MODEM_HAYES16450,		NULL,},
2960a6a1f1dSLionel Sambuc 	{ "Hayes&16550-compat",	PCI_INTERFACE_MODEM_HAYES16550,		NULL,},
2970a6a1f1dSLionel Sambuc 	{ "Hayes&16650-compat",	PCI_INTERFACE_MODEM_HAYES16650,		NULL,},
2980a6a1f1dSLionel Sambuc 	{ "Hayes&16750-compat",	PCI_INTERFACE_MODEM_HAYES16750,		NULL,},
2990a6a1f1dSLionel Sambuc 	{ NULL,			0,					NULL,},
3000a6a1f1dSLionel Sambuc };
3010a6a1f1dSLionel Sambuc 
3020a6a1f1dSLionel Sambuc /* Subclasses */
3037eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_communications[] = {
3040a6a1f1dSLionel Sambuc 	{ "serial",		PCI_SUBCLASS_COMMUNICATIONS_SERIAL,
3050a6a1f1dSLionel Sambuc 	  pci_interface_serial, },
3060a6a1f1dSLionel Sambuc 	{ "parallel",		PCI_SUBCLASS_COMMUNICATIONS_PARALLEL,
3070a6a1f1dSLionel Sambuc 	  pci_interface_parallel, },
3087eb99bdaSLionel Sambuc 	{ "multi-port serial",	PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL,	NULL,},
3090a6a1f1dSLionel Sambuc 	{ "modem",		PCI_SUBCLASS_COMMUNICATIONS_MODEM,
3100a6a1f1dSLionel Sambuc 	  pci_interface_modem, },
3117eb99bdaSLionel Sambuc 	{ "GPIB",		PCI_SUBCLASS_COMMUNICATIONS_GPIB,	NULL,},
3127eb99bdaSLionel Sambuc 	{ "smartcard",		PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD,	NULL,},
3137eb99bdaSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_COMMUNICATIONS_MISC,	NULL,},
3147eb99bdaSLionel Sambuc 	{ NULL,			0,					NULL,},
3157eb99bdaSLionel Sambuc };
3167eb99bdaSLionel Sambuc 
3170a6a1f1dSLionel Sambuc /*
3180a6a1f1dSLionel Sambuc  * Class 0x08.
3190a6a1f1dSLionel Sambuc  * Base system peripheral.
3200a6a1f1dSLionel Sambuc  */
3210a6a1f1dSLionel Sambuc 
3220a6a1f1dSLionel Sambuc /* PIC programming interface */
3230a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_pic[] = {
3240a6a1f1dSLionel Sambuc 	{ "generic 8259",	PCI_INTERFACE_PIC_8259,		NULL,	},
3250a6a1f1dSLionel Sambuc 	{ "ISA PIC",		PCI_INTERFACE_PIC_ISA,		NULL,	},
3260a6a1f1dSLionel Sambuc 	{ "EISA PIC",		PCI_INTERFACE_PIC_EISA,		NULL,	},
3270a6a1f1dSLionel Sambuc 	{ "IO APIC",		PCI_INTERFACE_PIC_IOAPIC,	NULL,	},
3280a6a1f1dSLionel Sambuc 	{ "IO(x) APIC",		PCI_INTERFACE_PIC_IOXAPIC,	NULL,	},
3290a6a1f1dSLionel Sambuc 	{ NULL,			0,				NULL,	},
3300a6a1f1dSLionel Sambuc };
3310a6a1f1dSLionel Sambuc 
3320a6a1f1dSLionel Sambuc /* DMA programming interface */
3330a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_dma[] = {
3340a6a1f1dSLionel Sambuc 	{ "generic 8237",	PCI_INTERFACE_DMA_8237,		NULL,	},
3350a6a1f1dSLionel Sambuc 	{ "ISA",		PCI_INTERFACE_DMA_ISA,		NULL,	},
3360a6a1f1dSLionel Sambuc 	{ "EISA",		PCI_INTERFACE_DMA_EISA,		NULL,	},
3370a6a1f1dSLionel Sambuc 	{ NULL,			0,				NULL,	},
3380a6a1f1dSLionel Sambuc };
3390a6a1f1dSLionel Sambuc 
3400a6a1f1dSLionel Sambuc /* Timer programming interface */
3410a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_tmr[] = {
3420a6a1f1dSLionel Sambuc 	{ "generic 8254",	PCI_INTERFACE_TIMER_8254,	NULL,	},
3430a6a1f1dSLionel Sambuc 	{ "ISA",		PCI_INTERFACE_TIMER_ISA,	NULL,	},
3440a6a1f1dSLionel Sambuc 	{ "EISA",		PCI_INTERFACE_TIMER_EISA,	NULL,	},
3450a6a1f1dSLionel Sambuc 	{ "HPET",		PCI_INTERFACE_TIMER_HPET,	NULL,	},
3460a6a1f1dSLionel Sambuc 	{ NULL,			0,				NULL,	},
3470a6a1f1dSLionel Sambuc };
3480a6a1f1dSLionel Sambuc 
3490a6a1f1dSLionel Sambuc /* RTC programming interface */
3500a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_rtc[] = {
3510a6a1f1dSLionel Sambuc 	{ "generic",		PCI_INTERFACE_RTC_GENERIC,	NULL,	},
3520a6a1f1dSLionel Sambuc 	{ "ISA",		PCI_INTERFACE_RTC_ISA,		NULL,	},
3530a6a1f1dSLionel Sambuc 	{ NULL,			0,				NULL,	},
3540a6a1f1dSLionel Sambuc };
3550a6a1f1dSLionel Sambuc 
3560a6a1f1dSLionel Sambuc /* Subclasses */
3577eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_system[] = {
3580a6a1f1dSLionel Sambuc 	{ "interrupt",		PCI_SUBCLASS_SYSTEM_PIC,   pci_interface_pic,},
3590a6a1f1dSLionel Sambuc 	{ "DMA",		PCI_SUBCLASS_SYSTEM_DMA,   pci_interface_dma,},
3600a6a1f1dSLionel Sambuc 	{ "timer",		PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,},
3610a6a1f1dSLionel Sambuc 	{ "RTC",		PCI_SUBCLASS_SYSTEM_RTC,   pci_interface_rtc,},
3627eb99bdaSLionel Sambuc 	{ "PCI Hot-Plug",	PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL,	},
3637eb99bdaSLionel Sambuc 	{ "SD Host Controller",	PCI_SUBCLASS_SYSTEM_SDHC,	NULL,	},
3640a6a1f1dSLionel Sambuc 	{ "IOMMU",		PCI_SUBCLASS_SYSTEM_IOMMU,	NULL,	},
3650a6a1f1dSLionel Sambuc 	{ "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, },
3667eb99bdaSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_SYSTEM_MISC,	NULL,	},
3677eb99bdaSLionel Sambuc 	{ NULL,			0,				NULL,	},
3687eb99bdaSLionel Sambuc };
3697eb99bdaSLionel Sambuc 
3700a6a1f1dSLionel Sambuc /*
3710a6a1f1dSLionel Sambuc  * Class 0x09.
3720a6a1f1dSLionel Sambuc  * Input device.
3730a6a1f1dSLionel Sambuc  */
3740a6a1f1dSLionel Sambuc 
3750a6a1f1dSLionel Sambuc /* Gameport programming interface */
3760a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_game[] = {
3770a6a1f1dSLionel Sambuc 	{ "generic",		PCI_INTERFACE_GAMEPORT_GENERIC,	NULL,	},
3780a6a1f1dSLionel Sambuc 	{ "legacy",		PCI_INTERFACE_GAMEPORT_LEGACY,	NULL,	},
3790a6a1f1dSLionel Sambuc 	{ NULL,			0,				NULL,	},
3800a6a1f1dSLionel Sambuc };
3810a6a1f1dSLionel Sambuc 
3820a6a1f1dSLionel Sambuc /* Subclasses */
3837eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_input[] = {
3847eb99bdaSLionel Sambuc 	{ "keyboard",		PCI_SUBCLASS_INPUT_KEYBOARD,	NULL,	},
3857eb99bdaSLionel Sambuc 	{ "digitizer",		PCI_SUBCLASS_INPUT_DIGITIZER,	NULL,	},
3867eb99bdaSLionel Sambuc 	{ "mouse",		PCI_SUBCLASS_INPUT_MOUSE,	NULL,	},
3877eb99bdaSLionel Sambuc 	{ "scanner",		PCI_SUBCLASS_INPUT_SCANNER,	NULL,	},
3880a6a1f1dSLionel Sambuc 	{ "game port",		PCI_SUBCLASS_INPUT_GAMEPORT,
3890a6a1f1dSLionel Sambuc 	  pci_interface_game, },
3907eb99bdaSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_INPUT_MISC,	NULL,	},
3917eb99bdaSLionel Sambuc 	{ NULL,			0,				NULL,	},
3927eb99bdaSLionel Sambuc };
3937eb99bdaSLionel Sambuc 
3940a6a1f1dSLionel Sambuc /*
3950a6a1f1dSLionel Sambuc  * Class 0x0a.
3960a6a1f1dSLionel Sambuc  * Docking station.
3970a6a1f1dSLionel Sambuc  */
3987eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_dock[] = {
3997eb99bdaSLionel Sambuc 	{ "generic",		PCI_SUBCLASS_DOCK_GENERIC,	NULL,	},
4007eb99bdaSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_DOCK_MISC,		NULL,	},
4017eb99bdaSLionel Sambuc 	{ NULL,			0,				NULL,	},
4027eb99bdaSLionel Sambuc };
4037eb99bdaSLionel Sambuc 
4040a6a1f1dSLionel Sambuc /*
4050a6a1f1dSLionel Sambuc  * Class 0x0b.
4060a6a1f1dSLionel Sambuc  * Processor.
4070a6a1f1dSLionel Sambuc  */
4087eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_processor[] = {
4097eb99bdaSLionel Sambuc 	{ "386",		PCI_SUBCLASS_PROCESSOR_386,	NULL,	},
4107eb99bdaSLionel Sambuc 	{ "486",		PCI_SUBCLASS_PROCESSOR_486,	NULL,	},
4117eb99bdaSLionel Sambuc 	{ "Pentium",		PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL,	},
4127eb99bdaSLionel Sambuc 	{ "Alpha",		PCI_SUBCLASS_PROCESSOR_ALPHA,	NULL,	},
4137eb99bdaSLionel Sambuc 	{ "PowerPC",		PCI_SUBCLASS_PROCESSOR_POWERPC, NULL,	},
4147eb99bdaSLionel Sambuc 	{ "MIPS",		PCI_SUBCLASS_PROCESSOR_MIPS,	NULL,	},
4157eb99bdaSLionel Sambuc 	{ "Co-processor",	PCI_SUBCLASS_PROCESSOR_COPROC,	NULL,	},
4160a6a1f1dSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_PROCESSOR_MISC,	NULL,	},
4177eb99bdaSLionel Sambuc 	{ NULL,			0,				NULL,	},
4187eb99bdaSLionel Sambuc };
4197eb99bdaSLionel Sambuc 
4200a6a1f1dSLionel Sambuc /*
4210a6a1f1dSLionel Sambuc  * Class 0x0c.
4220a6a1f1dSLionel Sambuc  * Serial bus controller.
4230a6a1f1dSLionel Sambuc  */
4240a6a1f1dSLionel Sambuc 
4250a6a1f1dSLionel Sambuc /* IEEE1394 programming interface */
4260a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_ieee1394[] = {
4270a6a1f1dSLionel Sambuc 	{ "Firewire",		PCI_INTERFACE_IEEE1394_FIREWIRE,	NULL,},
4280a6a1f1dSLionel Sambuc 	{ "OpenHCI",		PCI_INTERFACE_IEEE1394_OPENHCI,		NULL,},
4290a6a1f1dSLionel Sambuc 	{ NULL,			0,					NULL,},
4300a6a1f1dSLionel Sambuc };
4310a6a1f1dSLionel Sambuc 
4320a6a1f1dSLionel Sambuc /* USB programming interface */
4330a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_usb[] = {
4340a6a1f1dSLionel Sambuc 	{ "UHCI",		PCI_INTERFACE_USB_UHCI,		NULL,	},
4350a6a1f1dSLionel Sambuc 	{ "OHCI",		PCI_INTERFACE_USB_OHCI,		NULL,	},
4360a6a1f1dSLionel Sambuc 	{ "EHCI",		PCI_INTERFACE_USB_EHCI,		NULL,	},
4370a6a1f1dSLionel Sambuc 	{ "xHCI",		PCI_INTERFACE_USB_XHCI,		NULL,	},
4380a6a1f1dSLionel Sambuc 	{ "other HC",		PCI_INTERFACE_USB_OTHERHC,	NULL,	},
4390a6a1f1dSLionel Sambuc 	{ "device",		PCI_INTERFACE_USB_DEVICE,	NULL,	},
4400a6a1f1dSLionel Sambuc 	{ NULL,			0,				NULL,	},
4410a6a1f1dSLionel Sambuc };
4420a6a1f1dSLionel Sambuc 
4430a6a1f1dSLionel Sambuc /* IPMI programming interface */
4440a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_ipmi[] = {
4450a6a1f1dSLionel Sambuc 	{ "SMIC",		PCI_INTERFACE_IPMI_SMIC,		NULL,},
4460a6a1f1dSLionel Sambuc 	{ "keyboard",		PCI_INTERFACE_IPMI_KBD,			NULL,},
4470a6a1f1dSLionel Sambuc 	{ "block transfer",	PCI_INTERFACE_IPMI_BLOCKXFER,		NULL,},
4480a6a1f1dSLionel Sambuc 	{ NULL,			0,					NULL,},
4490a6a1f1dSLionel Sambuc };
4500a6a1f1dSLionel Sambuc 
4510a6a1f1dSLionel Sambuc /* Subclasses */
4527eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_serialbus[] = {
4530a6a1f1dSLionel Sambuc 	{ "IEEE1394",		PCI_SUBCLASS_SERIALBUS_FIREWIRE,
4540a6a1f1dSLionel Sambuc 	  pci_interface_ieee1394, },
4557eb99bdaSLionel Sambuc 	{ "ACCESS.bus",		PCI_SUBCLASS_SERIALBUS_ACCESS,	NULL,	},
4567eb99bdaSLionel Sambuc 	{ "SSA",		PCI_SUBCLASS_SERIALBUS_SSA,	NULL,	},
4570a6a1f1dSLionel Sambuc 	{ "USB",		PCI_SUBCLASS_SERIALBUS_USB,
4580a6a1f1dSLionel Sambuc 	  pci_interface_usb, },
4597eb99bdaSLionel Sambuc 	/* XXX Fiber Channel/_FIBRECHANNEL */
4607eb99bdaSLionel Sambuc 	{ "Fiber Channel",	PCI_SUBCLASS_SERIALBUS_FIBER,	NULL,	},
4617eb99bdaSLionel Sambuc 	{ "SMBus",		PCI_SUBCLASS_SERIALBUS_SMBUS,	NULL,	},
4627eb99bdaSLionel Sambuc 	{ "InfiniBand",		PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,},
4630a6a1f1dSLionel Sambuc 	{ "IPMI",		PCI_SUBCLASS_SERIALBUS_IPMI,
4640a6a1f1dSLionel Sambuc 	  pci_interface_ipmi, },
4657eb99bdaSLionel Sambuc 	{ "SERCOS",		PCI_SUBCLASS_SERIALBUS_SERCOS,	NULL,	},
4667eb99bdaSLionel Sambuc 	{ "CANbus",		PCI_SUBCLASS_SERIALBUS_CANBUS,	NULL,	},
4670a6a1f1dSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_SERIALBUS_MISC,	NULL,	},
4687eb99bdaSLionel Sambuc 	{ NULL,			0,				NULL,	},
4697eb99bdaSLionel Sambuc };
4707eb99bdaSLionel Sambuc 
4710a6a1f1dSLionel Sambuc /*
4720a6a1f1dSLionel Sambuc  * Class 0x0d.
4730a6a1f1dSLionel Sambuc  * Wireless Controller.
4740a6a1f1dSLionel Sambuc  */
4757eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_wireless[] = {
4767eb99bdaSLionel Sambuc 	{ "IrDA",		PCI_SUBCLASS_WIRELESS_IRDA,	NULL,	},
4770a6a1f1dSLionel Sambuc 	{ "Consumer IR",/*XXX*/	PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL,	},
4787eb99bdaSLionel Sambuc 	{ "RF",			PCI_SUBCLASS_WIRELESS_RF,	NULL,	},
4797eb99bdaSLionel Sambuc 	{ "bluetooth",		PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL,	},
4807eb99bdaSLionel Sambuc 	{ "broadband",		PCI_SUBCLASS_WIRELESS_BROADBAND, NULL,	},
4817eb99bdaSLionel Sambuc 	{ "802.11a (5 GHz)",	PCI_SUBCLASS_WIRELESS_802_11A,	NULL,	},
4827eb99bdaSLionel Sambuc 	{ "802.11b (2.4 GHz)",	PCI_SUBCLASS_WIRELESS_802_11B,	NULL,	},
4837eb99bdaSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_WIRELESS_MISC,	NULL,	},
4847eb99bdaSLionel Sambuc 	{ NULL,			0,				NULL,	},
4857eb99bdaSLionel Sambuc };
4867eb99bdaSLionel Sambuc 
4870a6a1f1dSLionel Sambuc /*
4880a6a1f1dSLionel Sambuc  * Class 0x0e.
4890a6a1f1dSLionel Sambuc  * Intelligent IO controller.
4900a6a1f1dSLionel Sambuc  */
4910a6a1f1dSLionel Sambuc 
4920a6a1f1dSLionel Sambuc /* Intelligent IO programming interface */
4930a6a1f1dSLionel Sambuc static const struct pci_class pci_interface_i2o[] = {
4940a6a1f1dSLionel Sambuc 	{ "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40,		NULL,},
4957eb99bdaSLionel Sambuc 	{ NULL,			0,					NULL,},
4967eb99bdaSLionel Sambuc };
4977eb99bdaSLionel Sambuc 
4980a6a1f1dSLionel Sambuc /* Subclasses */
4990a6a1f1dSLionel Sambuc static const struct pci_class pci_subclass_i2o[] = {
5000a6a1f1dSLionel Sambuc 	{ "standard",		PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,},
5010a6a1f1dSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_I2O_MISC,		NULL,	},
5020a6a1f1dSLionel Sambuc 	{ NULL,			0,				NULL,	},
5030a6a1f1dSLionel Sambuc };
5040a6a1f1dSLionel Sambuc 
5050a6a1f1dSLionel Sambuc /*
5060a6a1f1dSLionel Sambuc  * Class 0x0f.
5070a6a1f1dSLionel Sambuc  * Satellite communication controller.
5080a6a1f1dSLionel Sambuc  */
5097eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_satcom[] = {
5107eb99bdaSLionel Sambuc 	{ "TV",			PCI_SUBCLASS_SATCOM_TV,	 	NULL,	},
5117eb99bdaSLionel Sambuc 	{ "audio",		PCI_SUBCLASS_SATCOM_AUDIO, 	NULL,	},
5127eb99bdaSLionel Sambuc 	{ "voice",		PCI_SUBCLASS_SATCOM_VOICE, 	NULL,	},
5137eb99bdaSLionel Sambuc 	{ "data",		PCI_SUBCLASS_SATCOM_DATA,	NULL,	},
5140a6a1f1dSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_SATCOM_MISC,	NULL,	},
5157eb99bdaSLionel Sambuc 	{ NULL,			0,				NULL,	},
5167eb99bdaSLionel Sambuc };
5177eb99bdaSLionel Sambuc 
5180a6a1f1dSLionel Sambuc /*
5190a6a1f1dSLionel Sambuc  * Class 0x10.
5200a6a1f1dSLionel Sambuc  * Encryption/Decryption controller.
5210a6a1f1dSLionel Sambuc  */
5227eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_crypto[] = {
5237eb99bdaSLionel Sambuc 	{ "network/computing",	PCI_SUBCLASS_CRYPTO_NETCOMP, 	NULL,	},
5247eb99bdaSLionel Sambuc 	{ "entertainment",	PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,},
5257eb99bdaSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_CRYPTO_MISC, 	NULL,	},
5267eb99bdaSLionel Sambuc 	{ NULL,			0,				NULL,	},
5277eb99bdaSLionel Sambuc };
5287eb99bdaSLionel Sambuc 
5290a6a1f1dSLionel Sambuc /*
5300a6a1f1dSLionel Sambuc  * Class 0x11.
5310a6a1f1dSLionel Sambuc  * Data aquuisition and signal processing controller.
5320a6a1f1dSLionel Sambuc  */
5337eb99bdaSLionel Sambuc static const struct pci_class pci_subclass_dasp[] = {
5347eb99bdaSLionel Sambuc 	{ "DPIO",		PCI_SUBCLASS_DASP_DPIO,		NULL,	},
5350a6a1f1dSLionel Sambuc 	{ "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ,	NULL,	},
5367eb99bdaSLionel Sambuc 	{ "synchronization",	PCI_SUBCLASS_DASP_SYNC,		NULL,	},
5377eb99bdaSLionel Sambuc 	{ "management",		PCI_SUBCLASS_DASP_MGMT,		NULL,	},
5387eb99bdaSLionel Sambuc 	{ "miscellaneous",	PCI_SUBCLASS_DASP_MISC,		NULL,	},
5397eb99bdaSLionel Sambuc 	{ NULL,			0,				NULL,	},
5407eb99bdaSLionel Sambuc };
5417eb99bdaSLionel Sambuc 
5420a6a1f1dSLionel Sambuc /* List of classes */
5437eb99bdaSLionel Sambuc static const struct pci_class pci_class[] = {
5447eb99bdaSLionel Sambuc 	{ "prehistoric",	PCI_CLASS_PREHISTORIC,
5457eb99bdaSLionel Sambuc 	    pci_subclass_prehistoric,				},
5467eb99bdaSLionel Sambuc 	{ "mass storage",	PCI_CLASS_MASS_STORAGE,
5477eb99bdaSLionel Sambuc 	    pci_subclass_mass_storage,				},
5487eb99bdaSLionel Sambuc 	{ "network",		PCI_CLASS_NETWORK,
5497eb99bdaSLionel Sambuc 	    pci_subclass_network,				},
5507eb99bdaSLionel Sambuc 	{ "display",		PCI_CLASS_DISPLAY,
5517eb99bdaSLionel Sambuc 	    pci_subclass_display,				},
5527eb99bdaSLionel Sambuc 	{ "multimedia",		PCI_CLASS_MULTIMEDIA,
5537eb99bdaSLionel Sambuc 	    pci_subclass_multimedia,				},
5547eb99bdaSLionel Sambuc 	{ "memory",		PCI_CLASS_MEMORY,
5557eb99bdaSLionel Sambuc 	    pci_subclass_memory,				},
5567eb99bdaSLionel Sambuc 	{ "bridge",		PCI_CLASS_BRIDGE,
5577eb99bdaSLionel Sambuc 	    pci_subclass_bridge,				},
5587eb99bdaSLionel Sambuc 	{ "communications",	PCI_CLASS_COMMUNICATIONS,
5597eb99bdaSLionel Sambuc 	    pci_subclass_communications,			},
5607eb99bdaSLionel Sambuc 	{ "system",		PCI_CLASS_SYSTEM,
5617eb99bdaSLionel Sambuc 	    pci_subclass_system,				},
5627eb99bdaSLionel Sambuc 	{ "input",		PCI_CLASS_INPUT,
5637eb99bdaSLionel Sambuc 	    pci_subclass_input,					},
5647eb99bdaSLionel Sambuc 	{ "dock",		PCI_CLASS_DOCK,
5657eb99bdaSLionel Sambuc 	    pci_subclass_dock,					},
5667eb99bdaSLionel Sambuc 	{ "processor",		PCI_CLASS_PROCESSOR,
5677eb99bdaSLionel Sambuc 	    pci_subclass_processor,				},
5687eb99bdaSLionel Sambuc 	{ "serial bus",		PCI_CLASS_SERIALBUS,
5697eb99bdaSLionel Sambuc 	    pci_subclass_serialbus,				},
5707eb99bdaSLionel Sambuc 	{ "wireless",		PCI_CLASS_WIRELESS,
5717eb99bdaSLionel Sambuc 	    pci_subclass_wireless,				},
5727eb99bdaSLionel Sambuc 	{ "I2O",		PCI_CLASS_I2O,
5737eb99bdaSLionel Sambuc 	    pci_subclass_i2o,					},
5747eb99bdaSLionel Sambuc 	{ "satellite comm",	PCI_CLASS_SATCOM,
5757eb99bdaSLionel Sambuc 	    pci_subclass_satcom,				},
5767eb99bdaSLionel Sambuc 	{ "crypto",		PCI_CLASS_CRYPTO,
5777eb99bdaSLionel Sambuc 	    pci_subclass_crypto,				},
5787eb99bdaSLionel Sambuc 	{ "DASP",		PCI_CLASS_DASP,
5797eb99bdaSLionel Sambuc 	    pci_subclass_dasp,					},
5807eb99bdaSLionel Sambuc 	{ "undefined",		PCI_CLASS_UNDEFINED,
5817eb99bdaSLionel Sambuc 	    NULL,						},
5827eb99bdaSLionel Sambuc 	{ NULL,			0,
5837eb99bdaSLionel Sambuc 	    NULL,						},
5847eb99bdaSLionel Sambuc };
5857eb99bdaSLionel Sambuc 
5863641562fSLionel Sambuc #if defined(__minix) && defined(_PCI_SERVER)
5873641562fSLionel Sambuc const char *
pci_baseclass_name(pcireg_t reg)5883641562fSLionel Sambuc pci_baseclass_name(pcireg_t reg)
5893641562fSLionel Sambuc {
5903641562fSLionel Sambuc 	const struct pci_class *classp = pci_class;
5913641562fSLionel Sambuc 
5923641562fSLionel Sambuc 	while (classp->name != NULL) {
5933641562fSLionel Sambuc 		if (PCI_CLASS(reg) == classp->val)
5943641562fSLionel Sambuc 			break;
5953641562fSLionel Sambuc 		classp++;
5963641562fSLionel Sambuc 	}
5973641562fSLionel Sambuc 
5983641562fSLionel Sambuc 	return classp->name;
5993641562fSLionel Sambuc }
6003641562fSLionel Sambuc 
6013641562fSLionel Sambuc const char *
pci_subclass_name(pcireg_t reg)6023641562fSLionel Sambuc pci_subclass_name(pcireg_t reg)
6033641562fSLionel Sambuc {
6043641562fSLionel Sambuc 	const struct pci_class *classp = pci_class;
6053641562fSLionel Sambuc 	const struct pci_class *subclassp;
6063641562fSLionel Sambuc 
6073641562fSLionel Sambuc 	while (classp->name != NULL) {
6083641562fSLionel Sambuc 		if (PCI_CLASS(reg) == classp->val)
6093641562fSLionel Sambuc 			break;
6103641562fSLionel Sambuc 		classp++;
6113641562fSLionel Sambuc 	}
6123641562fSLionel Sambuc 
6133641562fSLionel Sambuc 	subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
6143641562fSLionel Sambuc 	while (subclassp && subclassp->name != NULL) {
6153641562fSLionel Sambuc 		if (PCI_SUBCLASS(reg) == subclassp->val)
6163641562fSLionel Sambuc 			break;
6173641562fSLionel Sambuc 		subclassp++;
6183641562fSLionel Sambuc 	}
6193641562fSLionel Sambuc 
620*b2ee0702SKrystian Lewandowski 	if (subclassp) {
6213641562fSLionel Sambuc 		return subclassp->name;
622*b2ee0702SKrystian Lewandowski 	} else {
623*b2ee0702SKrystian Lewandowski 		return NULL;
624*b2ee0702SKrystian Lewandowski 	}
6253641562fSLionel Sambuc }
6260a6a1f1dSLionel Sambuc #endif /* defined(__minix) && defined(_PCI_SERVER) */
6273641562fSLionel Sambuc 
6280a6a1f1dSLionel Sambuc DEV_VERBOSE_DEFINE(pci);
6297eb99bdaSLionel Sambuc 
6300a6a1f1dSLionel Sambuc #if defined(__minix) && !defined(_PCI_SERVER)
6317eb99bdaSLionel Sambuc 
6327eb99bdaSLionel Sambuc void
pci_devinfo(pcireg_t id_reg,pcireg_t class_reg,int showclass,char * cp,size_t l)6337eb99bdaSLionel Sambuc pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp,
6347eb99bdaSLionel Sambuc     size_t l)
6357eb99bdaSLionel Sambuc {
6360a6a1f1dSLionel Sambuc 	pci_class_t pciclass;
6377eb99bdaSLionel Sambuc 	pci_subclass_t subclass;
6387eb99bdaSLionel Sambuc 	pci_interface_t interface;
6397eb99bdaSLionel Sambuc 	pci_revision_t revision;
6400a6a1f1dSLionel Sambuc 	char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN];
6410a6a1f1dSLionel Sambuc 	const struct pci_class *classp, *subclassp, *interfacep;
6427eb99bdaSLionel Sambuc 	char *ep;
6437eb99bdaSLionel Sambuc 
6447eb99bdaSLionel Sambuc 	ep = cp + l;
6457eb99bdaSLionel Sambuc 
6460a6a1f1dSLionel Sambuc 	pciclass = PCI_CLASS(class_reg);
6477eb99bdaSLionel Sambuc 	subclass = PCI_SUBCLASS(class_reg);
6487eb99bdaSLionel Sambuc 	interface = PCI_INTERFACE(class_reg);
6497eb99bdaSLionel Sambuc 	revision = PCI_REVISION(class_reg);
6507eb99bdaSLionel Sambuc 
6510a6a1f1dSLionel Sambuc 	pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg));
6520a6a1f1dSLionel Sambuc 	pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg),
6530a6a1f1dSLionel Sambuc 	    PCI_PRODUCT(id_reg));
6547eb99bdaSLionel Sambuc 
6557eb99bdaSLionel Sambuc 	classp = pci_class;
6567eb99bdaSLionel Sambuc 	while (classp->name != NULL) {
6570a6a1f1dSLionel Sambuc 		if (pciclass == classp->val)
6587eb99bdaSLionel Sambuc 			break;
6597eb99bdaSLionel Sambuc 		classp++;
6607eb99bdaSLionel Sambuc 	}
6617eb99bdaSLionel Sambuc 
6627eb99bdaSLionel Sambuc 	subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
6637eb99bdaSLionel Sambuc 	while (subclassp && subclassp->name != NULL) {
6647eb99bdaSLionel Sambuc 		if (subclass == subclassp->val)
6657eb99bdaSLionel Sambuc 			break;
6667eb99bdaSLionel Sambuc 		subclassp++;
6677eb99bdaSLionel Sambuc 	}
6687eb99bdaSLionel Sambuc 
6690a6a1f1dSLionel Sambuc 	interfacep = (subclassp && subclassp->name != NULL) ?
6700a6a1f1dSLionel Sambuc 	    subclassp->subclasses : NULL;
6710a6a1f1dSLionel Sambuc 	while (interfacep && interfacep->name != NULL) {
6720a6a1f1dSLionel Sambuc 		if (interface == interfacep->val)
6730a6a1f1dSLionel Sambuc 			break;
6740a6a1f1dSLionel Sambuc 		interfacep++;
6750a6a1f1dSLionel Sambuc 	}
6760a6a1f1dSLionel Sambuc 
6770a6a1f1dSLionel Sambuc 	cp += snprintf(cp, ep - cp, "%s %s", vendor, product);
6787eb99bdaSLionel Sambuc 	if (showclass) {
6797eb99bdaSLionel Sambuc 		cp += snprintf(cp, ep - cp, " (");
6807eb99bdaSLionel Sambuc 		if (classp->name == NULL)
6817eb99bdaSLionel Sambuc 			cp += snprintf(cp, ep - cp,
6820a6a1f1dSLionel Sambuc 			    "class 0x%02x, subclass 0x%02x", pciclass, subclass);
6837eb99bdaSLionel Sambuc 		else {
6847eb99bdaSLionel Sambuc 			if (subclassp == NULL || subclassp->name == NULL)
6857eb99bdaSLionel Sambuc 				cp += snprintf(cp, ep - cp,
6867eb99bdaSLionel Sambuc 				    "%s, subclass 0x%02x",
6877eb99bdaSLionel Sambuc 				    classp->name, subclass);
6887eb99bdaSLionel Sambuc 			else
6897eb99bdaSLionel Sambuc 				cp += snprintf(cp, ep - cp, "%s %s",
6907eb99bdaSLionel Sambuc 				    subclassp->name, classp->name);
6917eb99bdaSLionel Sambuc 		}
6920a6a1f1dSLionel Sambuc 		if ((interfacep == NULL) || (interfacep->name == NULL)) {
6937eb99bdaSLionel Sambuc 			if (interface != 0)
6940a6a1f1dSLionel Sambuc 				cp += snprintf(cp, ep - cp,
6950a6a1f1dSLionel Sambuc 				    ", interface 0x%02x", interface);
6960a6a1f1dSLionel Sambuc 		} else if (strncmp(interfacep->name, "", 1) != 0)
6970a6a1f1dSLionel Sambuc 			cp += snprintf(cp, ep - cp, ", %s",
6980a6a1f1dSLionel Sambuc 			    interfacep->name);
6997eb99bdaSLionel Sambuc 		if (revision != 0)
7007eb99bdaSLionel Sambuc 			cp += snprintf(cp, ep - cp, ", revision 0x%02x",
7017eb99bdaSLionel Sambuc 			    revision);
7027eb99bdaSLionel Sambuc 		cp += snprintf(cp, ep - cp, ")");
7037eb99bdaSLionel Sambuc 	}
7047eb99bdaSLionel Sambuc }
7057eb99bdaSLionel Sambuc 
7067eb99bdaSLionel Sambuc #ifdef _KERNEL
7077eb99bdaSLionel Sambuc void
pci_aprint_devinfo_fancy(const struct pci_attach_args * pa,const char * naive,const char * known,int addrev)7087eb99bdaSLionel Sambuc pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive,
7097eb99bdaSLionel Sambuc 			 const char *known, int addrev)
7107eb99bdaSLionel Sambuc {
7117eb99bdaSLionel Sambuc 	char devinfo[256];
7127eb99bdaSLionel Sambuc 
7137eb99bdaSLionel Sambuc 	if (known) {
7147eb99bdaSLionel Sambuc 		aprint_normal(": %s", known);
7157eb99bdaSLionel Sambuc 		if (addrev)
7167eb99bdaSLionel Sambuc 			aprint_normal(" (rev. 0x%02x)",
7177eb99bdaSLionel Sambuc 				      PCI_REVISION(pa->pa_class));
7187eb99bdaSLionel Sambuc 		aprint_normal("\n");
7197eb99bdaSLionel Sambuc 	} else {
7207eb99bdaSLionel Sambuc 		pci_devinfo(pa->pa_id, pa->pa_class, 0,
7217eb99bdaSLionel Sambuc 			    devinfo, sizeof(devinfo));
7227eb99bdaSLionel Sambuc 		aprint_normal(": %s (rev. 0x%02x)\n", devinfo,
7237eb99bdaSLionel Sambuc 			      PCI_REVISION(pa->pa_class));
7247eb99bdaSLionel Sambuc 	}
7257eb99bdaSLionel Sambuc 	if (naive)
7267eb99bdaSLionel Sambuc 		aprint_naive(": %s\n", naive);
7277eb99bdaSLionel Sambuc 	else
7287eb99bdaSLionel Sambuc 		aprint_naive("\n");
7297eb99bdaSLionel Sambuc }
7307eb99bdaSLionel Sambuc #endif
7317eb99bdaSLionel Sambuc 
7327eb99bdaSLionel Sambuc /*
7337eb99bdaSLionel Sambuc  * Print out most of the PCI configuration registers.  Typically used
7347eb99bdaSLionel Sambuc  * in a device attach routine like this:
7357eb99bdaSLionel Sambuc  *
7367eb99bdaSLionel Sambuc  *	#ifdef MYDEV_DEBUG
7377eb99bdaSLionel Sambuc  *		printf("%s: ", device_xname(sc->sc_dev));
7387eb99bdaSLionel Sambuc  *		pci_conf_print(pa->pa_pc, pa->pa_tag, NULL);
7397eb99bdaSLionel Sambuc  *	#endif
7407eb99bdaSLionel Sambuc  */
7417eb99bdaSLionel Sambuc 
7427eb99bdaSLionel Sambuc #define	i2o(i)	((i) * 4)
7437eb99bdaSLionel Sambuc #define	o2i(o)	((o) / 4)
7440a6a1f1dSLionel Sambuc #define	onoff2(str, rval, bit, onstr, offstr)				      \
7450a6a1f1dSLionel Sambuc 	printf("      %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr);
7460a6a1f1dSLionel Sambuc #define	onoff(str, rval, bit)	onoff2(str, rval, bit, "on", "off")
7477eb99bdaSLionel Sambuc 
7487eb99bdaSLionel Sambuc static void
pci_conf_print_common(pci_chipset_tag_t pc,pcitag_t tag,const pcireg_t * regs)7497eb99bdaSLionel Sambuc pci_conf_print_common(
7507eb99bdaSLionel Sambuc #ifdef _KERNEL
7517eb99bdaSLionel Sambuc     pci_chipset_tag_t pc, pcitag_t tag,
7527eb99bdaSLionel Sambuc #endif
7537eb99bdaSLionel Sambuc     const pcireg_t *regs)
7547eb99bdaSLionel Sambuc {
7557eb99bdaSLionel Sambuc 	const char *name;
7567eb99bdaSLionel Sambuc 	const struct pci_class *classp, *subclassp;
7570a6a1f1dSLionel Sambuc 	char vendor[PCI_VENDORSTR_LEN];
7580a6a1f1dSLionel Sambuc 	char product[PCI_PRODUCTSTR_LEN];
7597eb99bdaSLionel Sambuc 	pcireg_t rval;
7600a6a1f1dSLionel Sambuc 	unsigned int num;
7617eb99bdaSLionel Sambuc 
7627eb99bdaSLionel Sambuc 	rval = regs[o2i(PCI_ID_REG)];
7630a6a1f1dSLionel Sambuc 	name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval));
7647eb99bdaSLionel Sambuc 	if (name)
7657eb99bdaSLionel Sambuc 		printf("    Vendor Name: %s (0x%04x)\n", name,
7667eb99bdaSLionel Sambuc 		    PCI_VENDOR(rval));
7677eb99bdaSLionel Sambuc 	else
7687eb99bdaSLionel Sambuc 		printf("    Vendor ID: 0x%04x\n", PCI_VENDOR(rval));
7690a6a1f1dSLionel Sambuc 	name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval),
7700a6a1f1dSLionel Sambuc 	    PCI_PRODUCT(rval));
7717eb99bdaSLionel Sambuc 	if (name)
7727eb99bdaSLionel Sambuc 		printf("    Device Name: %s (0x%04x)\n", name,
7737eb99bdaSLionel Sambuc 		    PCI_PRODUCT(rval));
7747eb99bdaSLionel Sambuc 	else
7757eb99bdaSLionel Sambuc 		printf("    Device ID: 0x%04x\n", PCI_PRODUCT(rval));
7767eb99bdaSLionel Sambuc 
7777eb99bdaSLionel Sambuc 	rval = regs[o2i(PCI_COMMAND_STATUS_REG)];
7787eb99bdaSLionel Sambuc 
7797eb99bdaSLionel Sambuc 	printf("    Command register: 0x%04x\n", rval & 0xffff);
7800a6a1f1dSLionel Sambuc 	onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE);
7810a6a1f1dSLionel Sambuc 	onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE);
7820a6a1f1dSLionel Sambuc 	onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE);
7830a6a1f1dSLionel Sambuc 	onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE);
7840a6a1f1dSLionel Sambuc 	onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE);
7850a6a1f1dSLionel Sambuc 	onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE);
7860a6a1f1dSLionel Sambuc 	onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE);
7870a6a1f1dSLionel Sambuc 	onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE);
7880a6a1f1dSLionel Sambuc 	onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE);
7890a6a1f1dSLionel Sambuc 	onoff("Fast back-to-back transactions", rval,
7900a6a1f1dSLionel Sambuc 	    PCI_COMMAND_BACKTOBACK_ENABLE);
7910a6a1f1dSLionel Sambuc 	onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE);
7927eb99bdaSLionel Sambuc 
7937eb99bdaSLionel Sambuc 	printf("    Status register: 0x%04x\n", (rval >> 16) & 0xffff);
7940a6a1f1dSLionel Sambuc 	onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active",
7950a6a1f1dSLionel Sambuc 	    "inactive");
7960a6a1f1dSLionel Sambuc 	onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT);
7970a6a1f1dSLionel Sambuc 	onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT);
7980a6a1f1dSLionel Sambuc 	onoff("User Definable Features (UDF) support", rval,
7990a6a1f1dSLionel Sambuc 	    PCI_STATUS_UDF_SUPPORT);
8000a6a1f1dSLionel Sambuc 	onoff("Fast back-to-back capable", rval,
8010a6a1f1dSLionel Sambuc 	    PCI_STATUS_BACKTOBACK_SUPPORT);
8020a6a1f1dSLionel Sambuc 	onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR);
8037eb99bdaSLionel Sambuc 
8047eb99bdaSLionel Sambuc 	printf("      DEVSEL timing: ");
8057eb99bdaSLionel Sambuc 	switch (rval & PCI_STATUS_DEVSEL_MASK) {
8067eb99bdaSLionel Sambuc 	case PCI_STATUS_DEVSEL_FAST:
8077eb99bdaSLionel Sambuc 		printf("fast");
8087eb99bdaSLionel Sambuc 		break;
8097eb99bdaSLionel Sambuc 	case PCI_STATUS_DEVSEL_MEDIUM:
8107eb99bdaSLionel Sambuc 		printf("medium");
8117eb99bdaSLionel Sambuc 		break;
8127eb99bdaSLionel Sambuc 	case PCI_STATUS_DEVSEL_SLOW:
8137eb99bdaSLionel Sambuc 		printf("slow");
8147eb99bdaSLionel Sambuc 		break;
8157eb99bdaSLionel Sambuc 	default:
8167eb99bdaSLionel Sambuc 		printf("unknown/reserved");	/* XXX */
8177eb99bdaSLionel Sambuc 		break;
8187eb99bdaSLionel Sambuc 	}
8197eb99bdaSLionel Sambuc 	printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25);
8207eb99bdaSLionel Sambuc 
8210a6a1f1dSLionel Sambuc 	onoff("Slave signaled Target Abort", rval,
8220a6a1f1dSLionel Sambuc 	    PCI_STATUS_TARGET_TARGET_ABORT);
8230a6a1f1dSLionel Sambuc 	onoff("Master received Target Abort", rval,
8240a6a1f1dSLionel Sambuc 	    PCI_STATUS_MASTER_TARGET_ABORT);
8250a6a1f1dSLionel Sambuc 	onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT);
8260a6a1f1dSLionel Sambuc 	onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR);
8270a6a1f1dSLionel Sambuc 	onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT);
8287eb99bdaSLionel Sambuc 
8297eb99bdaSLionel Sambuc 	rval = regs[o2i(PCI_CLASS_REG)];
8307eb99bdaSLionel Sambuc 	for (classp = pci_class; classp->name != NULL; classp++) {
8317eb99bdaSLionel Sambuc 		if (PCI_CLASS(rval) == classp->val)
8327eb99bdaSLionel Sambuc 			break;
8337eb99bdaSLionel Sambuc 	}
8347eb99bdaSLionel Sambuc 	subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
8357eb99bdaSLionel Sambuc 	while (subclassp && subclassp->name != NULL) {
8367eb99bdaSLionel Sambuc 		if (PCI_SUBCLASS(rval) == subclassp->val)
8377eb99bdaSLionel Sambuc 			break;
8387eb99bdaSLionel Sambuc 		subclassp++;
8397eb99bdaSLionel Sambuc 	}
8407eb99bdaSLionel Sambuc 	if (classp->name != NULL) {
8417eb99bdaSLionel Sambuc 		printf("    Class Name: %s (0x%02x)\n", classp->name,
8427eb99bdaSLionel Sambuc 		    PCI_CLASS(rval));
8437eb99bdaSLionel Sambuc 		if (subclassp != NULL && subclassp->name != NULL)
8447eb99bdaSLionel Sambuc 			printf("    Subclass Name: %s (0x%02x)\n",
8457eb99bdaSLionel Sambuc 			    subclassp->name, PCI_SUBCLASS(rval));
8467eb99bdaSLionel Sambuc 		else
8470a6a1f1dSLionel Sambuc 			printf("    Subclass ID: 0x%02x\n",
8480a6a1f1dSLionel Sambuc 			    PCI_SUBCLASS(rval));
8497eb99bdaSLionel Sambuc 	} else {
8507eb99bdaSLionel Sambuc 		printf("    Class ID: 0x%02x\n", PCI_CLASS(rval));
8517eb99bdaSLionel Sambuc 		printf("    Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval));
8527eb99bdaSLionel Sambuc 	}
8537eb99bdaSLionel Sambuc 	printf("    Interface: 0x%02x\n", PCI_INTERFACE(rval));
8547eb99bdaSLionel Sambuc 	printf("    Revision ID: 0x%02x\n", PCI_REVISION(rval));
8557eb99bdaSLionel Sambuc 
8567eb99bdaSLionel Sambuc 	rval = regs[o2i(PCI_BHLC_REG)];
8577eb99bdaSLionel Sambuc 	printf("    BIST: 0x%02x\n", PCI_BIST(rval));
8587eb99bdaSLionel Sambuc 	printf("    Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval),
8597eb99bdaSLionel Sambuc 	    PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "",
8607eb99bdaSLionel Sambuc 	    PCI_HDRTYPE(rval));
8617eb99bdaSLionel Sambuc 	printf("    Latency Timer: 0x%02x\n", PCI_LATTIMER(rval));
8620a6a1f1dSLionel Sambuc 	num = PCI_CACHELINE(rval);
8630a6a1f1dSLionel Sambuc 	printf("    Cache Line Size: %ubytes (0x%02x)\n", num * 4, num);
8647eb99bdaSLionel Sambuc }
8657eb99bdaSLionel Sambuc 
8667eb99bdaSLionel Sambuc static int
pci_conf_print_bar(pci_chipset_tag_t pc,pcitag_t tag,const pcireg_t * regs,int reg,const char * name,int sizebar)8677eb99bdaSLionel Sambuc pci_conf_print_bar(
8687eb99bdaSLionel Sambuc #ifdef _KERNEL
8697eb99bdaSLionel Sambuc     pci_chipset_tag_t pc, pcitag_t tag,
8707eb99bdaSLionel Sambuc #endif
8717eb99bdaSLionel Sambuc     const pcireg_t *regs, int reg, const char *name
8727eb99bdaSLionel Sambuc #ifdef _KERNEL
8737eb99bdaSLionel Sambuc     , int sizebar
8747eb99bdaSLionel Sambuc #endif
8757eb99bdaSLionel Sambuc     )
8767eb99bdaSLionel Sambuc {
8777eb99bdaSLionel Sambuc 	int width;
8787eb99bdaSLionel Sambuc 	pcireg_t rval, rval64h;
8797eb99bdaSLionel Sambuc #ifdef _KERNEL
8807eb99bdaSLionel Sambuc 	int s;
8817eb99bdaSLionel Sambuc 	pcireg_t mask, mask64h;
8827eb99bdaSLionel Sambuc #endif
8837eb99bdaSLionel Sambuc 
8847eb99bdaSLionel Sambuc 	width = 4;
8857eb99bdaSLionel Sambuc 
8867eb99bdaSLionel Sambuc 	/*
8877eb99bdaSLionel Sambuc 	 * Section 6.2.5.1, `Address Maps', tells us that:
8887eb99bdaSLionel Sambuc 	 *
8897eb99bdaSLionel Sambuc 	 * 1) The builtin software should have already mapped the
8907eb99bdaSLionel Sambuc 	 * device in a reasonable way.
8917eb99bdaSLionel Sambuc 	 *
8927eb99bdaSLionel Sambuc 	 * 2) A device which wants 2^n bytes of memory will hardwire
8937eb99bdaSLionel Sambuc 	 * the bottom n bits of the address to 0.  As recommended,
8947eb99bdaSLionel Sambuc 	 * we write all 1s and see what we get back.
8957eb99bdaSLionel Sambuc 	 */
8967eb99bdaSLionel Sambuc 
8977eb99bdaSLionel Sambuc 	rval = regs[o2i(reg)];
8987eb99bdaSLionel Sambuc 	if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
8997eb99bdaSLionel Sambuc 	    PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
9007eb99bdaSLionel Sambuc 		rval64h = regs[o2i(reg + 4)];
9017eb99bdaSLionel Sambuc 		width = 8;
9027eb99bdaSLionel Sambuc 	} else
9037eb99bdaSLionel Sambuc 		rval64h = 0;
9047eb99bdaSLionel Sambuc 
9057eb99bdaSLionel Sambuc #ifdef _KERNEL
9067eb99bdaSLionel Sambuc 	/* XXX don't size unknown memory type? */
9077eb99bdaSLionel Sambuc 	if (rval != 0 && sizebar) {
9087eb99bdaSLionel Sambuc 		/*
9097eb99bdaSLionel Sambuc 		 * The following sequence seems to make some devices
9107eb99bdaSLionel Sambuc 		 * (e.g. host bus bridges, which don't normally
9117eb99bdaSLionel Sambuc 		 * have their space mapped) very unhappy, to
9127eb99bdaSLionel Sambuc 		 * the point of crashing the system.
9137eb99bdaSLionel Sambuc 		 *
9147eb99bdaSLionel Sambuc 		 * Therefore, if the mapping register is zero to
9157eb99bdaSLionel Sambuc 		 * start out with, don't bother trying.
9167eb99bdaSLionel Sambuc 		 */
9177eb99bdaSLionel Sambuc 		s = splhigh();
9187eb99bdaSLionel Sambuc 		pci_conf_write(pc, tag, reg, 0xffffffff);
9197eb99bdaSLionel Sambuc 		mask = pci_conf_read(pc, tag, reg);
9207eb99bdaSLionel Sambuc 		pci_conf_write(pc, tag, reg, rval);
9217eb99bdaSLionel Sambuc 		if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
9227eb99bdaSLionel Sambuc 		    PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
9237eb99bdaSLionel Sambuc 			pci_conf_write(pc, tag, reg + 4, 0xffffffff);
9247eb99bdaSLionel Sambuc 			mask64h = pci_conf_read(pc, tag, reg + 4);
9257eb99bdaSLionel Sambuc 			pci_conf_write(pc, tag, reg + 4, rval64h);
9267eb99bdaSLionel Sambuc 		} else
9277eb99bdaSLionel Sambuc 			mask64h = 0;
9287eb99bdaSLionel Sambuc 		splx(s);
9297eb99bdaSLionel Sambuc 	} else
9307eb99bdaSLionel Sambuc 		mask = mask64h = 0;
9317eb99bdaSLionel Sambuc #endif /* _KERNEL */
9327eb99bdaSLionel Sambuc 
9337eb99bdaSLionel Sambuc 	printf("    Base address register at 0x%02x", reg);
9347eb99bdaSLionel Sambuc 	if (name)
9357eb99bdaSLionel Sambuc 		printf(" (%s)", name);
9367eb99bdaSLionel Sambuc 	printf("\n      ");
9377eb99bdaSLionel Sambuc 	if (rval == 0) {
9387eb99bdaSLionel Sambuc 		printf("not implemented(?)\n");
9397eb99bdaSLionel Sambuc 		return width;
9407eb99bdaSLionel Sambuc 	}
9417eb99bdaSLionel Sambuc 	printf("type: ");
9427eb99bdaSLionel Sambuc 	if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) {
9437eb99bdaSLionel Sambuc 		const char *type, *prefetch;
9447eb99bdaSLionel Sambuc 
9457eb99bdaSLionel Sambuc 		switch (PCI_MAPREG_MEM_TYPE(rval)) {
9467eb99bdaSLionel Sambuc 		case PCI_MAPREG_MEM_TYPE_32BIT:
9477eb99bdaSLionel Sambuc 			type = "32-bit";
9487eb99bdaSLionel Sambuc 			break;
9497eb99bdaSLionel Sambuc 		case PCI_MAPREG_MEM_TYPE_32BIT_1M:
9507eb99bdaSLionel Sambuc 			type = "32-bit-1M";
9517eb99bdaSLionel Sambuc 			break;
9527eb99bdaSLionel Sambuc 		case PCI_MAPREG_MEM_TYPE_64BIT:
9537eb99bdaSLionel Sambuc 			type = "64-bit";
9547eb99bdaSLionel Sambuc 			break;
9557eb99bdaSLionel Sambuc 		default:
9567eb99bdaSLionel Sambuc 			type = "unknown (XXX)";
9577eb99bdaSLionel Sambuc 			break;
9587eb99bdaSLionel Sambuc 		}
9597eb99bdaSLionel Sambuc 		if (PCI_MAPREG_MEM_PREFETCHABLE(rval))
9607eb99bdaSLionel Sambuc 			prefetch = "";
9617eb99bdaSLionel Sambuc 		else
9627eb99bdaSLionel Sambuc 			prefetch = "non";
9637eb99bdaSLionel Sambuc 		printf("%s %sprefetchable memory\n", type, prefetch);
9647eb99bdaSLionel Sambuc 		switch (PCI_MAPREG_MEM_TYPE(rval)) {
9657eb99bdaSLionel Sambuc 		case PCI_MAPREG_MEM_TYPE_64BIT:
9667eb99bdaSLionel Sambuc 			printf("      base: 0x%016llx, ",
9677eb99bdaSLionel Sambuc 			    PCI_MAPREG_MEM64_ADDR(
9687eb99bdaSLionel Sambuc 				((((long long) rval64h) << 32) | rval)));
9697eb99bdaSLionel Sambuc #ifdef _KERNEL
9707eb99bdaSLionel Sambuc 			if (sizebar)
9717eb99bdaSLionel Sambuc 				printf("size: 0x%016llx",
9727eb99bdaSLionel Sambuc 				    PCI_MAPREG_MEM64_SIZE(
9737eb99bdaSLionel Sambuc 				      ((((long long) mask64h) << 32) | mask)));
9747eb99bdaSLionel Sambuc 			else
9757eb99bdaSLionel Sambuc #endif /* _KERNEL */
9767eb99bdaSLionel Sambuc 				printf("not sized");
9777eb99bdaSLionel Sambuc 			printf("\n");
9787eb99bdaSLionel Sambuc 			break;
9797eb99bdaSLionel Sambuc 		case PCI_MAPREG_MEM_TYPE_32BIT:
9807eb99bdaSLionel Sambuc 		case PCI_MAPREG_MEM_TYPE_32BIT_1M:
9817eb99bdaSLionel Sambuc 		default:
9827eb99bdaSLionel Sambuc 			printf("      base: 0x%08x, ",
9837eb99bdaSLionel Sambuc 			    PCI_MAPREG_MEM_ADDR(rval));
9847eb99bdaSLionel Sambuc #ifdef _KERNEL
9857eb99bdaSLionel Sambuc 			if (sizebar)
9867eb99bdaSLionel Sambuc 				printf("size: 0x%08x",
9877eb99bdaSLionel Sambuc 				    PCI_MAPREG_MEM_SIZE(mask));
9887eb99bdaSLionel Sambuc 			else
9897eb99bdaSLionel Sambuc #endif /* _KERNEL */
9907eb99bdaSLionel Sambuc 				printf("not sized");
9917eb99bdaSLionel Sambuc 			printf("\n");
9927eb99bdaSLionel Sambuc 			break;
9937eb99bdaSLionel Sambuc 		}
9947eb99bdaSLionel Sambuc 	} else {
9957eb99bdaSLionel Sambuc #ifdef _KERNEL
9967eb99bdaSLionel Sambuc 		if (sizebar)
9977eb99bdaSLionel Sambuc 			printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16);
9987eb99bdaSLionel Sambuc #endif /* _KERNEL */
9997eb99bdaSLionel Sambuc 		printf("i/o\n");
10007eb99bdaSLionel Sambuc 		printf("      base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval));
10017eb99bdaSLionel Sambuc #ifdef _KERNEL
10027eb99bdaSLionel Sambuc 		if (sizebar)
10037eb99bdaSLionel Sambuc 			printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask));
10047eb99bdaSLionel Sambuc 		else
10057eb99bdaSLionel Sambuc #endif /* _KERNEL */
10067eb99bdaSLionel Sambuc 			printf("not sized");
10077eb99bdaSLionel Sambuc 		printf("\n");
10087eb99bdaSLionel Sambuc 	}
10097eb99bdaSLionel Sambuc 
10107eb99bdaSLionel Sambuc 	return width;
10117eb99bdaSLionel Sambuc }
10127eb99bdaSLionel Sambuc 
10137eb99bdaSLionel Sambuc static void
pci_conf_print_regs(const pcireg_t * regs,int first,int pastlast)10147eb99bdaSLionel Sambuc pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast)
10157eb99bdaSLionel Sambuc {
10167eb99bdaSLionel Sambuc 	int off, needaddr, neednl;
10177eb99bdaSLionel Sambuc 
10187eb99bdaSLionel Sambuc 	needaddr = 1;
10197eb99bdaSLionel Sambuc 	neednl = 0;
10207eb99bdaSLionel Sambuc 	for (off = first; off < pastlast; off += 4) {
10217eb99bdaSLionel Sambuc 		if ((off % 16) == 0 || needaddr) {
10227eb99bdaSLionel Sambuc 			printf("    0x%02x:", off);
10237eb99bdaSLionel Sambuc 			needaddr = 0;
10247eb99bdaSLionel Sambuc 		}
10257eb99bdaSLionel Sambuc 		printf(" 0x%08x", regs[o2i(off)]);
10267eb99bdaSLionel Sambuc 		neednl = 1;
10277eb99bdaSLionel Sambuc 		if ((off % 16) == 12) {
10287eb99bdaSLionel Sambuc 			printf("\n");
10297eb99bdaSLionel Sambuc 			neednl = 0;
10307eb99bdaSLionel Sambuc 		}
10317eb99bdaSLionel Sambuc 	}
10327eb99bdaSLionel Sambuc 	if (neednl)
10337eb99bdaSLionel Sambuc 		printf("\n");
10347eb99bdaSLionel Sambuc }
10357eb99bdaSLionel Sambuc 
10367eb99bdaSLionel Sambuc static void
pci_conf_print_agp_cap(const pcireg_t * regs,int capoff)10370a6a1f1dSLionel Sambuc pci_conf_print_agp_cap(const pcireg_t *regs, int capoff)
10387eb99bdaSLionel Sambuc {
10397eb99bdaSLionel Sambuc 	pcireg_t rval;
10407eb99bdaSLionel Sambuc 
10410a6a1f1dSLionel Sambuc 	printf("\n  AGP Capabilities Register\n");
10420a6a1f1dSLionel Sambuc 
10430a6a1f1dSLionel Sambuc 	rval = regs[o2i(capoff)];
10440a6a1f1dSLionel Sambuc 	printf("    Revision: %d.%d\n",
10450a6a1f1dSLionel Sambuc 	    PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval));
10460a6a1f1dSLionel Sambuc 
10470a6a1f1dSLionel Sambuc 	/* XXX need more */
10487eb99bdaSLionel Sambuc }
10497eb99bdaSLionel Sambuc 
10500a6a1f1dSLionel Sambuc static const char *
pci_conf_print_pcipm_cap_aux(uint16_t caps)10510a6a1f1dSLionel Sambuc pci_conf_print_pcipm_cap_aux(uint16_t caps)
10520a6a1f1dSLionel Sambuc {
10537eb99bdaSLionel Sambuc 
10540a6a1f1dSLionel Sambuc 	switch ((caps >> 6) & 7) {
10550a6a1f1dSLionel Sambuc 	case 0:	return "self-powered";
10560a6a1f1dSLionel Sambuc 	case 1: return "55 mA";
10570a6a1f1dSLionel Sambuc 	case 2: return "100 mA";
10580a6a1f1dSLionel Sambuc 	case 3: return "160 mA";
10590a6a1f1dSLionel Sambuc 	case 4: return "220 mA";
10600a6a1f1dSLionel Sambuc 	case 5: return "270 mA";
10610a6a1f1dSLionel Sambuc 	case 6: return "320 mA";
10620a6a1f1dSLionel Sambuc 	case 7:
10630a6a1f1dSLionel Sambuc 	default: return "375 mA";
10647eb99bdaSLionel Sambuc 	}
10657eb99bdaSLionel Sambuc }
10667eb99bdaSLionel Sambuc 
10670a6a1f1dSLionel Sambuc static const char *
pci_conf_print_pcipm_cap_pmrev(uint8_t val)10680a6a1f1dSLionel Sambuc pci_conf_print_pcipm_cap_pmrev(uint8_t val)
10690a6a1f1dSLionel Sambuc {
10700a6a1f1dSLionel Sambuc 	static const char unk[] = "unknown";
10710a6a1f1dSLionel Sambuc 	static const char *pmrev[8] = {
10720a6a1f1dSLionel Sambuc 		unk, "1.0", "1.1", "1.2", unk, unk, unk, unk
10730a6a1f1dSLionel Sambuc 	};
10740a6a1f1dSLionel Sambuc 	if (val > 7)
10750a6a1f1dSLionel Sambuc 		return unk;
10760a6a1f1dSLionel Sambuc 	return pmrev[val];
10770a6a1f1dSLionel Sambuc }
10780a6a1f1dSLionel Sambuc 
10790a6a1f1dSLionel Sambuc static void
pci_conf_print_pcipm_cap(const pcireg_t * regs,int capoff)10800a6a1f1dSLionel Sambuc pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff)
10810a6a1f1dSLionel Sambuc {
10820a6a1f1dSLionel Sambuc 	uint16_t caps, pmcsr;
10830a6a1f1dSLionel Sambuc 	pcireg_t reg;
10840a6a1f1dSLionel Sambuc 
10850a6a1f1dSLionel Sambuc 	caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT;
10860a6a1f1dSLionel Sambuc 	reg = regs[o2i(capoff + PCI_PMCSR)];
10870a6a1f1dSLionel Sambuc 	pmcsr = reg & 0xffff;
10880a6a1f1dSLionel Sambuc 
10890a6a1f1dSLionel Sambuc 	printf("\n  PCI Power Management Capabilities Register\n");
10900a6a1f1dSLionel Sambuc 
10910a6a1f1dSLionel Sambuc 	printf("    Capabilities register: 0x%04x\n", caps);
10920a6a1f1dSLionel Sambuc 	printf("      Version: %s\n",
10930a6a1f1dSLionel Sambuc 	    pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK));
10940a6a1f1dSLionel Sambuc 	onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK);
10950a6a1f1dSLionel Sambuc 	onoff("Device specific initialization", caps, PCI_PMCR_DSI);
10960a6a1f1dSLionel Sambuc 	printf("      3.3V auxiliary current: %s\n",
10970a6a1f1dSLionel Sambuc 	    pci_conf_print_pcipm_cap_aux(caps));
10980a6a1f1dSLionel Sambuc 	onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP);
10990a6a1f1dSLionel Sambuc 	onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP);
11000a6a1f1dSLionel Sambuc 	onoff("PME# support D0", caps, PCI_PMCR_PME_D0);
11010a6a1f1dSLionel Sambuc 	onoff("PME# support D1", caps, PCI_PMCR_PME_D1);
11020a6a1f1dSLionel Sambuc 	onoff("PME# support D2", caps, PCI_PMCR_PME_D2);
11030a6a1f1dSLionel Sambuc 	onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT);
11040a6a1f1dSLionel Sambuc 	onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD);
11050a6a1f1dSLionel Sambuc 
11060a6a1f1dSLionel Sambuc 	printf("    Control/status register: 0x%04x\n", pmcsr);
11070a6a1f1dSLionel Sambuc 	printf("      Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK);
11080a6a1f1dSLionel Sambuc 	onoff("PCI Express reserved", (pmcsr >> 2), 1);
11090a6a1f1dSLionel Sambuc 	onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST);
11100a6a1f1dSLionel Sambuc 	printf("      PME# assertion: %sabled\n",
11110a6a1f1dSLionel Sambuc 	    (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis");
11120a6a1f1dSLionel Sambuc 	onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS);
11130a6a1f1dSLionel Sambuc 	printf("    Bridge Support Extensions register: 0x%02x\n",
11140a6a1f1dSLionel Sambuc 	    (reg >> 16) & 0xff);
11150a6a1f1dSLionel Sambuc 	onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT);
11160a6a1f1dSLionel Sambuc 	onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN);
11170a6a1f1dSLionel Sambuc 	printf("    Data register: 0x%02x\n", (reg >> 24) & 0xff);
11180a6a1f1dSLionel Sambuc 
11190a6a1f1dSLionel Sambuc }
11200a6a1f1dSLionel Sambuc 
11210a6a1f1dSLionel Sambuc /* XXX pci_conf_print_vpd_cap */
11220a6a1f1dSLionel Sambuc /* XXX pci_conf_print_slotid_cap */
11230a6a1f1dSLionel Sambuc 
11240a6a1f1dSLionel Sambuc static void
pci_conf_print_msi_cap(const pcireg_t * regs,int capoff)11250a6a1f1dSLionel Sambuc pci_conf_print_msi_cap(const pcireg_t *regs, int capoff)
11260a6a1f1dSLionel Sambuc {
11270a6a1f1dSLionel Sambuc 	uint32_t ctl, mmc, mme;
11280a6a1f1dSLionel Sambuc 
11290a6a1f1dSLionel Sambuc 	regs += o2i(capoff);
11300a6a1f1dSLionel Sambuc 	ctl = *regs++;
11310a6a1f1dSLionel Sambuc 	mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK);
11320a6a1f1dSLionel Sambuc 	mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK);
11330a6a1f1dSLionel Sambuc 
11340a6a1f1dSLionel Sambuc 	printf("\n  PCI Message Signaled Interrupt\n");
11350a6a1f1dSLionel Sambuc 
11360a6a1f1dSLionel Sambuc 	printf("    Message Control register: 0x%04x\n", ctl >> 16);
11370a6a1f1dSLionel Sambuc 	onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE);
11380a6a1f1dSLionel Sambuc 	printf("      Multiple Message Capable: %s (%d vector%s)\n",
11390a6a1f1dSLionel Sambuc 	    mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : "");
11400a6a1f1dSLionel Sambuc 	printf("      Multiple Message Enabled: %s (%d vector%s)\n",
11410a6a1f1dSLionel Sambuc 	    mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : "");
11420a6a1f1dSLionel Sambuc 	onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR);
11430a6a1f1dSLionel Sambuc 	onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK);
11440a6a1f1dSLionel Sambuc 	printf("    Message Address %sregister: 0x%08x\n",
11450a6a1f1dSLionel Sambuc 	    ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++);
11460a6a1f1dSLionel Sambuc 	if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
11470a6a1f1dSLionel Sambuc 		printf("    Message Address %sregister: 0x%08x\n",
11480a6a1f1dSLionel Sambuc 		    "(upper) ", *regs++);
11490a6a1f1dSLionel Sambuc 	}
11500a6a1f1dSLionel Sambuc 	printf("    Message Data register: 0x%08x\n", *regs++);
11510a6a1f1dSLionel Sambuc 	if (ctl & PCI_MSI_CTL_PERVEC_MASK) {
11520a6a1f1dSLionel Sambuc 		printf("    Vector Mask register: 0x%08x\n", *regs++);
11530a6a1f1dSLionel Sambuc 		printf("    Vector Pending register: 0x%08x\n", *regs++);
11540a6a1f1dSLionel Sambuc 	}
11550a6a1f1dSLionel Sambuc }
11560a6a1f1dSLionel Sambuc 
11570a6a1f1dSLionel Sambuc /* XXX pci_conf_print_cpci_hostwap_cap */
11580a6a1f1dSLionel Sambuc 
11590a6a1f1dSLionel Sambuc /*
11600a6a1f1dSLionel Sambuc  * For both command register and status register.
11610a6a1f1dSLionel Sambuc  * The argument "idx" is index number (0 to 7).
11620a6a1f1dSLionel Sambuc  */
11630a6a1f1dSLionel Sambuc static int
pcix_split_trans(unsigned int idx)11640a6a1f1dSLionel Sambuc pcix_split_trans(unsigned int idx)
11650a6a1f1dSLionel Sambuc {
11660a6a1f1dSLionel Sambuc 	static int table[8] = {
11670a6a1f1dSLionel Sambuc 		1, 2, 3, 4, 8, 12, 16, 32
11680a6a1f1dSLionel Sambuc 	};
11690a6a1f1dSLionel Sambuc 
11700a6a1f1dSLionel Sambuc 	if (idx >= __arraycount(table))
11710a6a1f1dSLionel Sambuc 		return -1;
11720a6a1f1dSLionel Sambuc 	return table[idx];
11730a6a1f1dSLionel Sambuc }
11740a6a1f1dSLionel Sambuc 
11750a6a1f1dSLionel Sambuc static void
pci_conf_print_pcix_cap(const pcireg_t * regs,int capoff)11760a6a1f1dSLionel Sambuc pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff)
11770a6a1f1dSLionel Sambuc {
11780a6a1f1dSLionel Sambuc 	pcireg_t reg;
11790a6a1f1dSLionel Sambuc 	int isbridge;
11800a6a1f1dSLionel Sambuc 	int i;
11810a6a1f1dSLionel Sambuc 
11820a6a1f1dSLionel Sambuc 	isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])
11830a6a1f1dSLionel Sambuc 	    & PCI_HDRTYPE_PPB) != 0 ? 1 : 0;
11840a6a1f1dSLionel Sambuc 	printf("\n  PCI-X %s Capabilities Register\n",
11850a6a1f1dSLionel Sambuc 	    isbridge ? "Bridge" : "Non-bridge");
11860a6a1f1dSLionel Sambuc 
11870a6a1f1dSLionel Sambuc 	reg = regs[o2i(capoff)];
11880a6a1f1dSLionel Sambuc 	if (isbridge != 0) {
11890a6a1f1dSLionel Sambuc 		printf("    Secondary status register: 0x%04x\n",
11900a6a1f1dSLionel Sambuc 		    (reg & 0xffff0000) >> 16);
11910a6a1f1dSLionel Sambuc 		onoff("64bit device", reg, PCIX_STATUS_64BIT);
11920a6a1f1dSLionel Sambuc 		onoff("133MHz capable", reg, PCIX_STATUS_133);
11930a6a1f1dSLionel Sambuc 		onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC);
11940a6a1f1dSLionel Sambuc 		onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX);
11950a6a1f1dSLionel Sambuc 		onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN);
11960a6a1f1dSLionel Sambuc 		onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL);
11970a6a1f1dSLionel Sambuc 		printf("      Secondary clock frequency: 0x%x\n",
11980a6a1f1dSLionel Sambuc 		    (reg & PCIX_BRIDGE_2NDST_CLKF)
11990a6a1f1dSLionel Sambuc 		    >> PCIX_BRIDGE_2NDST_CLKF_SHIFT);
12000a6a1f1dSLionel Sambuc 		printf("      Version: 0x%x\n",
12010a6a1f1dSLionel Sambuc 		    (reg & PCIX_BRIDGE_2NDST_VER_MASK)
12020a6a1f1dSLionel Sambuc 		    >> PCIX_BRIDGE_2NDST_VER_SHIFT);
12030a6a1f1dSLionel Sambuc 		onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266);
12040a6a1f1dSLionel Sambuc 		onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533);
12050a6a1f1dSLionel Sambuc 	} else {
12060a6a1f1dSLionel Sambuc 		printf("    Command register: 0x%04x\n",
12070a6a1f1dSLionel Sambuc 		    (reg & 0xffff0000) >> 16);
12080a6a1f1dSLionel Sambuc 		onoff("Data Parity Error Recovery", reg,
12090a6a1f1dSLionel Sambuc 		    PCIX_CMD_PERR_RECOVER);
12100a6a1f1dSLionel Sambuc 		onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER);
12110a6a1f1dSLionel Sambuc 		printf("      Maximum Burst Read Count: %u\n",
12120a6a1f1dSLionel Sambuc 		    PCIX_CMD_BYTECNT(reg));
12130a6a1f1dSLionel Sambuc 		printf("      Maximum Split Transactions: %d\n",
12140a6a1f1dSLionel Sambuc 		    pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK)
12150a6a1f1dSLionel Sambuc 			>> PCIX_CMD_SPLTRANS_SHIFT));
12160a6a1f1dSLionel Sambuc 	}
12170a6a1f1dSLionel Sambuc 	reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */
12180a6a1f1dSLionel Sambuc 	printf("    %sStatus register: 0x%08x\n",
12190a6a1f1dSLionel Sambuc 	    isbridge ? "Bridge " : "", reg);
12200a6a1f1dSLionel Sambuc 	printf("      Function: %d\n", PCIX_STATUS_FN(reg));
12210a6a1f1dSLionel Sambuc 	printf("      Device: %d\n", PCIX_STATUS_DEV(reg));
12220a6a1f1dSLionel Sambuc 	printf("      Bus: %d\n", PCIX_STATUS_BUS(reg));
12230a6a1f1dSLionel Sambuc 	onoff("64bit device", reg, PCIX_STATUS_64BIT);
12240a6a1f1dSLionel Sambuc 	onoff("133MHz capable", reg, PCIX_STATUS_133);
12250a6a1f1dSLionel Sambuc 	onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC);
12260a6a1f1dSLionel Sambuc 	onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX);
12270a6a1f1dSLionel Sambuc 	if (isbridge != 0) {
12280a6a1f1dSLionel Sambuc 		onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN);
12290a6a1f1dSLionel Sambuc 		onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL);
12300a6a1f1dSLionel Sambuc 	} else {
12310a6a1f1dSLionel Sambuc 		onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX,
12320a6a1f1dSLionel Sambuc 		    "bridge device", "simple device");
12330a6a1f1dSLionel Sambuc 		printf("      Designed max memory read byte count: %d\n",
12340a6a1f1dSLionel Sambuc 		    512 << ((reg & PCIX_STATUS_MAXB_MASK)
12350a6a1f1dSLionel Sambuc 			>> PCIX_STATUS_MAXB_SHIFT));
12360a6a1f1dSLionel Sambuc 		printf("      Designed max outstanding split transaction: %d\n",
12370a6a1f1dSLionel Sambuc 		    pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK)
12380a6a1f1dSLionel Sambuc 			>> PCIX_STATUS_MAXST_SHIFT));
12390a6a1f1dSLionel Sambuc 		printf("      MAX cumulative Read Size: %u\n",
12400a6a1f1dSLionel Sambuc 		    8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT));
12410a6a1f1dSLionel Sambuc 		onoff("Received split completion error", reg,
12420a6a1f1dSLionel Sambuc 		    PCIX_STATUS_SCERR);
12430a6a1f1dSLionel Sambuc 	}
12440a6a1f1dSLionel Sambuc 	onoff("266MHz capable", reg, PCIX_STATUS_266);
12450a6a1f1dSLionel Sambuc 	onoff("533MHz capable", reg, PCIX_STATUS_533);
12460a6a1f1dSLionel Sambuc 
12470a6a1f1dSLionel Sambuc 	if (isbridge == 0)
12480a6a1f1dSLionel Sambuc 		return;
12490a6a1f1dSLionel Sambuc 
12500a6a1f1dSLionel Sambuc 	/* Only for bridge */
12510a6a1f1dSLionel Sambuc 	for (i = 0; i < 2; i++) {
12520a6a1f1dSLionel Sambuc 		reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))];
12530a6a1f1dSLionel Sambuc 		printf("    %s split transaction control register: 0x%08x\n",
12540a6a1f1dSLionel Sambuc 		    (i == 0) ? "Upstream" : "Downstream", reg);
12550a6a1f1dSLionel Sambuc 		printf("      Capacity: %d\n", reg & PCIX_BRIDGE_STCAP);
12560a6a1f1dSLionel Sambuc 		printf("      Commitment Limit: %d\n",
12570a6a1f1dSLionel Sambuc 		    (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT);
12580a6a1f1dSLionel Sambuc 	}
12590a6a1f1dSLionel Sambuc }
12600a6a1f1dSLionel Sambuc 
12610a6a1f1dSLionel Sambuc /* XXX pci_conf_print_ldt_cap */
12620a6a1f1dSLionel Sambuc 
12630a6a1f1dSLionel Sambuc static void
pci_conf_print_vendspec_cap(const pcireg_t * regs,int capoff)12640a6a1f1dSLionel Sambuc pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff)
12650a6a1f1dSLionel Sambuc {
12660a6a1f1dSLionel Sambuc 	uint16_t caps;
12670a6a1f1dSLionel Sambuc 
12680a6a1f1dSLionel Sambuc 	caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT;
12690a6a1f1dSLionel Sambuc 
12700a6a1f1dSLionel Sambuc 	printf("\n  PCI Vendor Specific Capabilities Register\n");
12710a6a1f1dSLionel Sambuc 	printf("    Capabilities length: 0x%02x\n", caps & 0xff);
12720a6a1f1dSLionel Sambuc }
12730a6a1f1dSLionel Sambuc 
12740a6a1f1dSLionel Sambuc static void
pci_conf_print_debugport_cap(const pcireg_t * regs,int capoff)12750a6a1f1dSLionel Sambuc pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff)
12760a6a1f1dSLionel Sambuc {
12770a6a1f1dSLionel Sambuc 	pcireg_t val;
12780a6a1f1dSLionel Sambuc 
12790a6a1f1dSLionel Sambuc 	val = regs[o2i(capoff + PCI_DEBUG_BASER)];
12800a6a1f1dSLionel Sambuc 
12810a6a1f1dSLionel Sambuc 	printf("\n  Debugport Capability Register\n");
12820a6a1f1dSLionel Sambuc 	printf("    Debug base Register: 0x%04x\n",
12830a6a1f1dSLionel Sambuc 	    val >> PCI_DEBUG_BASER_SHIFT);
12840a6a1f1dSLionel Sambuc 	printf("      port offset: 0x%04x\n",
12850a6a1f1dSLionel Sambuc 	    (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT);
12860a6a1f1dSLionel Sambuc 	printf("      BAR number: %u\n",
12870a6a1f1dSLionel Sambuc 	    (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT);
12880a6a1f1dSLionel Sambuc }
12890a6a1f1dSLionel Sambuc 
12900a6a1f1dSLionel Sambuc /* XXX pci_conf_print_cpci_rsrcctl_cap */
12910a6a1f1dSLionel Sambuc /* XXX pci_conf_print_hotplug_cap */
12920a6a1f1dSLionel Sambuc 
12930a6a1f1dSLionel Sambuc static void
pci_conf_print_subsystem_cap(const pcireg_t * regs,int capoff)12940a6a1f1dSLionel Sambuc pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff)
12950a6a1f1dSLionel Sambuc {
12960a6a1f1dSLionel Sambuc 	pcireg_t reg;
12970a6a1f1dSLionel Sambuc 
12980a6a1f1dSLionel Sambuc 	reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)];
12990a6a1f1dSLionel Sambuc 
13000a6a1f1dSLionel Sambuc 	printf("\n  Subsystem ID Capability Register\n");
13010a6a1f1dSLionel Sambuc 	printf("    Subsystem ID : 0x%08x\n", reg);
13020a6a1f1dSLionel Sambuc }
13030a6a1f1dSLionel Sambuc 
13040a6a1f1dSLionel Sambuc /* XXX pci_conf_print_agp8_cap */
13050a6a1f1dSLionel Sambuc /* XXX pci_conf_print_secure_cap */
13060a6a1f1dSLionel Sambuc 
13077eb99bdaSLionel Sambuc static void
pci_print_pcie_L0s_latency(uint32_t val)13087eb99bdaSLionel Sambuc pci_print_pcie_L0s_latency(uint32_t val)
13097eb99bdaSLionel Sambuc {
13107eb99bdaSLionel Sambuc 
13117eb99bdaSLionel Sambuc 	switch (val) {
13127eb99bdaSLionel Sambuc 	case 0x0:
13137eb99bdaSLionel Sambuc 		printf("Less than 64ns\n");
13147eb99bdaSLionel Sambuc 		break;
13157eb99bdaSLionel Sambuc 	case 0x1:
13167eb99bdaSLionel Sambuc 	case 0x2:
13177eb99bdaSLionel Sambuc 	case 0x3:
13187eb99bdaSLionel Sambuc 		printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1));
13197eb99bdaSLionel Sambuc 		break;
13207eb99bdaSLionel Sambuc 	case 0x4:
13217eb99bdaSLionel Sambuc 		printf("512ns to less than 1us\n");
13227eb99bdaSLionel Sambuc 		break;
13237eb99bdaSLionel Sambuc 	case 0x5:
13247eb99bdaSLionel Sambuc 		printf("1us to less than 2us\n");
13257eb99bdaSLionel Sambuc 		break;
13267eb99bdaSLionel Sambuc 	case 0x6:
13277eb99bdaSLionel Sambuc 		printf("2us - 4us\n");
13287eb99bdaSLionel Sambuc 		break;
13297eb99bdaSLionel Sambuc 	case 0x7:
13307eb99bdaSLionel Sambuc 		printf("More than 4us\n");
13317eb99bdaSLionel Sambuc 		break;
13327eb99bdaSLionel Sambuc 	}
13337eb99bdaSLionel Sambuc }
13347eb99bdaSLionel Sambuc 
13357eb99bdaSLionel Sambuc static void
pci_print_pcie_L1_latency(uint32_t val)13367eb99bdaSLionel Sambuc pci_print_pcie_L1_latency(uint32_t val)
13377eb99bdaSLionel Sambuc {
13387eb99bdaSLionel Sambuc 
13397eb99bdaSLionel Sambuc 	switch (val) {
13407eb99bdaSLionel Sambuc 	case 0x0:
13417eb99bdaSLionel Sambuc 		printf("Less than 1us\n");
13427eb99bdaSLionel Sambuc 		break;
13437eb99bdaSLionel Sambuc 	case 0x6:
13447eb99bdaSLionel Sambuc 		printf("32us - 64us\n");
13457eb99bdaSLionel Sambuc 		break;
13467eb99bdaSLionel Sambuc 	case 0x7:
13477eb99bdaSLionel Sambuc 		printf("More than 64us\n");
13487eb99bdaSLionel Sambuc 		break;
13497eb99bdaSLionel Sambuc 	default:
13507eb99bdaSLionel Sambuc 		printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val);
13517eb99bdaSLionel Sambuc 		break;
13527eb99bdaSLionel Sambuc 	}
13537eb99bdaSLionel Sambuc }
13547eb99bdaSLionel Sambuc 
13557eb99bdaSLionel Sambuc static void
pci_print_pcie_compl_timeout(uint32_t val)13567eb99bdaSLionel Sambuc pci_print_pcie_compl_timeout(uint32_t val)
13577eb99bdaSLionel Sambuc {
13587eb99bdaSLionel Sambuc 
13597eb99bdaSLionel Sambuc 	switch (val) {
13607eb99bdaSLionel Sambuc 	case 0x0:
13617eb99bdaSLionel Sambuc 		printf("50us to 50ms\n");
13627eb99bdaSLionel Sambuc 		break;
13637eb99bdaSLionel Sambuc 	case 0x5:
13647eb99bdaSLionel Sambuc 		printf("16ms to 55ms\n");
13657eb99bdaSLionel Sambuc 		break;
13667eb99bdaSLionel Sambuc 	case 0x6:
13677eb99bdaSLionel Sambuc 		printf("65ms to 210ms\n");
13687eb99bdaSLionel Sambuc 		break;
13697eb99bdaSLionel Sambuc 	case 0x9:
13707eb99bdaSLionel Sambuc 		printf("260ms to 900ms\n");
13717eb99bdaSLionel Sambuc 		break;
13727eb99bdaSLionel Sambuc 	case 0xa:
13737eb99bdaSLionel Sambuc 		printf("1s to 3.5s\n");
13747eb99bdaSLionel Sambuc 		break;
13757eb99bdaSLionel Sambuc 	default:
13767eb99bdaSLionel Sambuc 		printf("unknown %u value\n", val);
13777eb99bdaSLionel Sambuc 		break;
13787eb99bdaSLionel Sambuc 	}
13797eb99bdaSLionel Sambuc }
13807eb99bdaSLionel Sambuc 
13817eb99bdaSLionel Sambuc static void
pci_conf_print_pcie_cap(const pcireg_t * regs,int capoff)13827eb99bdaSLionel Sambuc pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
13837eb99bdaSLionel Sambuc {
13847eb99bdaSLionel Sambuc 	pcireg_t reg; /* for each register */
13857eb99bdaSLionel Sambuc 	pcireg_t val; /* for each bitfield */
13867eb99bdaSLionel Sambuc 	bool check_link = false;
13877eb99bdaSLionel Sambuc 	bool check_slot = false;
13887eb99bdaSLionel Sambuc 	bool check_rootport = false;
13897eb99bdaSLionel Sambuc 	unsigned int pciever;
13907eb99bdaSLionel Sambuc 	static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"};
13917eb99bdaSLionel Sambuc 	int i;
13927eb99bdaSLionel Sambuc 
13937eb99bdaSLionel Sambuc 	printf("\n  PCI Express Capabilities Register\n");
13947eb99bdaSLionel Sambuc 	/* Capability Register */
13957eb99bdaSLionel Sambuc 	reg = regs[o2i(capoff)];
13967eb99bdaSLionel Sambuc 	printf("    Capability register: %04x\n", reg >> 16);
13977eb99bdaSLionel Sambuc 	pciever = (unsigned int)((reg & 0x000f0000) >> 16);
13987eb99bdaSLionel Sambuc 	printf("      Capability version: %u\n", pciever);
13997eb99bdaSLionel Sambuc 	printf("      Device type: ");
14007eb99bdaSLionel Sambuc 	switch ((reg & 0x00f00000) >> 20) {
14017eb99bdaSLionel Sambuc 	case 0x0:
14027eb99bdaSLionel Sambuc 		printf("PCI Express Endpoint device\n");
14037eb99bdaSLionel Sambuc 		check_link = true;
14047eb99bdaSLionel Sambuc 		break;
14057eb99bdaSLionel Sambuc 	case 0x1:
14067eb99bdaSLionel Sambuc 		printf("Legacy PCI Express Endpoint device\n");
14077eb99bdaSLionel Sambuc 		check_link = true;
14087eb99bdaSLionel Sambuc 		break;
14097eb99bdaSLionel Sambuc 	case 0x4:
14107eb99bdaSLionel Sambuc 		printf("Root Port of PCI Express Root Complex\n");
14117eb99bdaSLionel Sambuc 		check_link = true;
14127eb99bdaSLionel Sambuc 		check_slot = true;
14137eb99bdaSLionel Sambuc 		check_rootport = true;
14147eb99bdaSLionel Sambuc 		break;
14157eb99bdaSLionel Sambuc 	case 0x5:
14167eb99bdaSLionel Sambuc 		printf("Upstream Port of PCI Express Switch\n");
14177eb99bdaSLionel Sambuc 		break;
14187eb99bdaSLionel Sambuc 	case 0x6:
14197eb99bdaSLionel Sambuc 		printf("Downstream Port of PCI Express Switch\n");
14207eb99bdaSLionel Sambuc 		check_slot = true;
14217eb99bdaSLionel Sambuc 		check_rootport = true;
14227eb99bdaSLionel Sambuc 		break;
14237eb99bdaSLionel Sambuc 	case 0x7:
14247eb99bdaSLionel Sambuc 		printf("PCI Express to PCI/PCI-X Bridge\n");
14257eb99bdaSLionel Sambuc 		break;
14267eb99bdaSLionel Sambuc 	case 0x8:
14277eb99bdaSLionel Sambuc 		printf("PCI/PCI-X to PCI Express Bridge\n");
14287eb99bdaSLionel Sambuc 		break;
14297eb99bdaSLionel Sambuc 	case 0x9:
14307eb99bdaSLionel Sambuc 		printf("Root Complex Integrated Endpoint\n");
14317eb99bdaSLionel Sambuc 		break;
14327eb99bdaSLionel Sambuc 	case 0xa:
14337eb99bdaSLionel Sambuc 		check_rootport = true;
14347eb99bdaSLionel Sambuc 		printf("Root Complex Event Collector\n");
14357eb99bdaSLionel Sambuc 		break;
14367eb99bdaSLionel Sambuc 	default:
14377eb99bdaSLionel Sambuc 		printf("unknown\n");
14387eb99bdaSLionel Sambuc 		break;
14397eb99bdaSLionel Sambuc 	}
14400a6a1f1dSLionel Sambuc 	onoff("Slot implemented", reg, PCIE_XCAP_SI);
14417eb99bdaSLionel Sambuc 	printf("      Interrupt Message Number: %x\n",
14427eb99bdaSLionel Sambuc 	    (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27));
14437eb99bdaSLionel Sambuc 
14447eb99bdaSLionel Sambuc 	/* Device Capability Register */
14457eb99bdaSLionel Sambuc 	reg = regs[o2i(capoff + PCIE_DCAP)];
14467eb99bdaSLionel Sambuc 	printf("    Device Capabilities Register: 0x%08x\n", reg);
14477eb99bdaSLionel Sambuc 	printf("      Max Payload Size Supported: %u bytes max\n",
14480a6a1f1dSLionel Sambuc 	    128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD));
14497eb99bdaSLionel Sambuc 	printf("      Phantom Functions Supported: ");
14507eb99bdaSLionel Sambuc 	switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) {
14517eb99bdaSLionel Sambuc 	case 0x0:
14527eb99bdaSLionel Sambuc 		printf("not available\n");
14537eb99bdaSLionel Sambuc 		break;
14547eb99bdaSLionel Sambuc 	case 0x1:
14557eb99bdaSLionel Sambuc 		printf("MSB\n");
14567eb99bdaSLionel Sambuc 		break;
14577eb99bdaSLionel Sambuc 	case 0x2:
14587eb99bdaSLionel Sambuc 		printf("two MSB\n");
14597eb99bdaSLionel Sambuc 		break;
14607eb99bdaSLionel Sambuc 	case 0x3:
14617eb99bdaSLionel Sambuc 		printf("All three bits\n");
14627eb99bdaSLionel Sambuc 		break;
14637eb99bdaSLionel Sambuc 	}
14647eb99bdaSLionel Sambuc 	printf("      Extended Tag Field Supported: %dbit\n",
14657eb99bdaSLionel Sambuc 	    (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8);
14667eb99bdaSLionel Sambuc 	printf("      Endpoint L0 Acceptable Latency: ");
14677eb99bdaSLionel Sambuc 	pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6);
14687eb99bdaSLionel Sambuc 	printf("      Endpoint L1 Acceptable Latency: ");
14697eb99bdaSLionel Sambuc 	pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9);
14700a6a1f1dSLionel Sambuc 	onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON);
14710a6a1f1dSLionel Sambuc 	onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND);
14720a6a1f1dSLionel Sambuc 	onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND);
14730a6a1f1dSLionel Sambuc 	onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT);
14747eb99bdaSLionel Sambuc 	printf("      Captured Slot Power Limit Value: %d\n",
14757eb99bdaSLionel Sambuc 	    (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18);
14767eb99bdaSLionel Sambuc 	printf("      Captured Slot Power Limit Scale: %d\n",
14777eb99bdaSLionel Sambuc 	    (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26);
14780a6a1f1dSLionel Sambuc 	onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR);
14797eb99bdaSLionel Sambuc 
14807eb99bdaSLionel Sambuc 	/* Device Control Register */
14817eb99bdaSLionel Sambuc 	reg = regs[o2i(capoff + PCIE_DCSR)];
14827eb99bdaSLionel Sambuc 	printf("    Device Control Register: 0x%04x\n", reg & 0xffff);
14830a6a1f1dSLionel Sambuc 	onoff("Correctable Error Reporting Enable", reg,
14840a6a1f1dSLionel Sambuc 	    PCIE_DCSR_ENA_COR_ERR);
14850a6a1f1dSLionel Sambuc 	onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER);
14860a6a1f1dSLionel Sambuc 	onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER);
14870a6a1f1dSLionel Sambuc 	onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR);
14880a6a1f1dSLionel Sambuc 	onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD);
14897eb99bdaSLionel Sambuc 	printf("      Max Payload Size: %d byte\n",
14907eb99bdaSLionel Sambuc 	    128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5)));
14910a6a1f1dSLionel Sambuc 	onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD);
14920a6a1f1dSLionel Sambuc 	onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS);
14930a6a1f1dSLionel Sambuc 	onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM);
14940a6a1f1dSLionel Sambuc 	onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP);
14957eb99bdaSLionel Sambuc 	printf("      Max Read Request Size: %d byte\n",
14967eb99bdaSLionel Sambuc 	    128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12));
14977eb99bdaSLionel Sambuc 
14987eb99bdaSLionel Sambuc 	/* Device Status Register */
14997eb99bdaSLionel Sambuc 	reg = regs[o2i(capoff + PCIE_DCSR)];
15007eb99bdaSLionel Sambuc 	printf("    Device Status Register: 0x%04x\n", reg >> 16);
15010a6a1f1dSLionel Sambuc 	onoff("Correctable Error Detected", reg, PCIE_DCSR_CED);
15020a6a1f1dSLionel Sambuc 	onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED);
15030a6a1f1dSLionel Sambuc 	onoff("Fatal Error Detected", reg, PCIE_DCSR_FED);
15040a6a1f1dSLionel Sambuc 	onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD);
15050a6a1f1dSLionel Sambuc 	onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR);
15060a6a1f1dSLionel Sambuc 	onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND);
15077eb99bdaSLionel Sambuc 
15087eb99bdaSLionel Sambuc 	if (check_link) {
15097eb99bdaSLionel Sambuc 		/* Link Capability Register */
15107eb99bdaSLionel Sambuc 		reg = regs[o2i(capoff + PCIE_LCAP)];
15117eb99bdaSLionel Sambuc 		printf("    Link Capabilities Register: 0x%08x\n", reg);
15127eb99bdaSLionel Sambuc 		printf("      Maximum Link Speed: ");
15137eb99bdaSLionel Sambuc 		val = reg & PCIE_LCAP_MAX_SPEED;
15147eb99bdaSLionel Sambuc 		if (val < 1 || val > 3) {
15157eb99bdaSLionel Sambuc 			printf("unknown %u value\n", val);
15167eb99bdaSLionel Sambuc 		} else {
15177eb99bdaSLionel Sambuc 			printf("%sGT/s\n", linkspeeds[val - 1]);
15187eb99bdaSLionel Sambuc 		}
15197eb99bdaSLionel Sambuc 		printf("      Maximum Link Width: x%u lanes\n",
15207eb99bdaSLionel Sambuc 		    (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4);
15217eb99bdaSLionel Sambuc 		printf("      Active State PM Support: ");
15227eb99bdaSLionel Sambuc 		val = (reg & PCIE_LCAP_ASPM) >> 10;
15237eb99bdaSLionel Sambuc 		switch (val) {
15247eb99bdaSLionel Sambuc 		case 0x1:
15257eb99bdaSLionel Sambuc 			printf("L0s Entry supported\n");
15267eb99bdaSLionel Sambuc 			break;
15277eb99bdaSLionel Sambuc 		case 0x3:
15287eb99bdaSLionel Sambuc 			printf("L0s and L1 supported\n");
15297eb99bdaSLionel Sambuc 			break;
15307eb99bdaSLionel Sambuc 		default:
15317eb99bdaSLionel Sambuc 			printf("Reserved value\n");
15327eb99bdaSLionel Sambuc 			break;
15337eb99bdaSLionel Sambuc 		}
15347eb99bdaSLionel Sambuc 		printf("      L0 Exit Latency: ");
15357eb99bdaSLionel Sambuc 		pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12);
15367eb99bdaSLionel Sambuc 		printf("      L1 Exit Latency: ");
15377eb99bdaSLionel Sambuc 		pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15);
15387eb99bdaSLionel Sambuc 		printf("      Port Number: %u\n", reg >> 24);
15390a6a1f1dSLionel Sambuc 		onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM);
15400a6a1f1dSLionel Sambuc 		onoff("Surprise Down Error Report", reg,
15410a6a1f1dSLionel Sambuc 		    PCIE_LCAP_SURPRISE_DOWN);
15420a6a1f1dSLionel Sambuc 		onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE);
15430a6a1f1dSLionel Sambuc 		onoff("Link BW Notification Capable", reg,
15440a6a1f1dSLionel Sambuc 			PCIE_LCAP_LINK_BW_NOTIFY);
15450a6a1f1dSLionel Sambuc 		onoff("ASPM Optionally Compliance", reg,
15460a6a1f1dSLionel Sambuc 		    PCIE_LCAP_ASPM_COMPLIANCE);
15477eb99bdaSLionel Sambuc 
15487eb99bdaSLionel Sambuc 		/* Link Control Register */
15497eb99bdaSLionel Sambuc 		reg = regs[o2i(capoff + PCIE_LCSR)];
15507eb99bdaSLionel Sambuc 		printf("    Link Control Register: 0x%04x\n", reg & 0xffff);
15517eb99bdaSLionel Sambuc 		printf("      Active State PM Control: ");
15527eb99bdaSLionel Sambuc 		val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S);
15537eb99bdaSLionel Sambuc 		switch (val) {
15547eb99bdaSLionel Sambuc 		case 0:
15557eb99bdaSLionel Sambuc 			printf("disabled\n");
15567eb99bdaSLionel Sambuc 			break;
15577eb99bdaSLionel Sambuc 		case 1:
15587eb99bdaSLionel Sambuc 			printf("L0s Entry Enabled\n");
15597eb99bdaSLionel Sambuc 			break;
15607eb99bdaSLionel Sambuc 		case 2:
15617eb99bdaSLionel Sambuc 			printf("L1 Entry Enabled\n");
15627eb99bdaSLionel Sambuc 			break;
15637eb99bdaSLionel Sambuc 		case 3:
15647eb99bdaSLionel Sambuc 			printf("L0s and L1 Entry Enabled\n");
15657eb99bdaSLionel Sambuc 			break;
15667eb99bdaSLionel Sambuc 		}
15670a6a1f1dSLionel Sambuc 		onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB,
15680a6a1f1dSLionel Sambuc 		    "128bytes", "64bytes");
15690a6a1f1dSLionel Sambuc 		onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS);
15700a6a1f1dSLionel Sambuc 		onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN);
15710a6a1f1dSLionel Sambuc 		onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG);
15720a6a1f1dSLionel Sambuc 		onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC);
15730a6a1f1dSLionel Sambuc 		onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM);
15740a6a1f1dSLionel Sambuc 		onoff("Hardware Autonomous Width Disable", reg,
15750a6a1f1dSLionel Sambuc 		    PCIE_LCSR_HAWD);
15760a6a1f1dSLionel Sambuc 		onoff("Link Bandwidth Management Interrupt Enable", reg,
15770a6a1f1dSLionel Sambuc 		    PCIE_LCSR_LBMIE);
15780a6a1f1dSLionel Sambuc 		onoff("Link Autonomous Bandwidth Interrupt Enable", reg,
15790a6a1f1dSLionel Sambuc 		    PCIE_LCSR_LABIE);
15807eb99bdaSLionel Sambuc 
15817eb99bdaSLionel Sambuc 		/* Link Status Register */
15827eb99bdaSLionel Sambuc 		reg = regs[o2i(capoff + PCIE_LCSR)];
15837eb99bdaSLionel Sambuc 		printf("    Link Status Register: 0x%04x\n", reg >> 16);
15847eb99bdaSLionel Sambuc 		printf("      Negotiated Link Speed: ");
15857eb99bdaSLionel Sambuc 		if (((reg >> 16) & 0x000f) < 1 ||
15867eb99bdaSLionel Sambuc 		    ((reg >> 16) & 0x000f) > 3) {
15877eb99bdaSLionel Sambuc 			printf("unknown %u value\n",
15887eb99bdaSLionel Sambuc 			    (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16);
15897eb99bdaSLionel Sambuc 		} else {
15907eb99bdaSLionel Sambuc 			printf("%sGT/s\n",
15917eb99bdaSLionel Sambuc 			    linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16)-1]);
15927eb99bdaSLionel Sambuc 		}
15937eb99bdaSLionel Sambuc 		printf("      Negotiated Link Width: x%u lanes\n",
15947eb99bdaSLionel Sambuc 		    (reg >> 20) & 0x003f);
15950a6a1f1dSLionel Sambuc 		onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR);
15960a6a1f1dSLionel Sambuc 		onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN);
15970a6a1f1dSLionel Sambuc 		onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG);
15980a6a1f1dSLionel Sambuc 		onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE);
15990a6a1f1dSLionel Sambuc 		onoff("Link Bandwidth Management Status", reg,
16000a6a1f1dSLionel Sambuc 		    PCIE_LCSR_LINK_BW_MGMT);
16010a6a1f1dSLionel Sambuc 		onoff("Link Autonomous Bandwidth Status", reg,
16020a6a1f1dSLionel Sambuc 		    PCIE_LCSR_LINK_AUTO_BW);
16037eb99bdaSLionel Sambuc 	}
16047eb99bdaSLionel Sambuc 
16057eb99bdaSLionel Sambuc 	if (check_slot == true) {
16067eb99bdaSLionel Sambuc 		/* Slot Capability Register */
16077eb99bdaSLionel Sambuc 		reg = regs[o2i(capoff + PCIE_SLCAP)];
16087eb99bdaSLionel Sambuc 		printf("    Slot Capability Register: %08x\n", reg);
16090a6a1f1dSLionel Sambuc 		onoff("Attention Button Present", reg, PCIE_SLCAP_ABP);
16100a6a1f1dSLionel Sambuc 		onoff("Power Controller Present", reg, PCIE_SLCAP_PCP);
16110a6a1f1dSLionel Sambuc 		onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP);
16120a6a1f1dSLionel Sambuc 		onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP);
16130a6a1f1dSLionel Sambuc 		onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP);
16140a6a1f1dSLionel Sambuc 		onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS);
16150a6a1f1dSLionel Sambuc 		onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC);
16167eb99bdaSLionel Sambuc 		printf("      Slot Power Limit Value: %d\n",
16177eb99bdaSLionel Sambuc 		    (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7);
16187eb99bdaSLionel Sambuc 		printf("      Slot Power Limit Scale: %d\n",
16197eb99bdaSLionel Sambuc 		    (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15);
16200a6a1f1dSLionel Sambuc 		onoff("Electromechanical Interlock Present", reg,
16210a6a1f1dSLionel Sambuc 		    PCIE_SLCAP_EIP);
16220a6a1f1dSLionel Sambuc 		onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS);
16237eb99bdaSLionel Sambuc 		printf("      Physical Slot Number: %d\n",
16247eb99bdaSLionel Sambuc 		    (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19);
16257eb99bdaSLionel Sambuc 
16267eb99bdaSLionel Sambuc 		/* Slot Control Register */
16277eb99bdaSLionel Sambuc 		reg = regs[o2i(capoff + PCIE_SLCSR)];
16287eb99bdaSLionel Sambuc 		printf("    Slot Control Register: %04x\n", reg & 0xffff);
16290a6a1f1dSLionel Sambuc 		onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE);
16300a6a1f1dSLionel Sambuc 		onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE);
16310a6a1f1dSLionel Sambuc 		onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE);
16320a6a1f1dSLionel Sambuc 		onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE);
16330a6a1f1dSLionel Sambuc 		onoff("Command Completed Interrupt Enabled", reg,
16340a6a1f1dSLionel Sambuc 		    PCIE_SLCSR_CCE);
16350a6a1f1dSLionel Sambuc 		onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE);
16367eb99bdaSLionel Sambuc 		printf("      Attention Indicator Control: ");
16377eb99bdaSLionel Sambuc 		switch ((reg & PCIE_SLCSR_AIC) >> 6) {
16387eb99bdaSLionel Sambuc 		case 0x0:
16397eb99bdaSLionel Sambuc 			printf("reserved\n");
16407eb99bdaSLionel Sambuc 			break;
16417eb99bdaSLionel Sambuc 		case 0x1:
16427eb99bdaSLionel Sambuc 			printf("on\n");
16437eb99bdaSLionel Sambuc 			break;
16447eb99bdaSLionel Sambuc 		case 0x2:
16457eb99bdaSLionel Sambuc 			printf("blink\n");
16467eb99bdaSLionel Sambuc 			break;
16477eb99bdaSLionel Sambuc 		case 0x3:
16487eb99bdaSLionel Sambuc 			printf("off\n");
16497eb99bdaSLionel Sambuc 			break;
16507eb99bdaSLionel Sambuc 		}
16517eb99bdaSLionel Sambuc 		printf("      Power Indicator Control: ");
16527eb99bdaSLionel Sambuc 		switch ((reg & PCIE_SLCSR_PIC) >> 8) {
16537eb99bdaSLionel Sambuc 		case 0x0:
16547eb99bdaSLionel Sambuc 			printf("reserved\n");
16557eb99bdaSLionel Sambuc 			break;
16567eb99bdaSLionel Sambuc 		case 0x1:
16577eb99bdaSLionel Sambuc 			printf("on\n");
16587eb99bdaSLionel Sambuc 			break;
16597eb99bdaSLionel Sambuc 		case 0x2:
16607eb99bdaSLionel Sambuc 			printf("blink\n");
16617eb99bdaSLionel Sambuc 			break;
16627eb99bdaSLionel Sambuc 		case 0x3:
16637eb99bdaSLionel Sambuc 			printf("off\n");
16647eb99bdaSLionel Sambuc 			break;
16657eb99bdaSLionel Sambuc 		}
16660a6a1f1dSLionel Sambuc 		onoff("Power Controller Control", reg, PCIE_SLCSR_PCC);
16670a6a1f1dSLionel Sambuc 		onoff("Electromechanical Interlock Control",
16680a6a1f1dSLionel Sambuc 		    reg, PCIE_SLCSR_EIC);
16690a6a1f1dSLionel Sambuc 		onoff("Data Link Layer State Changed Enable", reg,
16700a6a1f1dSLionel Sambuc 		    PCIE_SLCSR_DLLSCE);
16717eb99bdaSLionel Sambuc 
16727eb99bdaSLionel Sambuc 		/* Slot Status Register */
16737eb99bdaSLionel Sambuc 		printf("    Slot Status Register: %04x\n", reg >> 16);
16740a6a1f1dSLionel Sambuc 		onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP);
16750a6a1f1dSLionel Sambuc 		onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD);
16760a6a1f1dSLionel Sambuc 		onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC);
16770a6a1f1dSLionel Sambuc 		onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC);
16780a6a1f1dSLionel Sambuc 		onoff("Command Completed", reg, PCIE_SLCSR_CC);
16790a6a1f1dSLionel Sambuc 		onoff("MRL Open", reg, PCIE_SLCSR_MS);
16800a6a1f1dSLionel Sambuc 		onoff("Card Present in slot", reg, PCIE_SLCSR_PDS);
16810a6a1f1dSLionel Sambuc 		onoff("Electromechanical Interlock engaged", reg,
16820a6a1f1dSLionel Sambuc 		    PCIE_SLCSR_EIS);
16830a6a1f1dSLionel Sambuc 		onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS);
16847eb99bdaSLionel Sambuc 	}
16857eb99bdaSLionel Sambuc 
16867eb99bdaSLionel Sambuc 	if (check_rootport == true) {
16877eb99bdaSLionel Sambuc 		/* Root Control Register */
16887eb99bdaSLionel Sambuc 		reg = regs[o2i(capoff + PCIE_RCR)];
16897eb99bdaSLionel Sambuc 		printf("    Root Control Register: %04x\n", reg & 0xffff);
16900a6a1f1dSLionel Sambuc 		onoff("SERR on Correctable Error Enable", reg,
16910a6a1f1dSLionel Sambuc 		    PCIE_RCR_SERR_CER);
16920a6a1f1dSLionel Sambuc 		onoff("SERR on Non-Fatal Error Enable", reg,
16930a6a1f1dSLionel Sambuc 		    PCIE_RCR_SERR_NFER);
16940a6a1f1dSLionel Sambuc 		onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER);
16950a6a1f1dSLionel Sambuc 		onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE);
16960a6a1f1dSLionel Sambuc 		onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE);
16977eb99bdaSLionel Sambuc 
16987eb99bdaSLionel Sambuc 		/* Root Capability Register */
16997eb99bdaSLionel Sambuc 		printf("    Root Capability Register: %04x\n",
17007eb99bdaSLionel Sambuc 		    reg >> 16);
17010a6a1f1dSLionel Sambuc 		onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV);
17027eb99bdaSLionel Sambuc 
17037eb99bdaSLionel Sambuc 		/* Root Status Register */
17047eb99bdaSLionel Sambuc 		reg = regs[o2i(capoff + PCIE_RSR)];
17057eb99bdaSLionel Sambuc 		printf("    Root Status Register: %08x\n", reg);
17067eb99bdaSLionel Sambuc 		printf("      PME Requester ID: %04x\n",
17077eb99bdaSLionel Sambuc 		    (unsigned int)(reg & PCIE_RSR_PME_REQESTER));
17080a6a1f1dSLionel Sambuc 		onoff("PME was asserted", reg, PCIE_RSR_PME_STAT);
17090a6a1f1dSLionel Sambuc 		onoff("another PME is pending", reg, PCIE_RSR_PME_PEND);
17107eb99bdaSLionel Sambuc 	}
17117eb99bdaSLionel Sambuc 
17127eb99bdaSLionel Sambuc 	/* PCIe DW9 to DW14 is for PCIe 2.0 and newer */
17137eb99bdaSLionel Sambuc 	if (pciever < 2)
17147eb99bdaSLionel Sambuc 		return;
17157eb99bdaSLionel Sambuc 
17167eb99bdaSLionel Sambuc 	/* Device Capabilities 2 */
17177eb99bdaSLionel Sambuc 	reg = regs[o2i(capoff + PCIE_DCAP2)];
17187eb99bdaSLionel Sambuc 	printf("    Device Capabilities 2: 0x%08x\n", reg);
17197eb99bdaSLionel Sambuc 	printf("      Completion Timeout Ranges Supported: %u \n",
17207eb99bdaSLionel Sambuc 	    (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE));
17210a6a1f1dSLionel Sambuc 	onoff("Completion Timeout Disable Supported", reg,
17220a6a1f1dSLionel Sambuc 	    PCIE_DCAP2_COMPT_DIS);
17230a6a1f1dSLionel Sambuc 	onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD);
17240a6a1f1dSLionel Sambuc 	onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT);
17250a6a1f1dSLionel Sambuc 	onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM);
17260a6a1f1dSLionel Sambuc 	onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM);
17270a6a1f1dSLionel Sambuc 	onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS);
17280a6a1f1dSLionel Sambuc 	onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS);
17290a6a1f1dSLionel Sambuc 	onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC);
17307eb99bdaSLionel Sambuc 	printf("      TPH Completer Supported: %u\n",
17317eb99bdaSLionel Sambuc 	    (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12);
17327eb99bdaSLionel Sambuc 	printf("      OBFF Supported: ");
17337eb99bdaSLionel Sambuc 	switch ((reg & PCIE_DCAP2_OBFF) >> 18) {
17347eb99bdaSLionel Sambuc 	case 0x0:
17357eb99bdaSLionel Sambuc 		printf("Not supported\n");
17367eb99bdaSLionel Sambuc 		break;
17377eb99bdaSLionel Sambuc 	case 0x1:
17387eb99bdaSLionel Sambuc 		printf("Message only\n");
17397eb99bdaSLionel Sambuc 		break;
17407eb99bdaSLionel Sambuc 	case 0x2:
17417eb99bdaSLionel Sambuc 		printf("WAKE# only\n");
17427eb99bdaSLionel Sambuc 		break;
17437eb99bdaSLionel Sambuc 	case 0x3:
17447eb99bdaSLionel Sambuc 		printf("Both\n");
17457eb99bdaSLionel Sambuc 		break;
17467eb99bdaSLionel Sambuc 	}
17470a6a1f1dSLionel Sambuc 	onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD);
17480a6a1f1dSLionel Sambuc 	onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF);
17497eb99bdaSLionel Sambuc 	printf("      Max End-End TLP Prefixes: %u\n",
17507eb99bdaSLionel Sambuc 	    (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22);
17517eb99bdaSLionel Sambuc 
17527eb99bdaSLionel Sambuc 	/* Device Control 2 */
17537eb99bdaSLionel Sambuc 	reg = regs[o2i(capoff + PCIE_DCSR2)];
17547eb99bdaSLionel Sambuc 	printf("    Device Control 2: 0x%04x\n", reg & 0xffff);
17557eb99bdaSLionel Sambuc 	printf("      Completion Timeout Value: ");
17567eb99bdaSLionel Sambuc 	pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL);
17570a6a1f1dSLionel Sambuc 	onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS);
17580a6a1f1dSLionel Sambuc 	onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD);
17590a6a1f1dSLionel Sambuc 	onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ);
17600a6a1f1dSLionel Sambuc 	onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK);
17610a6a1f1dSLionel Sambuc 	onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ);
17620a6a1f1dSLionel Sambuc 	onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP);
17630a6a1f1dSLionel Sambuc 	onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC);
17647eb99bdaSLionel Sambuc 	printf("      OBFF: ");
17657eb99bdaSLionel Sambuc 	switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) {
17667eb99bdaSLionel Sambuc 	case 0x0:
17677eb99bdaSLionel Sambuc 		printf("Disabled\n");
17687eb99bdaSLionel Sambuc 		break;
17697eb99bdaSLionel Sambuc 	case 0x1:
17707eb99bdaSLionel Sambuc 		printf("Enabled with Message Signaling Variation A\n");
17717eb99bdaSLionel Sambuc 		break;
17727eb99bdaSLionel Sambuc 	case 0x2:
17737eb99bdaSLionel Sambuc 		printf("Enabled with Message Signaling Variation B\n");
17747eb99bdaSLionel Sambuc 		break;
17757eb99bdaSLionel Sambuc 	case 0x3:
17767eb99bdaSLionel Sambuc 		printf("Enabled using WAKE# signaling\n");
17777eb99bdaSLionel Sambuc 		break;
17787eb99bdaSLionel Sambuc 	}
17790a6a1f1dSLionel Sambuc 	onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP);
17807eb99bdaSLionel Sambuc 
17817eb99bdaSLionel Sambuc 	if (check_link) {
17827eb99bdaSLionel Sambuc 		/* Link Capability 2 */
17837eb99bdaSLionel Sambuc 		reg = regs[o2i(capoff + PCIE_LCAP2)];
17847eb99bdaSLionel Sambuc 		printf("    Link Capabilities 2: 0x%08x\n", reg);
17857eb99bdaSLionel Sambuc 		val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1;
17867eb99bdaSLionel Sambuc 		printf("      Supported Link Speed Vector:");
17877eb99bdaSLionel Sambuc 		for (i = 0; i <= 2; i++) {
17887eb99bdaSLionel Sambuc 			if (((val >> i) & 0x01) != 0)
17897eb99bdaSLionel Sambuc 				printf(" %sGT/s", linkspeeds[i]);
17907eb99bdaSLionel Sambuc 		}
17917eb99bdaSLionel Sambuc 		printf("\n");
17920a6a1f1dSLionel Sambuc 		onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK);
17937eb99bdaSLionel Sambuc 
17947eb99bdaSLionel Sambuc 		/* Link Control 2 */
17957eb99bdaSLionel Sambuc 		reg = regs[o2i(capoff + PCIE_LCSR2)];
17967eb99bdaSLionel Sambuc 		printf("    Link Control 2: 0x%04x\n", reg & 0xffff);
17977eb99bdaSLionel Sambuc 		printf("      Target Link Speed: ");
17987eb99bdaSLionel Sambuc 		val = reg & PCIE_LCSR2_TGT_LSPEED;
17990a6a1f1dSLionel Sambuc 		if (val < 1 || val > 3)
18007eb99bdaSLionel Sambuc 			printf("unknown %u value\n", val);
18010a6a1f1dSLionel Sambuc 		else
18027eb99bdaSLionel Sambuc 			printf("%sGT/s\n", linkspeeds[val - 1]);
18030a6a1f1dSLionel Sambuc 		onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL);
18040a6a1f1dSLionel Sambuc 		onoff("HW Autonomous Speed Disabled", reg,
18050a6a1f1dSLionel Sambuc 		    PCIE_LCSR2_HW_AS_DIS);
18060a6a1f1dSLionel Sambuc 		onoff("Selectable De-emphasis", reg, PCIE_LCSR2_SEL_DEEMP);
18077eb99bdaSLionel Sambuc 		printf("      Transmit Margin: %u\n",
18087eb99bdaSLionel Sambuc 		    (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7);
18090a6a1f1dSLionel Sambuc 		onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP);
18100a6a1f1dSLionel Sambuc 		onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS);
18117eb99bdaSLionel Sambuc 		printf("      Compliance Present/De-emphasis: %u\n",
18127eb99bdaSLionel Sambuc 		    (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12);
18137eb99bdaSLionel Sambuc 
18147eb99bdaSLionel Sambuc 		/* Link Status 2 */
18150a6a1f1dSLionel Sambuc 		printf("    Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff);
18160a6a1f1dSLionel Sambuc 		onoff("Current De-emphasis Level", reg, PCIE_LCSR2_DEEMP_LVL);
18170a6a1f1dSLionel Sambuc 		onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL);
18180a6a1f1dSLionel Sambuc 		onoff("Equalization Phase 1 Successful", reg,
18190a6a1f1dSLionel Sambuc 		    PCIE_LCSR2_EQP1_SUC);
18200a6a1f1dSLionel Sambuc 		onoff("Equalization Phase 2 Successful", reg,
18210a6a1f1dSLionel Sambuc 		    PCIE_LCSR2_EQP2_SUC);
18220a6a1f1dSLionel Sambuc 		onoff("Equalization Phase 3 Successful", reg,
18230a6a1f1dSLionel Sambuc 		    PCIE_LCSR2_EQP3_SUC);
18240a6a1f1dSLionel Sambuc 		onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ);
18257eb99bdaSLionel Sambuc 	}
18267eb99bdaSLionel Sambuc 
18277eb99bdaSLionel Sambuc 	/* Slot Capability 2 */
18287eb99bdaSLionel Sambuc 	/* Slot Control 2 */
18297eb99bdaSLionel Sambuc 	/* Slot Status 2 */
18307eb99bdaSLionel Sambuc }
18317eb99bdaSLionel Sambuc 
18320a6a1f1dSLionel Sambuc static void
pci_conf_print_msix_cap(const pcireg_t * regs,int capoff)18330a6a1f1dSLionel Sambuc pci_conf_print_msix_cap(const pcireg_t *regs, int capoff)
18347eb99bdaSLionel Sambuc {
18350a6a1f1dSLionel Sambuc 	pcireg_t reg;
18360a6a1f1dSLionel Sambuc 
18370a6a1f1dSLionel Sambuc 	printf("\n  MSI-X Capability Register\n");
18380a6a1f1dSLionel Sambuc 
18390a6a1f1dSLionel Sambuc 	reg = regs[o2i(capoff + PCI_MSIX_CTL)];
18400a6a1f1dSLionel Sambuc 	printf("    Message Control register: 0x%04x\n",
18410a6a1f1dSLionel Sambuc 	    (reg >> 16) & 0xff);
18420a6a1f1dSLionel Sambuc 	printf("      Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg));
18430a6a1f1dSLionel Sambuc 	onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK);
18440a6a1f1dSLionel Sambuc 	onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE);
18450a6a1f1dSLionel Sambuc 	reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)];
18460a6a1f1dSLionel Sambuc 	printf("    Table offset register: 0x%08x\n", reg);
18470a6a1f1dSLionel Sambuc 	printf("      Table offset: %08x\n", reg & PCI_MSIX_TBLOFFSET_MASK);
18480a6a1f1dSLionel Sambuc 	printf("      BIR: 0x%x\n", reg & PCI_MSIX_TBLBIR_MASK);
18490a6a1f1dSLionel Sambuc 	reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)];
18500a6a1f1dSLionel Sambuc 	printf("    Pending bit array register: 0x%08x\n", reg);
18510a6a1f1dSLionel Sambuc 	printf("      Pending bit array offset: %08x\n",
18520a6a1f1dSLionel Sambuc 	    reg & PCI_MSIX_PBAOFFSET_MASK);
18530a6a1f1dSLionel Sambuc 	printf("      BIR: 0x%x\n", reg & PCI_MSIX_PBABIR_MASK);
18547eb99bdaSLionel Sambuc }
18557eb99bdaSLionel Sambuc 
18560a6a1f1dSLionel Sambuc /* XXX pci_conf_print_sata_cap */
18570a6a1f1dSLionel Sambuc static void
pci_conf_print_pciaf_cap(const pcireg_t * regs,int capoff)18580a6a1f1dSLionel Sambuc pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff)
18597eb99bdaSLionel Sambuc {
18600a6a1f1dSLionel Sambuc 	pcireg_t reg;
18610a6a1f1dSLionel Sambuc 
18620a6a1f1dSLionel Sambuc 	printf("\n  Advanced Features Capability Register\n");
18630a6a1f1dSLionel Sambuc 
18640a6a1f1dSLionel Sambuc 	reg = regs[o2i(capoff + PCI_AFCAPR)];
18650a6a1f1dSLionel Sambuc 	printf("    AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff);
18660a6a1f1dSLionel Sambuc 	onoff("Transaction Pending", reg, PCI_AF_TP_CAP);
18670a6a1f1dSLionel Sambuc 	onoff("Function Level Reset", reg, PCI_AF_FLR_CAP);
18680a6a1f1dSLionel Sambuc 	reg = regs[o2i(capoff + PCI_AFCSR)];
18690a6a1f1dSLionel Sambuc 	printf("    AF Control register: 0x%02x\n", reg & 0xff);
18700a6a1f1dSLionel Sambuc 	/*
18710a6a1f1dSLionel Sambuc 	 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register
18720a6a1f1dSLionel Sambuc 	 * and it's always 0 on read
18730a6a1f1dSLionel Sambuc 	 */
18740a6a1f1dSLionel Sambuc 	printf("    AF Status register: 0x%02x\n", (reg >> 8) & 0xff);
18750a6a1f1dSLionel Sambuc 	onoff("Transaction Pending", reg, PCI_AFSR_TP);
18760a6a1f1dSLionel Sambuc }
18770a6a1f1dSLionel Sambuc 
18780a6a1f1dSLionel Sambuc static struct {
18790a6a1f1dSLionel Sambuc 	pcireg_t cap;
18800a6a1f1dSLionel Sambuc 	const char *name;
18810a6a1f1dSLionel Sambuc 	void (*printfunc)(const pcireg_t *, int);
18820a6a1f1dSLionel Sambuc } pci_captab[] = {
18830a6a1f1dSLionel Sambuc 	{ PCI_CAP_RESERVED0,	"reserved",	NULL },
18840a6a1f1dSLionel Sambuc 	{ PCI_CAP_PWRMGMT,	"Power Management", pci_conf_print_pcipm_cap },
18850a6a1f1dSLionel Sambuc 	{ PCI_CAP_AGP,		"AGP",		pci_conf_print_agp_cap },
18860a6a1f1dSLionel Sambuc 	{ PCI_CAP_VPD,		"VPD",		NULL },
18870a6a1f1dSLionel Sambuc 	{ PCI_CAP_SLOTID,	"SlotID",	NULL },
18880a6a1f1dSLionel Sambuc 	{ PCI_CAP_MSI,		"MSI",		pci_conf_print_msi_cap },
18890a6a1f1dSLionel Sambuc 	{ PCI_CAP_CPCI_HOTSWAP,	"CompactPCI Hot-swapping", NULL },
18900a6a1f1dSLionel Sambuc 	{ PCI_CAP_PCIX,		"PCI-X",	pci_conf_print_pcix_cap },
18910a6a1f1dSLionel Sambuc 	{ PCI_CAP_LDT,		"HyperTransport", NULL },
18920a6a1f1dSLionel Sambuc 	{ PCI_CAP_VENDSPEC,	"Vendor-specific",
18930a6a1f1dSLionel Sambuc 	  pci_conf_print_vendspec_cap },
18940a6a1f1dSLionel Sambuc 	{ PCI_CAP_DEBUGPORT,	"Debug Port",	pci_conf_print_debugport_cap },
18950a6a1f1dSLionel Sambuc 	{ PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL },
18960a6a1f1dSLionel Sambuc 	{ PCI_CAP_HOTPLUG,	"Hot-Plug",	NULL },
18970a6a1f1dSLionel Sambuc 	{ PCI_CAP_SUBVENDOR,	"Subsystem vendor ID",
18980a6a1f1dSLionel Sambuc 	  pci_conf_print_subsystem_cap },
18990a6a1f1dSLionel Sambuc 	{ PCI_CAP_AGP8,		"AGP 8x",	NULL },
19000a6a1f1dSLionel Sambuc 	{ PCI_CAP_SECURE,	"Secure Device", NULL },
19010a6a1f1dSLionel Sambuc 	{ PCI_CAP_PCIEXPRESS,	"PCI Express",	pci_conf_print_pcie_cap },
19020a6a1f1dSLionel Sambuc 	{ PCI_CAP_MSIX,		"MSI-X",	pci_conf_print_msix_cap },
19030a6a1f1dSLionel Sambuc 	{ PCI_CAP_SATA,		"SATA",		NULL },
19040a6a1f1dSLionel Sambuc 	{ PCI_CAP_PCIAF,	"Advanced Features", pci_conf_print_pciaf_cap }
19057eb99bdaSLionel Sambuc };
19067eb99bdaSLionel Sambuc 
19070a6a1f1dSLionel Sambuc static int
pci_conf_find_cap(const pcireg_t * regs,int capoff,unsigned int capid,int * offsetp)19080a6a1f1dSLionel Sambuc pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid,
19090a6a1f1dSLionel Sambuc     int *offsetp)
19107eb99bdaSLionel Sambuc {
19110a6a1f1dSLionel Sambuc 	pcireg_t rval;
19120a6a1f1dSLionel Sambuc 	int off;
19137eb99bdaSLionel Sambuc 
19140a6a1f1dSLionel Sambuc 	for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
19150a6a1f1dSLionel Sambuc 	     off != 0;
19160a6a1f1dSLionel Sambuc 	     off = PCI_CAPLIST_NEXT(rval)) {
19170a6a1f1dSLionel Sambuc 		rval = regs[o2i(off)];
19180a6a1f1dSLionel Sambuc 		if (capid == PCI_CAPLIST_CAP(rval)) {
19190a6a1f1dSLionel Sambuc 			if (offsetp != NULL)
19200a6a1f1dSLionel Sambuc 				*offsetp = off;
19210a6a1f1dSLionel Sambuc 			return 1;
19227eb99bdaSLionel Sambuc 		}
19237eb99bdaSLionel Sambuc 	}
19240a6a1f1dSLionel Sambuc 	return 0;
19250a6a1f1dSLionel Sambuc }
19260a6a1f1dSLionel Sambuc 
19277eb99bdaSLionel Sambuc static void
pci_conf_print_caplist(pci_chipset_tag_t pc,pcitag_t tag,const pcireg_t * regs,int capoff)19287eb99bdaSLionel Sambuc pci_conf_print_caplist(
19297eb99bdaSLionel Sambuc #ifdef _KERNEL
19307eb99bdaSLionel Sambuc     pci_chipset_tag_t pc, pcitag_t tag,
19317eb99bdaSLionel Sambuc #endif
19327eb99bdaSLionel Sambuc     const pcireg_t *regs, int capoff)
19337eb99bdaSLionel Sambuc {
19347eb99bdaSLionel Sambuc 	int off;
19350a6a1f1dSLionel Sambuc 	pcireg_t foundcap;
19367eb99bdaSLionel Sambuc 	pcireg_t rval;
19370a6a1f1dSLionel Sambuc 	bool foundtable[__arraycount(pci_captab)];
19380a6a1f1dSLionel Sambuc 	unsigned int i;
19397eb99bdaSLionel Sambuc 
19400a6a1f1dSLionel Sambuc 	/* Clear table */
19410a6a1f1dSLionel Sambuc 	for (i = 0; i < __arraycount(pci_captab); i++)
19420a6a1f1dSLionel Sambuc 		foundtable[i] = false;
19430a6a1f1dSLionel Sambuc 
19440a6a1f1dSLionel Sambuc 	/* Print capability register's offset and the type first */
19457eb99bdaSLionel Sambuc 	for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
19467eb99bdaSLionel Sambuc 	     off != 0;
19477eb99bdaSLionel Sambuc 	     off = PCI_CAPLIST_NEXT(regs[o2i(off)])) {
19487eb99bdaSLionel Sambuc 		rval = regs[o2i(off)];
19497eb99bdaSLionel Sambuc 		printf("  Capability register at 0x%02x\n", off);
19507eb99bdaSLionel Sambuc 
19517eb99bdaSLionel Sambuc 		printf("    type: 0x%02x (", PCI_CAPLIST_CAP(rval));
19520a6a1f1dSLionel Sambuc 		foundcap = PCI_CAPLIST_CAP(rval);
19530a6a1f1dSLionel Sambuc 		if (foundcap < __arraycount(pci_captab)) {
19540a6a1f1dSLionel Sambuc 			printf("%s)\n", pci_captab[foundcap].name);
19550a6a1f1dSLionel Sambuc 			/* Mark as found */
19560a6a1f1dSLionel Sambuc 			foundtable[foundcap] = true;
19570a6a1f1dSLionel Sambuc 		} else
19580a6a1f1dSLionel Sambuc 			printf("unknown)\n");
19590a6a1f1dSLionel Sambuc 	}
19600a6a1f1dSLionel Sambuc 
19610a6a1f1dSLionel Sambuc 	/*
19620a6a1f1dSLionel Sambuc 	 * And then, print the detail of each capability registers
19630a6a1f1dSLionel Sambuc 	 * in capability value's order.
19640a6a1f1dSLionel Sambuc 	 */
19650a6a1f1dSLionel Sambuc 	for (i = 0; i < __arraycount(pci_captab); i++) {
19660a6a1f1dSLionel Sambuc 		if (foundtable[i] == false)
19670a6a1f1dSLionel Sambuc 			continue;
19680a6a1f1dSLionel Sambuc 
19690a6a1f1dSLionel Sambuc 		/*
19700a6a1f1dSLionel Sambuc 		 * The type was found. Search capability list again and
19710a6a1f1dSLionel Sambuc 		 * print all capabilities that the capabiliy type is
19720a6a1f1dSLionel Sambuc 		 * the same. This is required because some capabilities
19730a6a1f1dSLionel Sambuc 		 * appear multiple times (e.g. HyperTransport capability).
19740a6a1f1dSLionel Sambuc 		 */
19750a6a1f1dSLionel Sambuc 		if (pci_conf_find_cap(regs, capoff, i, &off)) {
19760a6a1f1dSLionel Sambuc 			rval = regs[o2i(off)];
19770a6a1f1dSLionel Sambuc 			if (pci_captab[i].printfunc != NULL)
19780a6a1f1dSLionel Sambuc 				pci_captab[i].printfunc(regs, off);
19790a6a1f1dSLionel Sambuc 		}
19800a6a1f1dSLionel Sambuc 	}
19810a6a1f1dSLionel Sambuc }
19820a6a1f1dSLionel Sambuc 
19830a6a1f1dSLionel Sambuc /* Extended Capability */
19840a6a1f1dSLionel Sambuc 
19850a6a1f1dSLionel Sambuc static void
pci_conf_print_aer_cap_uc(pcireg_t reg)19860a6a1f1dSLionel Sambuc pci_conf_print_aer_cap_uc(pcireg_t reg)
19870a6a1f1dSLionel Sambuc {
19880a6a1f1dSLionel Sambuc 
19890a6a1f1dSLionel Sambuc 	onoff("Undefined", reg, PCI_AER_UC_UNDEFINED);
19900a6a1f1dSLionel Sambuc 	onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR);
19910a6a1f1dSLionel Sambuc 	onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR);
19920a6a1f1dSLionel Sambuc 	onoff("Poisoned TLP", reg, PCI_AER_UC_POISONED_TLP);
19930a6a1f1dSLionel Sambuc 	onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR);
19940a6a1f1dSLionel Sambuc 	onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT);
19950a6a1f1dSLionel Sambuc 	onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT);
19960a6a1f1dSLionel Sambuc 	onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION);
19970a6a1f1dSLionel Sambuc 	onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW);
19980a6a1f1dSLionel Sambuc 	onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP);
19990a6a1f1dSLionel Sambuc 	onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR);
20000a6a1f1dSLionel Sambuc 	onoff("Unsupported Request Error", reg,
20010a6a1f1dSLionel Sambuc 	    PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR);
20020a6a1f1dSLionel Sambuc 	onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION);
20030a6a1f1dSLionel Sambuc 	onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR);
20040a6a1f1dSLionel Sambuc 	onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP);
20050a6a1f1dSLionel Sambuc 	onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED);
20060a6a1f1dSLionel Sambuc 	onoff("TLP Prefix Blocked Error", reg,
20070a6a1f1dSLionel Sambuc 	   PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR);
20080a6a1f1dSLionel Sambuc }
20090a6a1f1dSLionel Sambuc 
20100a6a1f1dSLionel Sambuc static void
pci_conf_print_aer_cap_cor(pcireg_t reg)20110a6a1f1dSLionel Sambuc pci_conf_print_aer_cap_cor(pcireg_t reg)
20120a6a1f1dSLionel Sambuc {
20130a6a1f1dSLionel Sambuc 
20140a6a1f1dSLionel Sambuc 	onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR);
20150a6a1f1dSLionel Sambuc 	onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP);
20160a6a1f1dSLionel Sambuc 	onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP);
20170a6a1f1dSLionel Sambuc 	onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER);
20180a6a1f1dSLionel Sambuc 	onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT);
20190a6a1f1dSLionel Sambuc 	onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR);
20200a6a1f1dSLionel Sambuc 	onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR);
20210a6a1f1dSLionel Sambuc 	onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW);
20220a6a1f1dSLionel Sambuc }
20230a6a1f1dSLionel Sambuc 
20240a6a1f1dSLionel Sambuc static void
pci_conf_print_aer_cap_control(pcireg_t reg,bool * tlp_prefix_log)20250a6a1f1dSLionel Sambuc pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log)
20260a6a1f1dSLionel Sambuc {
20270a6a1f1dSLionel Sambuc 
20280a6a1f1dSLionel Sambuc 	printf("      First Error Pointer: 0x%04x\n",
20290a6a1f1dSLionel Sambuc 	    (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR));
20300a6a1f1dSLionel Sambuc 	onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE);
20310a6a1f1dSLionel Sambuc 	onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE);
20320a6a1f1dSLionel Sambuc 	onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE);
20330a6a1f1dSLionel Sambuc 	onoff("ECRC Check Enab", reg, PCI_AER_ECRC_CHECK_ENABLE);
20340a6a1f1dSLionel Sambuc 	onoff("Multiple Header Recording Capable", reg,
20350a6a1f1dSLionel Sambuc 	    PCI_AER_MULT_HDR_CAPABLE);
20360a6a1f1dSLionel Sambuc 	onoff("Multiple Header Recording Enable", reg, PCI_AER_MULT_HDR_ENABLE);
20370a6a1f1dSLionel Sambuc 
20380a6a1f1dSLionel Sambuc 	/* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */
20390a6a1f1dSLionel Sambuc 	if (!tlp_prefix_log)
20400a6a1f1dSLionel Sambuc 		return;
20410a6a1f1dSLionel Sambuc 	onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT);
20420a6a1f1dSLionel Sambuc 	*tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false;
20430a6a1f1dSLionel Sambuc }
20440a6a1f1dSLionel Sambuc 
20450a6a1f1dSLionel Sambuc static void
pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg)20460a6a1f1dSLionel Sambuc pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg)
20470a6a1f1dSLionel Sambuc {
20480a6a1f1dSLionel Sambuc 
20490a6a1f1dSLionel Sambuc 	onoff("Correctable Error Reporting Enable", reg,
20500a6a1f1dSLionel Sambuc 	    PCI_AER_ROOTERR_COR_ENABLE);
20510a6a1f1dSLionel Sambuc 	onoff("Non-Fatal Error Reporting Enable", reg,
20520a6a1f1dSLionel Sambuc 	    PCI_AER_ROOTERR_NF_ENABLE);
20530a6a1f1dSLionel Sambuc 	onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE);
20540a6a1f1dSLionel Sambuc }
20550a6a1f1dSLionel Sambuc 
20560a6a1f1dSLionel Sambuc static void
pci_conf_print_aer_cap_rooterr_status(pcireg_t reg)20570a6a1f1dSLionel Sambuc pci_conf_print_aer_cap_rooterr_status(pcireg_t reg)
20580a6a1f1dSLionel Sambuc {
20590a6a1f1dSLionel Sambuc 
20600a6a1f1dSLionel Sambuc 	onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR);
20610a6a1f1dSLionel Sambuc 	onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR);
20620a6a1f1dSLionel Sambuc 	onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR);
20630a6a1f1dSLionel Sambuc 	onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg,
20640a6a1f1dSLionel Sambuc 	    PCI_AER_ROOTERR_MULTI_UC_ERR);
20650a6a1f1dSLionel Sambuc 	onoff("First Uncorrectable Fatal", reg, PCI_AER_ROOTERR_FIRST_UC_FATAL);
20660a6a1f1dSLionel Sambuc 	onoff("Non-Fatal Error Messages Received", reg, PCI_AER_ROOTERR_NF_ERR);
20670a6a1f1dSLionel Sambuc 	onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR);
20680a6a1f1dSLionel Sambuc 	printf("      Advanced Error Interrupt Message Number: 0x%u\n",
20690a6a1f1dSLionel Sambuc 	    (pcireg_t)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE));
20700a6a1f1dSLionel Sambuc }
20710a6a1f1dSLionel Sambuc 
20720a6a1f1dSLionel Sambuc static void
pci_conf_print_aer_cap_errsrc_id(pcireg_t reg)20730a6a1f1dSLionel Sambuc pci_conf_print_aer_cap_errsrc_id(pcireg_t reg)
20740a6a1f1dSLionel Sambuc {
20750a6a1f1dSLionel Sambuc 
20760a6a1f1dSLionel Sambuc 	printf("      Correctable Source ID: 0x%04x\n",
20770a6a1f1dSLionel Sambuc 	    (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR));
20780a6a1f1dSLionel Sambuc 	printf("      ERR_FATAL/NONFATAL Source ID: 0x%04x\n",
20790a6a1f1dSLionel Sambuc 	    (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC));
20800a6a1f1dSLionel Sambuc }
20810a6a1f1dSLionel Sambuc 
20820a6a1f1dSLionel Sambuc static void
pci_conf_print_aer_cap(const pcireg_t * regs,int capoff,int extcapoff)20830a6a1f1dSLionel Sambuc pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff)
20840a6a1f1dSLionel Sambuc {
20850a6a1f1dSLionel Sambuc 	pcireg_t reg;
20860a6a1f1dSLionel Sambuc 	int pcie_capoff;
20870a6a1f1dSLionel Sambuc 	int pcie_devtype = -1;
20880a6a1f1dSLionel Sambuc 	bool tlp_prefix_log = false;
20890a6a1f1dSLionel Sambuc 
20900a6a1f1dSLionel Sambuc 	if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
20910a6a1f1dSLionel Sambuc 		reg = regs[o2i(pcie_capoff)];
20920a6a1f1dSLionel Sambuc 		pcie_devtype = reg & PCIE_XCAP_TYPE_MASK;
20930a6a1f1dSLionel Sambuc 		/* PCIe DW9 to DW14 is for PCIe 2.0 and newer */
20940a6a1f1dSLionel Sambuc 		if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) {
20950a6a1f1dSLionel Sambuc 			reg = regs[o2i(pcie_capoff + PCIE_DCAP2)];
20960a6a1f1dSLionel Sambuc 			/* End-End TLP Prefix Supported */
20970a6a1f1dSLionel Sambuc 			if (reg & PCIE_DCAP2_EETLP_PREF) {
20980a6a1f1dSLionel Sambuc 				tlp_prefix_log = true;
20990a6a1f1dSLionel Sambuc 			}
21000a6a1f1dSLionel Sambuc 		}
21010a6a1f1dSLionel Sambuc 	}
21020a6a1f1dSLionel Sambuc 
21030a6a1f1dSLionel Sambuc 	printf("\n  Advanced Error Reporting Register\n");
21040a6a1f1dSLionel Sambuc 
21050a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)];
21060a6a1f1dSLionel Sambuc 	printf("    Uncorrectable Error Status register: 0x%08x\n", reg);
21070a6a1f1dSLionel Sambuc 	pci_conf_print_aer_cap_uc(reg);
21080a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)];
21090a6a1f1dSLionel Sambuc 	printf("    Uncorrectable Error Mask register: 0x%08x\n", reg);
21100a6a1f1dSLionel Sambuc 	pci_conf_print_aer_cap_uc(reg);
21110a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)];
21120a6a1f1dSLionel Sambuc 	printf("    Uncorrectable Error Severity register: 0x%08x\n", reg);
21130a6a1f1dSLionel Sambuc 	pci_conf_print_aer_cap_uc(reg);
21140a6a1f1dSLionel Sambuc 
21150a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)];
21160a6a1f1dSLionel Sambuc 	printf("    Correctable Error Status register: 0x%08x\n", reg);
21170a6a1f1dSLionel Sambuc 	pci_conf_print_aer_cap_cor(reg);
21180a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)];
21190a6a1f1dSLionel Sambuc 	printf("    Correctable Error Mask register: 0x%08x\n", reg);
21200a6a1f1dSLionel Sambuc 	pci_conf_print_aer_cap_cor(reg);
21210a6a1f1dSLionel Sambuc 
21220a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)];
21230a6a1f1dSLionel Sambuc 	printf("    Advanced Error Capabilities and Control register: 0x%08x\n",
21240a6a1f1dSLionel Sambuc 	    reg);
21250a6a1f1dSLionel Sambuc 	pci_conf_print_aer_cap_control(reg, &tlp_prefix_log);
21260a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)];
21270a6a1f1dSLionel Sambuc 	printf("    Header Log register:\n");
21280a6a1f1dSLionel Sambuc 	pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG,
21290a6a1f1dSLionel Sambuc 	    extcapoff + PCI_AER_ROOTERR_CMD);
21300a6a1f1dSLionel Sambuc 
21310a6a1f1dSLionel Sambuc 	switch (pcie_devtype) {
21320a6a1f1dSLionel Sambuc 	case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */
21330a6a1f1dSLionel Sambuc 	case PCIE_XCAP_TYPE_ROOT_EVNTC:	/* Root Complex Event Collector */
21340a6a1f1dSLionel Sambuc 		reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)];
21350a6a1f1dSLionel Sambuc 		printf("    Root Error Command register: 0x%08x\n", reg);
21360a6a1f1dSLionel Sambuc 		pci_conf_print_aer_cap_rooterr_cmd(reg);
21370a6a1f1dSLionel Sambuc 		reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)];
21380a6a1f1dSLionel Sambuc 		printf("    Root Error Status register: 0x%08x\n", reg);
21390a6a1f1dSLionel Sambuc 		pci_conf_print_aer_cap_rooterr_status(reg);
21400a6a1f1dSLionel Sambuc 
21410a6a1f1dSLionel Sambuc 		reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)];
21420a6a1f1dSLionel Sambuc 		printf("    Error Source Identification: 0x%04x\n", reg);
21430a6a1f1dSLionel Sambuc 		pci_conf_print_aer_cap_errsrc_id(reg);
21447eb99bdaSLionel Sambuc 		break;
21450a6a1f1dSLionel Sambuc 	}
21460a6a1f1dSLionel Sambuc 
21470a6a1f1dSLionel Sambuc 	if (tlp_prefix_log) {
21480a6a1f1dSLionel Sambuc 		reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)];
21490a6a1f1dSLionel Sambuc 		printf("    TLP Prefix Log register: 0x%08x\n", reg);
21500a6a1f1dSLionel Sambuc 	}
21510a6a1f1dSLionel Sambuc }
21520a6a1f1dSLionel Sambuc 
21530a6a1f1dSLionel Sambuc static void
pci_conf_print_vc_cap_arbtab(const pcireg_t * regs,int off,const char * name,pcireg_t parbsel,int parbsize)21540a6a1f1dSLionel Sambuc pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name,
21550a6a1f1dSLionel Sambuc     pcireg_t parbsel, int parbsize)
21560a6a1f1dSLionel Sambuc {
21570a6a1f1dSLionel Sambuc 	pcireg_t reg;
21580a6a1f1dSLionel Sambuc 	int num = 16 << parbsel;
21590a6a1f1dSLionel Sambuc 	int num_per_reg = sizeof(pcireg_t) / parbsize;
21600a6a1f1dSLionel Sambuc 	int i, j;
21610a6a1f1dSLionel Sambuc 
21620a6a1f1dSLionel Sambuc 	/* First, dump the table */
21630a6a1f1dSLionel Sambuc 	for (i = 0; i < num; i += num_per_reg) {
21640a6a1f1dSLionel Sambuc 		reg = regs[o2i(off + i / num_per_reg)];
21650a6a1f1dSLionel Sambuc 		printf("    %s Arbitration Table: 0x%08x\n", name, reg);
21660a6a1f1dSLionel Sambuc 	}
21670a6a1f1dSLionel Sambuc 	/* And then, decode each entry */
21680a6a1f1dSLionel Sambuc 	for (i = 0; i < num; i += num_per_reg) {
21690a6a1f1dSLionel Sambuc 		reg = regs[o2i(off + i / num_per_reg)];
21700a6a1f1dSLionel Sambuc 		for (j = 0; j < num_per_reg; j++)
21710a6a1f1dSLionel Sambuc 			printf("      Phase[%d]: %d\n", j, reg);
21720a6a1f1dSLionel Sambuc 	}
21730a6a1f1dSLionel Sambuc }
21740a6a1f1dSLionel Sambuc 
21750a6a1f1dSLionel Sambuc static void
pci_conf_print_vc_cap(const pcireg_t * regs,int capoff,int extcapoff)21760a6a1f1dSLionel Sambuc pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff)
21770a6a1f1dSLionel Sambuc {
21780a6a1f1dSLionel Sambuc 	pcireg_t reg, n;
21790a6a1f1dSLionel Sambuc 	int parbtab, parbsize;
21800a6a1f1dSLionel Sambuc 	pcireg_t parbsel;
21810a6a1f1dSLionel Sambuc 	int varbtab, varbsize;
21820a6a1f1dSLionel Sambuc 	pcireg_t varbsel;
21830a6a1f1dSLionel Sambuc 	int i, count;
21840a6a1f1dSLionel Sambuc 
21850a6a1f1dSLionel Sambuc 	printf("\n  Virtual Channel Register\n");
21860a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_VC_CAP1)];
21870a6a1f1dSLionel Sambuc 	printf("    Port VC Capability register 1: 0x%08x\n", reg);
21880a6a1f1dSLionel Sambuc 	count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT);
21890a6a1f1dSLionel Sambuc 	printf("      Extended VC Count: %d\n", count);
21900a6a1f1dSLionel Sambuc 	n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT);
21910a6a1f1dSLionel Sambuc 	printf("      Low Priority Extended VC Count: %u\n", n);
21920a6a1f1dSLionel Sambuc 	n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK);
21930a6a1f1dSLionel Sambuc 	printf("      Reference Clock: %s\n",
21940a6a1f1dSLionel Sambuc 	    (n == PCI_VC_CAP1_REFCLK_100NS) ? "100" : "unknown");
21950a6a1f1dSLionel Sambuc 	parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE);
21960a6a1f1dSLionel Sambuc 	printf("      Port Arbitration Table Entry Size: %dbit\n", parbsize);
21970a6a1f1dSLionel Sambuc 
21980a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_VC_CAP2)];
21990a6a1f1dSLionel Sambuc 	printf("    Port VC Capability register 2: 0x%08x\n", reg);
22000a6a1f1dSLionel Sambuc 	onoff("Hardware fixed arbitration scheme",
22010a6a1f1dSLionel Sambuc 	    reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME);
22020a6a1f1dSLionel Sambuc 	onoff("WRR arbitration with 32 phases",
22030a6a1f1dSLionel Sambuc 	    reg, PCI_VC_CAP2_ARB_CAP_WRR_32);
22040a6a1f1dSLionel Sambuc 	onoff("WRR arbitration with 64 phases",
22050a6a1f1dSLionel Sambuc 	    reg, PCI_VC_CAP2_ARB_CAP_WRR_64);
22060a6a1f1dSLionel Sambuc 	onoff("WRR arbitration with 128 phases",
22070a6a1f1dSLionel Sambuc 	    reg, PCI_VC_CAP2_ARB_CAP_WRR_128);
22080a6a1f1dSLionel Sambuc 	varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET);
22090a6a1f1dSLionel Sambuc 	printf("      VC Arbitration Table Offset: 0x%x\n", varbtab);
22100a6a1f1dSLionel Sambuc 
22110a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff;
22120a6a1f1dSLionel Sambuc 	printf("    Port VC Control register: 0x%04x\n", reg);
22130a6a1f1dSLionel Sambuc 	varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT);
22140a6a1f1dSLionel Sambuc 	printf("      VC Arbitration Select: 0x%x\n", varbsel);
22150a6a1f1dSLionel Sambuc 
22160a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16;
22170a6a1f1dSLionel Sambuc 	printf("    Port VC Status register: 0x%04x\n", reg);
22180a6a1f1dSLionel Sambuc 	onoff("VC Arbitration Table Status",
22190a6a1f1dSLionel Sambuc 	    reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE);
22200a6a1f1dSLionel Sambuc 
22210a6a1f1dSLionel Sambuc 	for (i = 0; i < count + 1; i++) {
22220a6a1f1dSLionel Sambuc 		reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))];
22230a6a1f1dSLionel Sambuc 		printf("    VC number %d\n", i);
22240a6a1f1dSLionel Sambuc 		printf("      VC Resource Capability Register: 0x%08x\n", reg);
22250a6a1f1dSLionel Sambuc 		onoff("  Non-configurable Hardware fixed arbitration scheme",
22260a6a1f1dSLionel Sambuc 		    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME);
22270a6a1f1dSLionel Sambuc 		onoff("  WRR arbitration with 32 phases",
22280a6a1f1dSLionel Sambuc 		    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32);
22290a6a1f1dSLionel Sambuc 		onoff("  WRR arbitration with 64 phases",
22300a6a1f1dSLionel Sambuc 		    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64);
22310a6a1f1dSLionel Sambuc 		onoff("  WRR arbitration with 128 phases",
22320a6a1f1dSLionel Sambuc 		    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128);
22330a6a1f1dSLionel Sambuc 		onoff("  Time-based WRR arbitration with 128 phases",
22340a6a1f1dSLionel Sambuc 		    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128);
22350a6a1f1dSLionel Sambuc 		onoff("  WRR arbitration with 256 phases",
22360a6a1f1dSLionel Sambuc 		    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256);
22370a6a1f1dSLionel Sambuc 		onoff("  Advanced Packet Switching",
22380a6a1f1dSLionel Sambuc 		    reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH);
22390a6a1f1dSLionel Sambuc 		onoff("  Reject Snoop Transaction",
22400a6a1f1dSLionel Sambuc 		    reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS);
22410a6a1f1dSLionel Sambuc 		n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1;
22420a6a1f1dSLionel Sambuc 		printf("        Maximum Time Slots: %d\n", n);
22430a6a1f1dSLionel Sambuc 		parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S;
22440a6a1f1dSLionel Sambuc 		printf("        Port Arbitration Table offset: 0x%02x\n",
22450a6a1f1dSLionel Sambuc 		    parbtab);
22460a6a1f1dSLionel Sambuc 
22470a6a1f1dSLionel Sambuc 		reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))];
22480a6a1f1dSLionel Sambuc 		printf("      VC Resource Control Register: 0x%08x\n", reg);
22490a6a1f1dSLionel Sambuc 		printf("        TC/VC Map: %02x\n",
22500a6a1f1dSLionel Sambuc 		    (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP));
22510a6a1f1dSLionel Sambuc 		/*
22520a6a1f1dSLionel Sambuc 		 * The load Port Arbitration Table bit is used to update
22530a6a1f1dSLionel Sambuc 		 * the Port Arbitration logic and it's always 0 on read, so
22540a6a1f1dSLionel Sambuc 		 * we don't print it.
22550a6a1f1dSLionel Sambuc 		 */
22560a6a1f1dSLionel Sambuc 		parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT);
22570a6a1f1dSLionel Sambuc 		printf("        Port Arbitration Select: %x\n", parbsel);
22580a6a1f1dSLionel Sambuc 		n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID);
22590a6a1f1dSLionel Sambuc 		printf("        VC ID %d\n", n);
22600a6a1f1dSLionel Sambuc 		onoff("  VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE);
22610a6a1f1dSLionel Sambuc 
22620a6a1f1dSLionel Sambuc 		reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16;
22630a6a1f1dSLionel Sambuc 		printf("      VC Resource Status Register: 0x%08x\n", reg);
22640a6a1f1dSLionel Sambuc 		onoff("  Port Arbitration Table Status",
22650a6a1f1dSLionel Sambuc 		    reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE);
22660a6a1f1dSLionel Sambuc 		onoff("  VC Negotiation Pending",
22670a6a1f1dSLionel Sambuc 		    reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING);
22680a6a1f1dSLionel Sambuc 
22690a6a1f1dSLionel Sambuc 		if ((parbtab != 0) && (parbsel != 0))
22700a6a1f1dSLionel Sambuc 			pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab,
22710a6a1f1dSLionel Sambuc 			    "Port", parbsel, parbsize);
22720a6a1f1dSLionel Sambuc 	}
22730a6a1f1dSLionel Sambuc 
22740a6a1f1dSLionel Sambuc 	varbsize = 8;
22750a6a1f1dSLionel Sambuc 	if ((varbtab != 0) && (varbsel != 0))
22760a6a1f1dSLionel Sambuc 		pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab,
22770a6a1f1dSLionel Sambuc 		    "  VC", varbsel, varbsize);
22780a6a1f1dSLionel Sambuc }
22790a6a1f1dSLionel Sambuc 
22800a6a1f1dSLionel Sambuc static const char *
pci_conf_print_pwrbdgt_base_power(uint8_t reg)22810a6a1f1dSLionel Sambuc pci_conf_print_pwrbdgt_base_power(uint8_t reg)
22820a6a1f1dSLionel Sambuc {
22830a6a1f1dSLionel Sambuc 
22840a6a1f1dSLionel Sambuc 	switch (reg) {
22850a6a1f1dSLionel Sambuc 	case 0xf0:
22860a6a1f1dSLionel Sambuc 		return "250W";
22870a6a1f1dSLionel Sambuc 	case 0xf1:
22880a6a1f1dSLionel Sambuc 		return "275W";
22890a6a1f1dSLionel Sambuc 	case 0xf2:
22900a6a1f1dSLionel Sambuc 		return "300W";
22917eb99bdaSLionel Sambuc 	default:
22920a6a1f1dSLionel Sambuc 		return "Unknown";
22930a6a1f1dSLionel Sambuc 	}
22940a6a1f1dSLionel Sambuc }
22950a6a1f1dSLionel Sambuc 
22960a6a1f1dSLionel Sambuc static const char *
pci_conf_print_pwrbdgt_data_scale(uint8_t reg)22970a6a1f1dSLionel Sambuc pci_conf_print_pwrbdgt_data_scale(uint8_t reg)
22980a6a1f1dSLionel Sambuc {
22990a6a1f1dSLionel Sambuc 
23000a6a1f1dSLionel Sambuc 	switch (reg) {
23010a6a1f1dSLionel Sambuc 	case 0x00:
23020a6a1f1dSLionel Sambuc 		return "1.0x";
23030a6a1f1dSLionel Sambuc 	case 0x01:
23040a6a1f1dSLionel Sambuc 		return "0.1x";
23050a6a1f1dSLionel Sambuc 	case 0x02:
23060a6a1f1dSLionel Sambuc 		return "0.01x";
23070a6a1f1dSLionel Sambuc 	case 0x03:
23080a6a1f1dSLionel Sambuc 		return "0.001x";
23090a6a1f1dSLionel Sambuc 	default:
23100a6a1f1dSLionel Sambuc 		return "wrong value!";
23110a6a1f1dSLionel Sambuc 	}
23120a6a1f1dSLionel Sambuc }
23130a6a1f1dSLionel Sambuc 
23140a6a1f1dSLionel Sambuc static const char *
pci_conf_print_pwrbdgt_type(uint8_t reg)23150a6a1f1dSLionel Sambuc pci_conf_print_pwrbdgt_type(uint8_t reg)
23160a6a1f1dSLionel Sambuc {
23170a6a1f1dSLionel Sambuc 
23180a6a1f1dSLionel Sambuc 	switch (reg) {
23190a6a1f1dSLionel Sambuc 	case 0x00:
23200a6a1f1dSLionel Sambuc 		return "PME Aux";
23210a6a1f1dSLionel Sambuc 	case 0x01:
23220a6a1f1dSLionel Sambuc 		return "Auxilary";
23230a6a1f1dSLionel Sambuc 	case 0x02:
23240a6a1f1dSLionel Sambuc 		return "Idle";
23250a6a1f1dSLionel Sambuc 	case 0x03:
23260a6a1f1dSLionel Sambuc 		return "Sustained";
23270a6a1f1dSLionel Sambuc 	case 0x07:
23280a6a1f1dSLionel Sambuc 		return "Maximun";
23290a6a1f1dSLionel Sambuc 	default:
23300a6a1f1dSLionel Sambuc 		return "Unknown";
23310a6a1f1dSLionel Sambuc 	}
23320a6a1f1dSLionel Sambuc }
23330a6a1f1dSLionel Sambuc 
23340a6a1f1dSLionel Sambuc static const char *
pci_conf_print_pwrbdgt_pwrrail(uint8_t reg)23350a6a1f1dSLionel Sambuc pci_conf_print_pwrbdgt_pwrrail(uint8_t reg)
23360a6a1f1dSLionel Sambuc {
23370a6a1f1dSLionel Sambuc 
23380a6a1f1dSLionel Sambuc 	switch (reg) {
23390a6a1f1dSLionel Sambuc 	case 0x00:
23400a6a1f1dSLionel Sambuc 		return "Power(12V)";
23410a6a1f1dSLionel Sambuc 	case 0x01:
23420a6a1f1dSLionel Sambuc 		return "Power(3.3V)";
23430a6a1f1dSLionel Sambuc 	case 0x02:
23440a6a1f1dSLionel Sambuc 		return "Power(1.5V or 1.8V)";
23450a6a1f1dSLionel Sambuc 	case 0x07:
23460a6a1f1dSLionel Sambuc 		return "Thermal";
23470a6a1f1dSLionel Sambuc 	default:
23480a6a1f1dSLionel Sambuc 		return "Unknown";
23490a6a1f1dSLionel Sambuc 	}
23500a6a1f1dSLionel Sambuc }
23510a6a1f1dSLionel Sambuc 
23520a6a1f1dSLionel Sambuc static void
pci_conf_print_pwrbdgt_cap(const pcireg_t * regs,int capoff,int extcapoff)23530a6a1f1dSLionel Sambuc pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff)
23540a6a1f1dSLionel Sambuc {
23550a6a1f1dSLionel Sambuc 	pcireg_t reg;
23560a6a1f1dSLionel Sambuc 
23570a6a1f1dSLionel Sambuc 	printf("\n  Power Budget Register\n");
23580a6a1f1dSLionel Sambuc 
23590a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)];
23600a6a1f1dSLionel Sambuc 	printf("    Data Select register: 0x%08x\n", reg);
23610a6a1f1dSLionel Sambuc 
23620a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)];
23630a6a1f1dSLionel Sambuc 	printf("    Data register: 0x%08x\n", reg);
23640a6a1f1dSLionel Sambuc 	printf("      Base Power: %s\n",
23650a6a1f1dSLionel Sambuc 	    pci_conf_print_pwrbdgt_base_power((uint8_t)reg));
23660a6a1f1dSLionel Sambuc 	printf("      Data Scale: %s\n",
23670a6a1f1dSLionel Sambuc 	    pci_conf_print_pwrbdgt_data_scale(
23680a6a1f1dSLionel Sambuc 		    (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE))));
23690a6a1f1dSLionel Sambuc 	printf("      PM Sub State: 0x%hhx\n",
23700a6a1f1dSLionel Sambuc 	    (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT));
23710a6a1f1dSLionel Sambuc 	printf("      PM State: D%u\n",
23720a6a1f1dSLionel Sambuc 	    (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT));
23730a6a1f1dSLionel Sambuc 	printf("      Type: %s\n",
23740a6a1f1dSLionel Sambuc 	    pci_conf_print_pwrbdgt_type(
23750a6a1f1dSLionel Sambuc 		    (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE))));
23760a6a1f1dSLionel Sambuc 	printf("      Power Rail: %s\n",
23770a6a1f1dSLionel Sambuc 	    pci_conf_print_pwrbdgt_pwrrail(
23780a6a1f1dSLionel Sambuc 		    (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL))));
23790a6a1f1dSLionel Sambuc 
23800a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)];
23810a6a1f1dSLionel Sambuc 	printf("    Power Budget Capability register: 0x%08x\n", reg);
23820a6a1f1dSLionel Sambuc 	onoff("System Allocated",
23830a6a1f1dSLionel Sambuc 	    reg, PCI_PWRBDGT_CAP_SYSALLOC);
23840a6a1f1dSLionel Sambuc }
23850a6a1f1dSLionel Sambuc 
23860a6a1f1dSLionel Sambuc static const char *
pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type)23870a6a1f1dSLionel Sambuc pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type)
23880a6a1f1dSLionel Sambuc {
23890a6a1f1dSLionel Sambuc 
23900a6a1f1dSLionel Sambuc 	switch (type) {
23910a6a1f1dSLionel Sambuc 	case 0x00:
23920a6a1f1dSLionel Sambuc 		return "Configuration Space Element";
23930a6a1f1dSLionel Sambuc 	case 0x01:
23940a6a1f1dSLionel Sambuc 		return "System Egress Port or internal sink (memory)";
23950a6a1f1dSLionel Sambuc 	case 0x02:
23960a6a1f1dSLionel Sambuc 		return "Internal Root Complex Link";
23970a6a1f1dSLionel Sambuc 	default:
23980a6a1f1dSLionel Sambuc 		return "Unknown";
23990a6a1f1dSLionel Sambuc 	}
24000a6a1f1dSLionel Sambuc }
24010a6a1f1dSLionel Sambuc 
24020a6a1f1dSLionel Sambuc static void
pci_conf_print_rclink_dcl_cap(const pcireg_t * regs,int capoff,int extcapoff)24030a6a1f1dSLionel Sambuc pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff)
24040a6a1f1dSLionel Sambuc {
24050a6a1f1dSLionel Sambuc 	pcireg_t reg;
24060a6a1f1dSLionel Sambuc 	unsigned char nent, linktype;
24070a6a1f1dSLionel Sambuc 	int i;
24080a6a1f1dSLionel Sambuc 
24090a6a1f1dSLionel Sambuc 	printf("\n  Root Complex Link Declaration\n");
24100a6a1f1dSLionel Sambuc 
24110a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)];
24120a6a1f1dSLionel Sambuc 	printf("    Element Self Description Register: 0x%08x\n", reg);
24130a6a1f1dSLionel Sambuc 	printf("      Element Type: %s\n",
24140a6a1f1dSLionel Sambuc 	    pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg));
24150a6a1f1dSLionel Sambuc 	nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT);
24160a6a1f1dSLionel Sambuc 	printf("      Number of Link Entries: %hhu\n", nent);
24170a6a1f1dSLionel Sambuc 	printf("      Component ID: %hhu\n",
24180a6a1f1dSLionel Sambuc 	    (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID));
24190a6a1f1dSLionel Sambuc 	printf("      Port Number: %hhu\n",
24200a6a1f1dSLionel Sambuc 	    (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM));
24210a6a1f1dSLionel Sambuc 	for (i = 0; i < nent; i++) {
24220a6a1f1dSLionel Sambuc 		reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))];
24230a6a1f1dSLionel Sambuc 		printf("    Link Description Register: 0x%08x\n", reg);
24240a6a1f1dSLionel Sambuc 		onoff("Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID);
24250a6a1f1dSLionel Sambuc 		linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE;
24260a6a1f1dSLionel Sambuc 		onoff2("Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE,
24270a6a1f1dSLionel Sambuc 		    "Configuration Space", "Memory-Mapped Space");
24280a6a1f1dSLionel Sambuc 		onoff("Associated RCRB Header", reg,
24290a6a1f1dSLionel Sambuc 		    PCI_RCLINK_DCL_LINKDESC_ARCRBH);
24300a6a1f1dSLionel Sambuc 		printf("      Target Component ID: %hhu\n",
24310a6a1f1dSLionel Sambuc 		    (unsigned char)__SHIFTOUT(reg,
24320a6a1f1dSLionel Sambuc 			PCI_RCLINK_DCL_LINKDESC_TCOMPID));
24330a6a1f1dSLionel Sambuc 		printf("      Target Port Number: %hhu\n",
24340a6a1f1dSLionel Sambuc 		    (unsigned char)__SHIFTOUT(reg,
24350a6a1f1dSLionel Sambuc 			PCI_RCLINK_DCL_LINKDESC_TPNUM));
24360a6a1f1dSLionel Sambuc 
24370a6a1f1dSLionel Sambuc 		if (linktype == 0) {
24380a6a1f1dSLionel Sambuc 			/* Memory-Mapped Space */
24390a6a1f1dSLionel Sambuc 			reg = regs[o2i(extcapoff
24400a6a1f1dSLionel Sambuc 				    + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))];
24410a6a1f1dSLionel Sambuc 			printf("    Link Address Low Register: 0x%08x\n", reg);
24420a6a1f1dSLionel Sambuc 			reg = regs[o2i(extcapoff
24430a6a1f1dSLionel Sambuc 				    + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))];
24440a6a1f1dSLionel Sambuc 			printf("    Link Address High Register: 0x%08x\n",reg);
24450a6a1f1dSLionel Sambuc 		} else {
24460a6a1f1dSLionel Sambuc 			unsigned int nb;
24470a6a1f1dSLionel Sambuc 			pcireg_t lo, hi;
24480a6a1f1dSLionel Sambuc 
24490a6a1f1dSLionel Sambuc 			/* Configuration Space */
24500a6a1f1dSLionel Sambuc 			lo = regs[o2i(extcapoff
24510a6a1f1dSLionel Sambuc 				    + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))];
24520a6a1f1dSLionel Sambuc 			printf("    Configuration Space Low Register: 0x%08x"
24530a6a1f1dSLionel Sambuc 			    "\n", lo);
24540a6a1f1dSLionel Sambuc 			hi = regs[o2i(extcapoff
24550a6a1f1dSLionel Sambuc 				    + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))];
24560a6a1f1dSLionel Sambuc 			printf("    Configuration Space High Register: 0x%08x"
24570a6a1f1dSLionel Sambuc 			    "\n", hi);
24580a6a1f1dSLionel Sambuc 			nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N);
24590a6a1f1dSLionel Sambuc 			printf("      N: %u\n", nb);
24600a6a1f1dSLionel Sambuc 			printf("      Func: %hhu\n",
24610a6a1f1dSLionel Sambuc 			    (unsigned char)__SHIFTOUT(lo,
24620a6a1f1dSLionel Sambuc 				PCI_RCLINK_DCL_LINKADDR_LT1_FUNC));
24630a6a1f1dSLionel Sambuc 			printf("      Dev: %hhu\n",
24640a6a1f1dSLionel Sambuc 			    (unsigned char)__SHIFTOUT(lo,
24650a6a1f1dSLionel Sambuc 				PCI_RCLINK_DCL_LINKADDR_LT1_DEV));
24660a6a1f1dSLionel Sambuc 			printf("      Bus: %hhu\n",
24670a6a1f1dSLionel Sambuc 			    (unsigned char)__SHIFTOUT(lo,
24680a6a1f1dSLionel Sambuc 				PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb)));
24690a6a1f1dSLionel Sambuc 			lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i);
24700a6a1f1dSLionel Sambuc 			printf("      Configuration Space Base Address: 0x%016"
24710a6a1f1dSLionel Sambuc 			    PRIx64 "\n", ((uint64_t)hi << 32) + lo);
24720a6a1f1dSLionel Sambuc 		}
24730a6a1f1dSLionel Sambuc 	}
24740a6a1f1dSLionel Sambuc }
24750a6a1f1dSLionel Sambuc 
24760a6a1f1dSLionel Sambuc /* XXX pci_conf_print_rclink_ctl_cap */
24770a6a1f1dSLionel Sambuc 
24780a6a1f1dSLionel Sambuc static void
pci_conf_print_rcec_assoc_cap(const pcireg_t * regs,int capoff,int extcapoff)24790a6a1f1dSLionel Sambuc pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff)
24800a6a1f1dSLionel Sambuc {
24810a6a1f1dSLionel Sambuc 	pcireg_t reg;
24820a6a1f1dSLionel Sambuc 
24830a6a1f1dSLionel Sambuc 	printf("\n  Root Complex Event Collector Association\n");
24840a6a1f1dSLionel Sambuc 
24850a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)];
24860a6a1f1dSLionel Sambuc 	printf("    Association Bitmap for Root Complex Integrated Devices:"
24870a6a1f1dSLionel Sambuc 	    " 0x%08x\n", reg);
24880a6a1f1dSLionel Sambuc }
24890a6a1f1dSLionel Sambuc 
24900a6a1f1dSLionel Sambuc /* XXX pci_conf_print_mfvc_cap */
24910a6a1f1dSLionel Sambuc /* XXX pci_conf_print_vc2_cap */
24920a6a1f1dSLionel Sambuc /* XXX pci_conf_print_rcrb_cap */
24930a6a1f1dSLionel Sambuc /* XXX pci_conf_print_vendor_cap */
24940a6a1f1dSLionel Sambuc /* XXX pci_conf_print_cac_cap */
24950a6a1f1dSLionel Sambuc 
24960a6a1f1dSLionel Sambuc static void
pci_conf_print_acs_cap(const pcireg_t * regs,int capoff,int extcapoff)24970a6a1f1dSLionel Sambuc pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff)
24980a6a1f1dSLionel Sambuc {
24990a6a1f1dSLionel Sambuc 	pcireg_t reg, cap, ctl;
25000a6a1f1dSLionel Sambuc 	unsigned int size, i;
25010a6a1f1dSLionel Sambuc 
25020a6a1f1dSLionel Sambuc 	printf("\n  Access Control Services\n");
25030a6a1f1dSLionel Sambuc 
25040a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_ACS_CAP)];
25050a6a1f1dSLionel Sambuc 	cap = reg & 0xffff;
25060a6a1f1dSLionel Sambuc 	ctl = reg >> 16;
25070a6a1f1dSLionel Sambuc 	printf("    ACS Capability register: 0x%08x\n", cap);
25080a6a1f1dSLionel Sambuc 	onoff("ACS Source Validation", cap, PCI_ACS_CAP_V);
25090a6a1f1dSLionel Sambuc 	onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B);
25100a6a1f1dSLionel Sambuc 	onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R);
25110a6a1f1dSLionel Sambuc 	onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C);
25120a6a1f1dSLionel Sambuc 	onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U);
25130a6a1f1dSLionel Sambuc 	onoff("ACS Egress Control", cap, PCI_ACS_CAP_E);
25140a6a1f1dSLionel Sambuc 	onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T);
25150a6a1f1dSLionel Sambuc 	size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE);
25160a6a1f1dSLionel Sambuc 	if (size == 0)
25170a6a1f1dSLionel Sambuc 		size = 256;
25180a6a1f1dSLionel Sambuc 	printf("      Egress Control Vector Size: %u\n", size);
25190a6a1f1dSLionel Sambuc 	printf("    ACS Control register: 0x%08x\n", ctl);
25200a6a1f1dSLionel Sambuc 	onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V);
25210a6a1f1dSLionel Sambuc 	onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B);
25220a6a1f1dSLionel Sambuc 	onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R);
25230a6a1f1dSLionel Sambuc 	onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C);
25240a6a1f1dSLionel Sambuc 	onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U);
25250a6a1f1dSLionel Sambuc 	onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E);
25260a6a1f1dSLionel Sambuc 	onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T);
25270a6a1f1dSLionel Sambuc 
25280a6a1f1dSLionel Sambuc 	/*
25290a6a1f1dSLionel Sambuc 	 * If the P2P Egress Control Capability bit is 0, ignore the Egress
25300a6a1f1dSLionel Sambuc 	 * Control vector.
25310a6a1f1dSLionel Sambuc 	 */
25320a6a1f1dSLionel Sambuc 	if ((cap & PCI_ACS_CAP_E) == 0)
25330a6a1f1dSLionel Sambuc 		return;
25340a6a1f1dSLionel Sambuc 	for (i = 0; i < size; i += 32)
25350a6a1f1dSLionel Sambuc 		printf("    Egress Control Vector [%u..%u]: %x\n", i + 31,
25360a6a1f1dSLionel Sambuc 		    i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]);
25370a6a1f1dSLionel Sambuc }
25380a6a1f1dSLionel Sambuc 
25390a6a1f1dSLionel Sambuc static void
pci_conf_print_ari_cap(const pcireg_t * regs,int capoff,int extcapoff)25400a6a1f1dSLionel Sambuc pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff)
25410a6a1f1dSLionel Sambuc {
25420a6a1f1dSLionel Sambuc 	pcireg_t reg, cap, ctl;
25430a6a1f1dSLionel Sambuc 
25440a6a1f1dSLionel Sambuc 	printf("\n  Alternative Routing-ID Interpretation Register\n");
25450a6a1f1dSLionel Sambuc 
25460a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_ARI_CAP)];
25470a6a1f1dSLionel Sambuc 	cap = reg & 0xffff;
25480a6a1f1dSLionel Sambuc 	ctl = reg >> 16;
25490a6a1f1dSLionel Sambuc 	printf("    Capability register: 0x%08x\n", cap);
25500a6a1f1dSLionel Sambuc 	onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M);
25510a6a1f1dSLionel Sambuc 	onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A);
25520a6a1f1dSLionel Sambuc 	printf("      Next Function Number: %u\n",
25530a6a1f1dSLionel Sambuc 	    (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN));
25540a6a1f1dSLionel Sambuc 	printf("    Control register: 0x%08x\n", ctl);
25550a6a1f1dSLionel Sambuc 	onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M);
25560a6a1f1dSLionel Sambuc 	onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A);
25570a6a1f1dSLionel Sambuc 	printf("      Function Group: %u\n",
25580a6a1f1dSLionel Sambuc 	    (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP));
25590a6a1f1dSLionel Sambuc }
25600a6a1f1dSLionel Sambuc 
25610a6a1f1dSLionel Sambuc static void
pci_conf_print_ats_cap(const pcireg_t * regs,int capoff,int extcapoff)25620a6a1f1dSLionel Sambuc pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff)
25630a6a1f1dSLionel Sambuc {
25640a6a1f1dSLionel Sambuc 	pcireg_t reg, cap, ctl;
25650a6a1f1dSLionel Sambuc 	unsigned int num;
25660a6a1f1dSLionel Sambuc 
25670a6a1f1dSLionel Sambuc 	printf("\n  Address Translation Services\n");
25680a6a1f1dSLionel Sambuc 
25690a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_ARI_CAP)];
25700a6a1f1dSLionel Sambuc 	cap = reg & 0xffff;
25710a6a1f1dSLionel Sambuc 	ctl = reg >> 16;
25720a6a1f1dSLionel Sambuc 	printf("    Capability register: 0x%04x\n", cap);
25730a6a1f1dSLionel Sambuc 	num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH);
25740a6a1f1dSLionel Sambuc 	if (num == 0)
25750a6a1f1dSLionel Sambuc 		num = 32;
25760a6a1f1dSLionel Sambuc 	printf("      Invalidate Queue Depth: %u\n", num);
25770a6a1f1dSLionel Sambuc 	onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ);
25780a6a1f1dSLionel Sambuc 
25790a6a1f1dSLionel Sambuc 	printf("    Control register: 0x%04x\n", ctl);
25800a6a1f1dSLionel Sambuc 	printf("      Smallest Translation Unit: %u\n",
25810a6a1f1dSLionel Sambuc 	    (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU));
25820a6a1f1dSLionel Sambuc 	onoff("Enable", reg, PCI_ATS_CTL_EN);
25830a6a1f1dSLionel Sambuc }
25840a6a1f1dSLionel Sambuc 
25850a6a1f1dSLionel Sambuc static void
pci_conf_print_sernum_cap(const pcireg_t * regs,int capoff,int extcapoff)25860a6a1f1dSLionel Sambuc pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff)
25870a6a1f1dSLionel Sambuc {
25880a6a1f1dSLionel Sambuc 	pcireg_t lo, hi;
25890a6a1f1dSLionel Sambuc 
25900a6a1f1dSLionel Sambuc 	printf("\n  Device Serial Number Register\n");
25910a6a1f1dSLionel Sambuc 
25920a6a1f1dSLionel Sambuc 	lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)];
25930a6a1f1dSLionel Sambuc 	hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)];
25940a6a1f1dSLionel Sambuc 	printf("    Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
25950a6a1f1dSLionel Sambuc 	    hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff,
25960a6a1f1dSLionel Sambuc 	    lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff);
25970a6a1f1dSLionel Sambuc }
25980a6a1f1dSLionel Sambuc 
25990a6a1f1dSLionel Sambuc static void
pci_conf_print_sriov_cap(const pcireg_t * regs,int capoff,int extcapoff)26000a6a1f1dSLionel Sambuc pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff)
26010a6a1f1dSLionel Sambuc {
26020a6a1f1dSLionel Sambuc 	char buf[sizeof("99999 MB")];
26030a6a1f1dSLionel Sambuc 	pcireg_t reg;
26040a6a1f1dSLionel Sambuc 	pcireg_t total_vfs;
26050a6a1f1dSLionel Sambuc 	int i;
26060a6a1f1dSLionel Sambuc 	bool first;
26070a6a1f1dSLionel Sambuc 
26080a6a1f1dSLionel Sambuc 	printf("\n  Single Root IO Virtualization Register\n");
26090a6a1f1dSLionel Sambuc 
26100a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)];
26110a6a1f1dSLionel Sambuc 	printf("    Capabilities register: 0x%08x\n", reg);
26120a6a1f1dSLionel Sambuc 	onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION);
26130a6a1f1dSLionel Sambuc 	onoff("ARI Capable Hierarchy Preserved", reg,
26140a6a1f1dSLionel Sambuc 	    PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED);
26150a6a1f1dSLionel Sambuc 	if (reg & PCI_SRIOV_CAP_VF_MIGRATION) {
26160a6a1f1dSLionel Sambuc 		printf("      VF Migration Interrupt Message Number: 0x%u\n",
26170a6a1f1dSLionel Sambuc 		    (pcireg_t)__SHIFTOUT(reg,
26180a6a1f1dSLionel Sambuc 		      PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N));
26190a6a1f1dSLionel Sambuc 	}
26200a6a1f1dSLionel Sambuc 
26210a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff;
26220a6a1f1dSLionel Sambuc 	printf("    Control register: 0x%04x\n", reg);
26230a6a1f1dSLionel Sambuc 	onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE);
26240a6a1f1dSLionel Sambuc 	onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT);
26250a6a1f1dSLionel Sambuc 	onoff("VF Migration Interrupt Enable", reg,
26260a6a1f1dSLionel Sambuc 	    PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE);
26270a6a1f1dSLionel Sambuc 	onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE);
26280a6a1f1dSLionel Sambuc 	onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER);
26290a6a1f1dSLionel Sambuc 
26300a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16;
26310a6a1f1dSLionel Sambuc 	printf("    Status register: 0x%04x\n", reg);
26320a6a1f1dSLionel Sambuc 	onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION);
26330a6a1f1dSLionel Sambuc 
26340a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff;
26350a6a1f1dSLionel Sambuc 	printf("    InitialVFs register: 0x%04x\n", reg);
26360a6a1f1dSLionel Sambuc 	total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16;
26370a6a1f1dSLionel Sambuc 	printf("    TotalVFs register: 0x%04x\n", reg);
26380a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff;
26390a6a1f1dSLionel Sambuc 	printf("    NumVFs register: 0x%04x\n", reg);
26400a6a1f1dSLionel Sambuc 
26410a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16;
26420a6a1f1dSLionel Sambuc 	printf("    Function Dependency Link register: 0x%04x\n", reg);
26430a6a1f1dSLionel Sambuc 
26440a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff;
26450a6a1f1dSLionel Sambuc 	printf("    First VF Offset register: 0x%04x\n", reg);
26460a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16;
26470a6a1f1dSLionel Sambuc 	printf("    VF Stride register: 0x%04x\n", reg);
26480a6a1f1dSLionel Sambuc 
26490a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)];
26500a6a1f1dSLionel Sambuc 	printf("    Supported Page Sizes register: 0x%08x\n", reg);
26510a6a1f1dSLionel Sambuc 	printf("      Supported Page Size:");
26520a6a1f1dSLionel Sambuc 	for (i = 0, first = true; i < 32; i++) {
26530a6a1f1dSLionel Sambuc 		if (reg & __BIT(i)) {
26540a6a1f1dSLionel Sambuc #ifdef _KERNEL
26550a6a1f1dSLionel Sambuc 			format_bytes(buf, sizeof(buf), 1LL << (i + 12));
26560a6a1f1dSLionel Sambuc #else
26570a6a1f1dSLionel Sambuc 			humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B",
26580a6a1f1dSLionel Sambuc 			    HN_AUTOSCALE, 0);
26590a6a1f1dSLionel Sambuc #endif
26600a6a1f1dSLionel Sambuc 			printf("%s %s", first ? "" : ",", buf);
26610a6a1f1dSLionel Sambuc 			first = false;
26620a6a1f1dSLionel Sambuc 		}
26630a6a1f1dSLionel Sambuc 	}
26640a6a1f1dSLionel Sambuc 	printf("\n");
26650a6a1f1dSLionel Sambuc 
26660a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)];
26670a6a1f1dSLionel Sambuc 	printf("    System Page Sizes register: 0x%08x\n", reg);
26680a6a1f1dSLionel Sambuc 	printf("      Page Size: ");
26690a6a1f1dSLionel Sambuc 	if (reg != 0) {
26700a6a1f1dSLionel Sambuc #ifdef _KERNEL
26710a6a1f1dSLionel Sambuc 		format_bytes(buf, sizeof(buf), 1LL << (ffs(reg) + 12));
26720a6a1f1dSLionel Sambuc #else
26730a6a1f1dSLionel Sambuc 		humanize_number(buf, sizeof(buf), 1LL << (ffs(reg) + 12), "B",
26740a6a1f1dSLionel Sambuc 		    HN_AUTOSCALE, 0);
26750a6a1f1dSLionel Sambuc #endif
26760a6a1f1dSLionel Sambuc 		printf("%s", buf);
26770a6a1f1dSLionel Sambuc 	} else {
26787eb99bdaSLionel Sambuc 		printf("unknown");
26797eb99bdaSLionel Sambuc 	}
26800a6a1f1dSLionel Sambuc 	printf("\n");
26810a6a1f1dSLionel Sambuc 
26820a6a1f1dSLionel Sambuc 	for (i = 0; i < 6; i++) {
26830a6a1f1dSLionel Sambuc 		reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))];
26840a6a1f1dSLionel Sambuc 		printf("    VF BAR%d register: 0x%08x\n", i, reg);
26857eb99bdaSLionel Sambuc 	}
26860a6a1f1dSLionel Sambuc 
26870a6a1f1dSLionel Sambuc 	if (total_vfs > 0) {
26880a6a1f1dSLionel Sambuc 		reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)];
26890a6a1f1dSLionel Sambuc 		printf("    VF Migration State Array Offset register: 0x%08x\n",
26900a6a1f1dSLionel Sambuc 		    reg);
26910a6a1f1dSLionel Sambuc 		printf("      VF Migration State Offset: 0x%08x\n",
26920a6a1f1dSLionel Sambuc 		    (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET));
26930a6a1f1dSLionel Sambuc 		i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR);
26940a6a1f1dSLionel Sambuc 		printf("      VF Migration State BIR: ");
26950a6a1f1dSLionel Sambuc 		if (i >= 0 && i <= 5) {
26960a6a1f1dSLionel Sambuc 			printf("BAR%d", i);
26970a6a1f1dSLionel Sambuc 		} else {
26980a6a1f1dSLionel Sambuc 			printf("unknown BAR (%d)", i);
26990a6a1f1dSLionel Sambuc 		}
27000a6a1f1dSLionel Sambuc 		printf("\n");
27010a6a1f1dSLionel Sambuc 	}
27020a6a1f1dSLionel Sambuc }
27030a6a1f1dSLionel Sambuc 
27040a6a1f1dSLionel Sambuc /* XXX pci_conf_print_mriov_cap */
27050a6a1f1dSLionel Sambuc /* XXX pci_conf_print_multicast_cap */
27060a6a1f1dSLionel Sambuc 
27070a6a1f1dSLionel Sambuc static void
pci_conf_print_page_req_cap(const pcireg_t * regs,int capoff,int extcapoff)27080a6a1f1dSLionel Sambuc pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff)
27090a6a1f1dSLionel Sambuc {
27100a6a1f1dSLionel Sambuc 	pcireg_t reg, ctl, sta;
27110a6a1f1dSLionel Sambuc 
27120a6a1f1dSLionel Sambuc 	printf("\n  Page Request\n");
27130a6a1f1dSLionel Sambuc 
27140a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)];
27150a6a1f1dSLionel Sambuc 	ctl = reg & 0xffff;
27160a6a1f1dSLionel Sambuc 	sta = reg >> 16;
27170a6a1f1dSLionel Sambuc 	printf("    Control Register: 0x%04x\n", ctl);
27180a6a1f1dSLionel Sambuc 	onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E);
27190a6a1f1dSLionel Sambuc 	onoff("Reset", reg, PCI_PAGE_REQ_CTL_R);
27200a6a1f1dSLionel Sambuc 
27210a6a1f1dSLionel Sambuc 	printf("    Status Register: 0x%04x\n", sta);
27220a6a1f1dSLionel Sambuc 	onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF);
27230a6a1f1dSLionel Sambuc 	onoff("Unexpected Page Request Group Index", reg,
27240a6a1f1dSLionel Sambuc 	    PCI_PAGE_REQ_STA_UPRGI);
27250a6a1f1dSLionel Sambuc 	onoff("Stopped", reg, PCI_PAGE_REQ_STA_S);
27260a6a1f1dSLionel Sambuc 
27270a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)];
27280a6a1f1dSLionel Sambuc 	printf("    Outstanding Page Request Capacity: %u\n", reg);
27290a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)];
27300a6a1f1dSLionel Sambuc 	printf("    Outstanding Page Request Allocation: %u\n", reg);
27310a6a1f1dSLionel Sambuc }
27320a6a1f1dSLionel Sambuc 
27330a6a1f1dSLionel Sambuc /* XXX pci_conf_print_amd_cap */
27340a6a1f1dSLionel Sambuc /* XXX pci_conf_print_resize_bar_cap */
27350a6a1f1dSLionel Sambuc /* XXX pci_conf_print_dpa_cap */
27360a6a1f1dSLionel Sambuc 
27370a6a1f1dSLionel Sambuc static const char *
pci_conf_print_tph_req_cap_sttabloc(unsigned char val)27380a6a1f1dSLionel Sambuc pci_conf_print_tph_req_cap_sttabloc(unsigned char val)
27390a6a1f1dSLionel Sambuc {
27400a6a1f1dSLionel Sambuc 
27410a6a1f1dSLionel Sambuc 	switch (val) {
27420a6a1f1dSLionel Sambuc 	case 0x0:
27430a6a1f1dSLionel Sambuc 		return "Not Present";
27440a6a1f1dSLionel Sambuc 	case 0x1:
27450a6a1f1dSLionel Sambuc 		return "in the TPH Requester Capability Structure";
27460a6a1f1dSLionel Sambuc 	case 0x2:
27470a6a1f1dSLionel Sambuc 		return "in the MSI-X Table";
27480a6a1f1dSLionel Sambuc 	default:
27490a6a1f1dSLionel Sambuc 		return "Unknown";
27500a6a1f1dSLionel Sambuc 	}
27510a6a1f1dSLionel Sambuc }
27520a6a1f1dSLionel Sambuc 
27530a6a1f1dSLionel Sambuc static void
pci_conf_print_tph_req_cap(const pcireg_t * regs,int capoff,int extcapoff)27540a6a1f1dSLionel Sambuc pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff)
27550a6a1f1dSLionel Sambuc {
27560a6a1f1dSLionel Sambuc 	pcireg_t reg;
27570a6a1f1dSLionel Sambuc 	int size, i, j;
27580a6a1f1dSLionel Sambuc 
27590a6a1f1dSLionel Sambuc 	printf("\n  TPH Requester Extended Capability\n");
27600a6a1f1dSLionel Sambuc 
27610a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)];
27620a6a1f1dSLionel Sambuc 	printf("    TPH Requester Capabililty register: 0x%08x\n", reg);
27630a6a1f1dSLionel Sambuc 	onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST);
27640a6a1f1dSLionel Sambuc 	onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC);
27650a6a1f1dSLionel Sambuc 	onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC);
27660a6a1f1dSLionel Sambuc 	onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ);
27670a6a1f1dSLionel Sambuc 	printf("      ST Table Location: %s\n",
27680a6a1f1dSLionel Sambuc 	    pci_conf_print_tph_req_cap_sttabloc(
27690a6a1f1dSLionel Sambuc 		    (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC)));
27700a6a1f1dSLionel Sambuc 	size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1;
27710a6a1f1dSLionel Sambuc 	printf("      ST Table Size: %d\n", size);
27720a6a1f1dSLionel Sambuc 	for (i = 0; i < size ; i += 2) {
27730a6a1f1dSLionel Sambuc 		reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)];
27740a6a1f1dSLionel Sambuc 		for (j = 0; j < 2 ; j++) {
27750a6a1f1dSLionel Sambuc 			uint32_t entry = reg;
27760a6a1f1dSLionel Sambuc 
27770a6a1f1dSLionel Sambuc 			if (j != 0)
27780a6a1f1dSLionel Sambuc 				entry >>= 16;
27790a6a1f1dSLionel Sambuc 			entry &= 0xffff;
27800a6a1f1dSLionel Sambuc 			printf("    TPH ST Table Entry (%d): 0x%04"PRIx32"\n",
27810a6a1f1dSLionel Sambuc 			    i + j, entry);
27820a6a1f1dSLionel Sambuc 		}
27830a6a1f1dSLionel Sambuc 	}
27840a6a1f1dSLionel Sambuc }
27850a6a1f1dSLionel Sambuc 
27860a6a1f1dSLionel Sambuc static void
pci_conf_print_ltr_cap(const pcireg_t * regs,int capoff,int extcapoff)27870a6a1f1dSLionel Sambuc pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff)
27880a6a1f1dSLionel Sambuc {
27890a6a1f1dSLionel Sambuc 	pcireg_t reg;
27900a6a1f1dSLionel Sambuc 
27910a6a1f1dSLionel Sambuc 	printf("\n  Latency Tolerance Reporting\n");
27920a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff;
27930a6a1f1dSLionel Sambuc 	printf("    Max Snoop Latency Register: 0x%04x\n", reg);
27940a6a1f1dSLionel Sambuc 	printf("      Max Snoop LatencyValue: %u\n",
27950a6a1f1dSLionel Sambuc 	    (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL));
27960a6a1f1dSLionel Sambuc 	printf("      Max Snoop LatencyScale: %uns\n",
27970a6a1f1dSLionel Sambuc 	    PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE)));
27980a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16;
27990a6a1f1dSLionel Sambuc 	printf("    Max No-Snoop Latency Register: 0x%04x\n", reg);
28000a6a1f1dSLionel Sambuc 	printf("      Max No-Snoop LatencyValue: %u\n",
28010a6a1f1dSLionel Sambuc 	    (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL));
28020a6a1f1dSLionel Sambuc 	printf("      Max No-Snoop LatencyScale: %uns\n",
28030a6a1f1dSLionel Sambuc 	    PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE)));
28040a6a1f1dSLionel Sambuc }
28050a6a1f1dSLionel Sambuc 
28060a6a1f1dSLionel Sambuc static void
pci_conf_print_sec_pcie_cap(const pcireg_t * regs,int capoff,int extcapoff)28070a6a1f1dSLionel Sambuc pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff)
28080a6a1f1dSLionel Sambuc {
28090a6a1f1dSLionel Sambuc 	int pcie_capoff;
28100a6a1f1dSLionel Sambuc 	pcireg_t reg;
28110a6a1f1dSLionel Sambuc 	int i, maxlinkwidth;
28120a6a1f1dSLionel Sambuc 
28130a6a1f1dSLionel Sambuc 	printf("\n  Secondary PCI Express Register\n");
28140a6a1f1dSLionel Sambuc 
28150a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)];
28160a6a1f1dSLionel Sambuc 	printf("    Link Control 3 register: 0x%08x\n", reg);
28170a6a1f1dSLionel Sambuc 	onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ);
28180a6a1f1dSLionel Sambuc 	onoff("Link Equalization Request Interrupt Enable",
28190a6a1f1dSLionel Sambuc 	    reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE);
28200a6a1f1dSLionel Sambuc 
28210a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)];
28220a6a1f1dSLionel Sambuc 	printf("    Lane Error Status register: 0x%08x\n", reg);
28230a6a1f1dSLionel Sambuc 
28240a6a1f1dSLionel Sambuc 	/* Get Max Link Width */
28250a6a1f1dSLionel Sambuc 	if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){
28260a6a1f1dSLionel Sambuc 		reg = regs[o2i(pcie_capoff + PCIE_LCAP)];
28270a6a1f1dSLionel Sambuc 		maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH);
28280a6a1f1dSLionel Sambuc 	} else {
28290a6a1f1dSLionel Sambuc 		printf("error: falied to get PCIe capablity\n");
28300a6a1f1dSLionel Sambuc 		return;
28310a6a1f1dSLionel Sambuc 	}
28320a6a1f1dSLionel Sambuc 	for (i = 0; i < maxlinkwidth; i++) {
28330a6a1f1dSLionel Sambuc 		reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))];
28340a6a1f1dSLionel Sambuc 		if (i % 2 != 0)
28350a6a1f1dSLionel Sambuc 			reg >>= 16;
28360a6a1f1dSLionel Sambuc 		else
28370a6a1f1dSLionel Sambuc 			reg &= 0xffff;
28380a6a1f1dSLionel Sambuc 		printf("    Equalization Control Register (Link %d): %04x\n",
28390a6a1f1dSLionel Sambuc 		    i, reg);
28400a6a1f1dSLionel Sambuc 		printf("      Downstream Port Transmit Preset: 0x%x\n",
28410a6a1f1dSLionel Sambuc 		    (pcireg_t)__SHIFTOUT(reg,
28420a6a1f1dSLionel Sambuc 			PCI_SECPCIE_EQCTL_DP_XMIT_PRESET));
28430a6a1f1dSLionel Sambuc 		printf("      Downstream Port Receive Hint: 0x%x\n",
28440a6a1f1dSLionel Sambuc 		    (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT));
28450a6a1f1dSLionel Sambuc 		printf("      Upstream Port Transmit Preset: 0x%x\n",
28460a6a1f1dSLionel Sambuc 		    (pcireg_t)__SHIFTOUT(reg,
28470a6a1f1dSLionel Sambuc 			PCI_SECPCIE_EQCTL_UP_XMIT_PRESET));
28480a6a1f1dSLionel Sambuc 		printf("      Upstream Port Receive Hint: 0x%x\n",
28490a6a1f1dSLionel Sambuc 		    (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT));
28500a6a1f1dSLionel Sambuc 	}
28510a6a1f1dSLionel Sambuc }
28520a6a1f1dSLionel Sambuc 
28530a6a1f1dSLionel Sambuc /* XXX pci_conf_print_pmux_cap */
28540a6a1f1dSLionel Sambuc 
28550a6a1f1dSLionel Sambuc static void
pci_conf_print_pasid_cap(const pcireg_t * regs,int capoff,int extcapoff)28560a6a1f1dSLionel Sambuc pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff)
28570a6a1f1dSLionel Sambuc {
28580a6a1f1dSLionel Sambuc 	pcireg_t reg, cap, ctl;
28590a6a1f1dSLionel Sambuc 	unsigned int num;
28600a6a1f1dSLionel Sambuc 
28610a6a1f1dSLionel Sambuc 	printf("\n  Process Address Space ID\n");
28620a6a1f1dSLionel Sambuc 
28630a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_PASID_CAP)];
28640a6a1f1dSLionel Sambuc 	cap = reg & 0xffff;
28650a6a1f1dSLionel Sambuc 	ctl = reg >> 16;
28660a6a1f1dSLionel Sambuc 	printf("    PASID Capability Register: 0x%04x\n", cap);
28670a6a1f1dSLionel Sambuc 	onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM);
28680a6a1f1dSLionel Sambuc 	onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE);
28690a6a1f1dSLionel Sambuc 	num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1;
28700a6a1f1dSLionel Sambuc 	printf("      Max PASID Width: %u\n", num);
28710a6a1f1dSLionel Sambuc 
28720a6a1f1dSLionel Sambuc 	printf("    PASID Control Register: 0x%04x\n", ctl);
28730a6a1f1dSLionel Sambuc 	onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN);
28740a6a1f1dSLionel Sambuc 	onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN);
28750a6a1f1dSLionel Sambuc 	onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN);
28760a6a1f1dSLionel Sambuc }
28770a6a1f1dSLionel Sambuc 
28780a6a1f1dSLionel Sambuc static void
pci_conf_print_lnr_cap(const pcireg_t * regs,int capoff,int extcapoff)28790a6a1f1dSLionel Sambuc pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff)
28800a6a1f1dSLionel Sambuc {
28810a6a1f1dSLionel Sambuc 	pcireg_t reg, cap, ctl;
28820a6a1f1dSLionel Sambuc 	unsigned int num;
28830a6a1f1dSLionel Sambuc 
28840a6a1f1dSLionel Sambuc 	printf("\n  LN Requester\n");
28850a6a1f1dSLionel Sambuc 
28860a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_LNR_CAP)];
28870a6a1f1dSLionel Sambuc 	cap = reg & 0xffff;
28880a6a1f1dSLionel Sambuc 	ctl = reg >> 16;
28890a6a1f1dSLionel Sambuc 	printf("    LNR Capability register: 0x%04x\n", cap);
28900a6a1f1dSLionel Sambuc 	onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64);
28910a6a1f1dSLionel Sambuc 	onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128);
28920a6a1f1dSLionel Sambuc 	num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX);
28930a6a1f1dSLionel Sambuc 	printf("      LNR Registration MAX: %u\n", num);
28940a6a1f1dSLionel Sambuc 
28950a6a1f1dSLionel Sambuc 	printf("    LNR Control register: 0x%04x\n", ctl);
28960a6a1f1dSLionel Sambuc 	onoff("LNR Enable", reg, PCI_LNR_CTL_EN);
28970a6a1f1dSLionel Sambuc 	onoff("LNR CLS", reg, PCI_LNR_CTL_CLS);
28980a6a1f1dSLionel Sambuc 	num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM);
28990a6a1f1dSLionel Sambuc 	printf("      LNR Registration Limit: %u\n", num);
29000a6a1f1dSLionel Sambuc }
29010a6a1f1dSLionel Sambuc 
29020a6a1f1dSLionel Sambuc /* XXX pci_conf_print_dpc_cap */
29030a6a1f1dSLionel Sambuc 
29040a6a1f1dSLionel Sambuc static int
pci_conf_l1pm_cap_tposcale(unsigned char scale)29050a6a1f1dSLionel Sambuc pci_conf_l1pm_cap_tposcale(unsigned char scale)
29060a6a1f1dSLionel Sambuc {
29070a6a1f1dSLionel Sambuc 
29080a6a1f1dSLionel Sambuc 	/* Return scale in us */
29090a6a1f1dSLionel Sambuc 	switch (scale) {
29100a6a1f1dSLionel Sambuc 	case 0x0:
29110a6a1f1dSLionel Sambuc 		return 2;
29120a6a1f1dSLionel Sambuc 	case 0x1:
29130a6a1f1dSLionel Sambuc 		return 10;
29140a6a1f1dSLionel Sambuc 	case 0x2:
29150a6a1f1dSLionel Sambuc 		return 100;
29160a6a1f1dSLionel Sambuc 	default:
29170a6a1f1dSLionel Sambuc 		return -1;
29180a6a1f1dSLionel Sambuc 	}
29190a6a1f1dSLionel Sambuc }
29200a6a1f1dSLionel Sambuc 
29210a6a1f1dSLionel Sambuc static void
pci_conf_print_l1pm_cap(const pcireg_t * regs,int capoff,int extcapoff)29220a6a1f1dSLionel Sambuc pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff)
29230a6a1f1dSLionel Sambuc {
29240a6a1f1dSLionel Sambuc 	pcireg_t reg;
29250a6a1f1dSLionel Sambuc 	int scale, val;
29260a6a1f1dSLionel Sambuc 
29270a6a1f1dSLionel Sambuc 	printf("\n  L1 PM Substates\n");
29280a6a1f1dSLionel Sambuc 
29290a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_L1PM_CAP)];
29300a6a1f1dSLionel Sambuc 	printf("    L1 PM Substates Capability register: 0x%08x\n", reg);
29310a6a1f1dSLionel Sambuc 	onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12);
29320a6a1f1dSLionel Sambuc 	onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11);
29330a6a1f1dSLionel Sambuc 	onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12);
29340a6a1f1dSLionel Sambuc 	onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11);
29350a6a1f1dSLionel Sambuc 	onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM);
29360a6a1f1dSLionel Sambuc 	printf("      Port Common Mode Restore Time: %uus\n",
29370a6a1f1dSLionel Sambuc 	    (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT));
29380a6a1f1dSLionel Sambuc 	scale = pci_conf_l1pm_cap_tposcale(
29390a6a1f1dSLionel Sambuc 		__SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE));
29400a6a1f1dSLionel Sambuc 	val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL);
29410a6a1f1dSLionel Sambuc 	printf("      Port T_POWER_ON: ");
29420a6a1f1dSLionel Sambuc 	if (scale == -1)
29430a6a1f1dSLionel Sambuc 		printf("unknown\n");
29440a6a1f1dSLionel Sambuc 	else
29450a6a1f1dSLionel Sambuc 		printf("%dus\n", val * scale);
29460a6a1f1dSLionel Sambuc 
29470a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)];
29480a6a1f1dSLionel Sambuc 	printf("    L1 PM Substates Control register 1: 0x%08x\n", reg);
29490a6a1f1dSLionel Sambuc 	onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN);
29500a6a1f1dSLionel Sambuc 	onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN);
29510a6a1f1dSLionel Sambuc 	onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN);
29520a6a1f1dSLionel Sambuc 	onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN);
29530a6a1f1dSLionel Sambuc 	printf("      Common Mode Restore Time: %uus\n",
29540a6a1f1dSLionel Sambuc 	    (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT));
29550a6a1f1dSLionel Sambuc 	scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE));
29560a6a1f1dSLionel Sambuc 	val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL);
29570a6a1f1dSLionel Sambuc 	printf("      LTR L1.2 THRESHOLD: %dus\n", val * scale);
29580a6a1f1dSLionel Sambuc 
29590a6a1f1dSLionel Sambuc 	reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)];
29600a6a1f1dSLionel Sambuc 	printf("    L1 PM Substates Control register 2: 0x%08x\n", reg);
29610a6a1f1dSLionel Sambuc 	scale = pci_conf_l1pm_cap_tposcale(
29620a6a1f1dSLionel Sambuc 		__SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE));
29630a6a1f1dSLionel Sambuc 	val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL);
29640a6a1f1dSLionel Sambuc 	printf("      T_POWER_ON: ");
29650a6a1f1dSLionel Sambuc 	if (scale == -1)
29660a6a1f1dSLionel Sambuc 		printf("unknown\n");
29670a6a1f1dSLionel Sambuc 	else
29680a6a1f1dSLionel Sambuc 		printf("%dus\n", val * scale);
29690a6a1f1dSLionel Sambuc }
29700a6a1f1dSLionel Sambuc 
29710a6a1f1dSLionel Sambuc /* XXX pci_conf_print_ptm_cap */
29720a6a1f1dSLionel Sambuc /* XXX pci_conf_print_mpcie_cap */
29730a6a1f1dSLionel Sambuc /* XXX pci_conf_print_frsq_cap */
29740a6a1f1dSLionel Sambuc /* XXX pci_conf_print_rtr_cap */
29750a6a1f1dSLionel Sambuc /* XXX pci_conf_print_desigvndsp_cap */
29760a6a1f1dSLionel Sambuc 
29770a6a1f1dSLionel Sambuc #undef	MS
29780a6a1f1dSLionel Sambuc #undef	SM
29790a6a1f1dSLionel Sambuc #undef	RW
29800a6a1f1dSLionel Sambuc 
29810a6a1f1dSLionel Sambuc static struct {
29820a6a1f1dSLionel Sambuc 	pcireg_t cap;
29830a6a1f1dSLionel Sambuc 	const char *name;
29840a6a1f1dSLionel Sambuc 	void (*printfunc)(const pcireg_t *, int, int);
29850a6a1f1dSLionel Sambuc } pci_extcaptab[] = {
29860a6a1f1dSLionel Sambuc 	{ 0,			"reserved",
29870a6a1f1dSLionel Sambuc 	  NULL },
29880a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_AER,	"Advanced Error Reporting",
29890a6a1f1dSLionel Sambuc 	  pci_conf_print_aer_cap },
29900a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_VC,	"Virtual Channel",
29910a6a1f1dSLionel Sambuc 	  pci_conf_print_vc_cap },
29920a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_SERNUM,	"Device Serial Number",
29930a6a1f1dSLionel Sambuc 	  pci_conf_print_sernum_cap },
29940a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_PWRBDGT,	"Power Budgeting",
29950a6a1f1dSLionel Sambuc 	  pci_conf_print_pwrbdgt_cap },
29960a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration",
29970a6a1f1dSLionel Sambuc 	  pci_conf_print_rclink_dcl_cap },
29980a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control",
29990a6a1f1dSLionel Sambuc 	  NULL },
30000a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association",
30010a6a1f1dSLionel Sambuc 	  pci_conf_print_rcec_assoc_cap },
30020a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_MFVC,	"Multi-Function Virtual Channel",
30030a6a1f1dSLionel Sambuc 	  NULL },
30040a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_VC2,	"Virtual Channel",
30050a6a1f1dSLionel Sambuc 	  NULL },
30060a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_RCRB,	"RCRB Header",
30070a6a1f1dSLionel Sambuc 	  NULL },
30080a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_VENDOR,	"Vendor Unique",
30090a6a1f1dSLionel Sambuc 	  NULL },
30100a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_CAC,	"Configuration Access Correction",
30110a6a1f1dSLionel Sambuc 	  NULL },
30120a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_ACS,	"Access Control Services",
30130a6a1f1dSLionel Sambuc 	  pci_conf_print_acs_cap },
30140a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_ARI,	"Alternative Routing-ID Interpretation",
30150a6a1f1dSLionel Sambuc 	  pci_conf_print_ari_cap },
30160a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_ATS,	"Address Translation Services",
30170a6a1f1dSLionel Sambuc 	  pci_conf_print_ats_cap },
30180a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_SRIOV,	"Single Root IO Virtualization",
30190a6a1f1dSLionel Sambuc 	  pci_conf_print_sriov_cap },
30200a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_MRIOV,	"Multiple Root IO Virtualization",
30210a6a1f1dSLionel Sambuc 	  NULL },
30220a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_MULTICAST,	"Multicast",
30230a6a1f1dSLionel Sambuc 	  NULL },
30240a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_PAGE_REQ,	"Page Request",
30250a6a1f1dSLionel Sambuc 	  pci_conf_print_page_req_cap },
30260a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_AMD,	"Reserved for AMD",
30270a6a1f1dSLionel Sambuc 	  NULL },
30280a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_RESIZE_BAR,"Resizable BAR",
30290a6a1f1dSLionel Sambuc 	  NULL },
30300a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_DPA,	"Dynamic Power Allocation",
30310a6a1f1dSLionel Sambuc 	  NULL },
30320a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_TPH_REQ,	"TPH Requester",
30330a6a1f1dSLionel Sambuc 	  pci_conf_print_tph_req_cap },
30340a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_LTR,	"Latency Tolerance Reporting",
30350a6a1f1dSLionel Sambuc 	  pci_conf_print_ltr_cap },
30360a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_SEC_PCIE,	"Secondary PCI Express",
30370a6a1f1dSLionel Sambuc 	  pci_conf_print_sec_pcie_cap },
30380a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_PMUX,	"Protocol Multiplexing",
30390a6a1f1dSLionel Sambuc 	  NULL },
30400a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_PASID,	"Process Address Space ID",
30410a6a1f1dSLionel Sambuc 	  pci_conf_print_pasid_cap },
30420a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_LN_REQ,	"LN Requester",
30430a6a1f1dSLionel Sambuc 	  pci_conf_print_lnr_cap },
30440a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_DPC,	"Downstream Port Containment",
30450a6a1f1dSLionel Sambuc 	  NULL },
30460a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_L1PM,	"L1 PM Substates",
30470a6a1f1dSLionel Sambuc 	  pci_conf_print_l1pm_cap },
30480a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_PTM,	"Precision Time Management",
30490a6a1f1dSLionel Sambuc 	  NULL },
30500a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_MPCIE,	"M-PCIe",
30510a6a1f1dSLionel Sambuc 	  NULL },
30520a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_FRSQ,	"Function Reading Status Queueing",
30530a6a1f1dSLionel Sambuc 	  NULL },
30540a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_RTR,	"Readiness Time Reporting",
30550a6a1f1dSLionel Sambuc 	  NULL },
30560a6a1f1dSLionel Sambuc 	{ PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific",
30570a6a1f1dSLionel Sambuc 	  NULL },
30580a6a1f1dSLionel Sambuc };
30590a6a1f1dSLionel Sambuc 
30600a6a1f1dSLionel Sambuc static int
pci_conf_find_extcap(const pcireg_t * regs,int capoff,unsigned int capid,int * offsetp)30610a6a1f1dSLionel Sambuc pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid,
30620a6a1f1dSLionel Sambuc     int *offsetp)
30630a6a1f1dSLionel Sambuc {
30640a6a1f1dSLionel Sambuc 	int off;
30650a6a1f1dSLionel Sambuc 	pcireg_t rval;
30660a6a1f1dSLionel Sambuc 
30670a6a1f1dSLionel Sambuc 	for (off = PCI_EXTCAPLIST_BASE;
30680a6a1f1dSLionel Sambuc 	     off != 0;
30690a6a1f1dSLionel Sambuc 	     off = PCI_EXTCAPLIST_NEXT(rval)) {
30700a6a1f1dSLionel Sambuc 		rval = regs[o2i(off)];
30710a6a1f1dSLionel Sambuc 		if (capid == PCI_EXTCAPLIST_CAP(rval)) {
30720a6a1f1dSLionel Sambuc 			if (offsetp != NULL)
30730a6a1f1dSLionel Sambuc 				*offsetp = off;
30740a6a1f1dSLionel Sambuc 			return 1;
30750a6a1f1dSLionel Sambuc 		}
30760a6a1f1dSLionel Sambuc 	}
30770a6a1f1dSLionel Sambuc 	return 0;
30780a6a1f1dSLionel Sambuc }
30790a6a1f1dSLionel Sambuc 
30800a6a1f1dSLionel Sambuc static void
pci_conf_print_extcaplist(pci_chipset_tag_t pc,pcitag_t tag,const pcireg_t * regs,int capoff)30810a6a1f1dSLionel Sambuc pci_conf_print_extcaplist(
30820a6a1f1dSLionel Sambuc #ifdef _KERNEL
30830a6a1f1dSLionel Sambuc     pci_chipset_tag_t pc, pcitag_t tag,
30840a6a1f1dSLionel Sambuc #endif
30850a6a1f1dSLionel Sambuc     const pcireg_t *regs, int capoff)
30860a6a1f1dSLionel Sambuc {
30870a6a1f1dSLionel Sambuc 	int off;
30880a6a1f1dSLionel Sambuc 	pcireg_t foundcap;
30890a6a1f1dSLionel Sambuc 	pcireg_t rval;
30900a6a1f1dSLionel Sambuc 	bool foundtable[__arraycount(pci_extcaptab)];
30910a6a1f1dSLionel Sambuc 	unsigned int i;
30920a6a1f1dSLionel Sambuc 
30930a6a1f1dSLionel Sambuc 	/* Check Extended capability structure */
30940a6a1f1dSLionel Sambuc 	off = PCI_EXTCAPLIST_BASE;
30950a6a1f1dSLionel Sambuc 	rval = regs[o2i(off)];
30960a6a1f1dSLionel Sambuc 	if (rval == 0xffffffff || rval == 0)
30970a6a1f1dSLionel Sambuc 		return;
30980a6a1f1dSLionel Sambuc 
30990a6a1f1dSLionel Sambuc 	/* Clear table */
31000a6a1f1dSLionel Sambuc 	for (i = 0; i < __arraycount(pci_extcaptab); i++)
31010a6a1f1dSLionel Sambuc 		foundtable[i] = false;
31020a6a1f1dSLionel Sambuc 
31030a6a1f1dSLionel Sambuc 	/* Print extended capability register's offset and the type first */
31040a6a1f1dSLionel Sambuc 	for (;;) {
31050a6a1f1dSLionel Sambuc 		printf("  Extended Capability Register at 0x%02x\n", off);
31060a6a1f1dSLionel Sambuc 
31070a6a1f1dSLionel Sambuc 		foundcap = PCI_EXTCAPLIST_CAP(rval);
31080a6a1f1dSLionel Sambuc 		printf("    type: 0x%04x (", foundcap);
31090a6a1f1dSLionel Sambuc 		if (foundcap < __arraycount(pci_extcaptab)) {
31100a6a1f1dSLionel Sambuc 			printf("%s)\n", pci_extcaptab[foundcap].name);
31110a6a1f1dSLionel Sambuc 			/* Mark as found */
31120a6a1f1dSLionel Sambuc 			foundtable[foundcap] = true;
31130a6a1f1dSLionel Sambuc 		} else
31140a6a1f1dSLionel Sambuc 			printf("unknown)\n");
31150a6a1f1dSLionel Sambuc 		printf("    version: %d\n", PCI_EXTCAPLIST_VERSION(rval));
31160a6a1f1dSLionel Sambuc 
31170a6a1f1dSLionel Sambuc 		off = PCI_EXTCAPLIST_NEXT(rval);
31180a6a1f1dSLionel Sambuc 		if (off == 0)
31190a6a1f1dSLionel Sambuc 			break;
31200a6a1f1dSLionel Sambuc 		rval = regs[o2i(off)];
31210a6a1f1dSLionel Sambuc 	}
31220a6a1f1dSLionel Sambuc 
31230a6a1f1dSLionel Sambuc 	/*
31240a6a1f1dSLionel Sambuc 	 * And then, print the detail of each capability registers
31250a6a1f1dSLionel Sambuc 	 * in capability value's order.
31260a6a1f1dSLionel Sambuc 	 */
31270a6a1f1dSLionel Sambuc 	for (i = 0; i < __arraycount(pci_extcaptab); i++) {
31280a6a1f1dSLionel Sambuc 		if (foundtable[i] == false)
31290a6a1f1dSLionel Sambuc 			continue;
31300a6a1f1dSLionel Sambuc 
31310a6a1f1dSLionel Sambuc 		/*
31320a6a1f1dSLionel Sambuc 		 * The type was found. Search capability list again and
31330a6a1f1dSLionel Sambuc 		 * print all capabilities that the capabiliy type is
31340a6a1f1dSLionel Sambuc 		 * the same.
31350a6a1f1dSLionel Sambuc 		 */
31360a6a1f1dSLionel Sambuc 		if (pci_conf_find_extcap(regs, capoff, i, &off) == 0)
31370a6a1f1dSLionel Sambuc 			continue;
31380a6a1f1dSLionel Sambuc 		rval = regs[o2i(off)];
31390a6a1f1dSLionel Sambuc 		if ((PCI_EXTCAPLIST_VERSION(rval) <= 0)
31400a6a1f1dSLionel Sambuc 		    || (pci_extcaptab[i].printfunc == NULL))
31410a6a1f1dSLionel Sambuc 			continue;
31420a6a1f1dSLionel Sambuc 
31430a6a1f1dSLionel Sambuc 		pci_extcaptab[i].printfunc(regs, capoff, off);
31440a6a1f1dSLionel Sambuc 
31450a6a1f1dSLionel Sambuc 	}
31467eb99bdaSLionel Sambuc }
31477eb99bdaSLionel Sambuc 
31487eb99bdaSLionel Sambuc /* Print the Secondary Status Register. */
31497eb99bdaSLionel Sambuc static void
pci_conf_print_ssr(pcireg_t rval)31507eb99bdaSLionel Sambuc pci_conf_print_ssr(pcireg_t rval)
31517eb99bdaSLionel Sambuc {
31527eb99bdaSLionel Sambuc 	pcireg_t devsel;
31537eb99bdaSLionel Sambuc 
31547eb99bdaSLionel Sambuc 	printf("    Secondary status register: 0x%04x\n", rval); /* XXX bits */
31550a6a1f1dSLionel Sambuc 	onoff("66 MHz capable", rval, __BIT(5));
31560a6a1f1dSLionel Sambuc 	onoff("User Definable Features (UDF) support", rval, __BIT(6));
31570a6a1f1dSLionel Sambuc 	onoff("Fast back-to-back capable", rval, __BIT(7));
31580a6a1f1dSLionel Sambuc 	onoff("Data parity error detected", rval, __BIT(8));
31597eb99bdaSLionel Sambuc 
31607eb99bdaSLionel Sambuc 	printf("      DEVSEL timing: ");
31617eb99bdaSLionel Sambuc 	devsel = __SHIFTOUT(rval, __BITS(10, 9));
31627eb99bdaSLionel Sambuc 	switch (devsel) {
31637eb99bdaSLionel Sambuc 	case 0:
31647eb99bdaSLionel Sambuc 		printf("fast");
31657eb99bdaSLionel Sambuc 		break;
31667eb99bdaSLionel Sambuc 	case 1:
31677eb99bdaSLionel Sambuc 		printf("medium");
31687eb99bdaSLionel Sambuc 		break;
31697eb99bdaSLionel Sambuc 	case 2:
31707eb99bdaSLionel Sambuc 		printf("slow");
31717eb99bdaSLionel Sambuc 		break;
31727eb99bdaSLionel Sambuc 	default:
31737eb99bdaSLionel Sambuc 		printf("unknown/reserved");	/* XXX */
31747eb99bdaSLionel Sambuc 		break;
31757eb99bdaSLionel Sambuc 	}
31767eb99bdaSLionel Sambuc 	printf(" (0x%x)\n", devsel);
31777eb99bdaSLionel Sambuc 
31780a6a1f1dSLionel Sambuc 	onoff("Signalled target abort", rval, __BIT(11));
31790a6a1f1dSLionel Sambuc 	onoff("Received target abort", rval, __BIT(12));
31800a6a1f1dSLionel Sambuc 	onoff("Received master abort", rval, __BIT(13));
31810a6a1f1dSLionel Sambuc 	onoff("Received system error", rval, __BIT(14));
31820a6a1f1dSLionel Sambuc 	onoff("Detected parity error", rval, __BIT(15));
31837eb99bdaSLionel Sambuc }
31847eb99bdaSLionel Sambuc 
31857eb99bdaSLionel Sambuc static void
pci_conf_print_type0(pci_chipset_tag_t pc,pcitag_t tag,const pcireg_t * regs,int sizebars)31860a6a1f1dSLionel Sambuc pci_conf_print_type0(
31877eb99bdaSLionel Sambuc #ifdef _KERNEL
31887eb99bdaSLionel Sambuc     pci_chipset_tag_t pc, pcitag_t tag,
31897eb99bdaSLionel Sambuc #endif
31907eb99bdaSLionel Sambuc     const pcireg_t *regs
31917eb99bdaSLionel Sambuc #ifdef _KERNEL
31927eb99bdaSLionel Sambuc     , int sizebars
31937eb99bdaSLionel Sambuc #endif
31947eb99bdaSLionel Sambuc     )
31957eb99bdaSLionel Sambuc {
31967eb99bdaSLionel Sambuc 	int off, width;
31977eb99bdaSLionel Sambuc 	pcireg_t rval;
31987eb99bdaSLionel Sambuc 
31990a6a1f1dSLionel Sambuc 	for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) {
32007eb99bdaSLionel Sambuc #ifdef _KERNEL
32017eb99bdaSLionel Sambuc 		width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars);
32027eb99bdaSLionel Sambuc #else
32037eb99bdaSLionel Sambuc 		width = pci_conf_print_bar(regs, off, NULL);
32047eb99bdaSLionel Sambuc #endif
32057eb99bdaSLionel Sambuc 	}
32067eb99bdaSLionel Sambuc 
32070a6a1f1dSLionel Sambuc 	printf("    Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]);
32087eb99bdaSLionel Sambuc 
32090a6a1f1dSLionel Sambuc 	rval = regs[o2i(PCI_SUBSYS_ID_REG)];
32100a6a1f1dSLionel Sambuc 	printf("    Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
32110a6a1f1dSLionel Sambuc 	printf("    Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
32127eb99bdaSLionel Sambuc 
32130a6a1f1dSLionel Sambuc 	/* XXX */
32140a6a1f1dSLionel Sambuc 	printf("    Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]);
32157eb99bdaSLionel Sambuc 
32167eb99bdaSLionel Sambuc 	if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
32177eb99bdaSLionel Sambuc 		printf("    Capability list pointer: 0x%02x\n",
32187eb99bdaSLionel Sambuc 		    PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]));
32197eb99bdaSLionel Sambuc 	else
32207eb99bdaSLionel Sambuc 		printf("    Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
32217eb99bdaSLionel Sambuc 
32220a6a1f1dSLionel Sambuc 	printf("    Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]);
32237eb99bdaSLionel Sambuc 
32240a6a1f1dSLionel Sambuc 	rval = regs[o2i(PCI_INTERRUPT_REG)];
32250a6a1f1dSLionel Sambuc 	printf("    Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff);
32260a6a1f1dSLionel Sambuc 	printf("    Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff);
32270a6a1f1dSLionel Sambuc 	printf("    Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval));
32280a6a1f1dSLionel Sambuc 	switch (PCI_INTERRUPT_PIN(rval)) {
32297eb99bdaSLionel Sambuc 	case PCI_INTERRUPT_PIN_NONE:
32307eb99bdaSLionel Sambuc 		printf("(none)");
32317eb99bdaSLionel Sambuc 		break;
32327eb99bdaSLionel Sambuc 	case PCI_INTERRUPT_PIN_A:
32337eb99bdaSLionel Sambuc 		printf("(pin A)");
32347eb99bdaSLionel Sambuc 		break;
32357eb99bdaSLionel Sambuc 	case PCI_INTERRUPT_PIN_B:
32367eb99bdaSLionel Sambuc 		printf("(pin B)");
32377eb99bdaSLionel Sambuc 		break;
32387eb99bdaSLionel Sambuc 	case PCI_INTERRUPT_PIN_C:
32397eb99bdaSLionel Sambuc 		printf("(pin C)");
32407eb99bdaSLionel Sambuc 		break;
32417eb99bdaSLionel Sambuc 	case PCI_INTERRUPT_PIN_D:
32427eb99bdaSLionel Sambuc 		printf("(pin D)");
32437eb99bdaSLionel Sambuc 		break;
32447eb99bdaSLionel Sambuc 	default:
32457eb99bdaSLionel Sambuc 		printf("(? ? ?)");
32467eb99bdaSLionel Sambuc 		break;
32477eb99bdaSLionel Sambuc 	}
32487eb99bdaSLionel Sambuc 	printf("\n");
32490a6a1f1dSLionel Sambuc 	printf("    Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval));
32500a6a1f1dSLionel Sambuc }
32510a6a1f1dSLionel Sambuc 
32520a6a1f1dSLionel Sambuc static void
pci_conf_print_type1(pci_chipset_tag_t pc,pcitag_t tag,const pcireg_t * regs,int sizebars)32530a6a1f1dSLionel Sambuc pci_conf_print_type1(
32540a6a1f1dSLionel Sambuc #ifdef _KERNEL
32550a6a1f1dSLionel Sambuc     pci_chipset_tag_t pc, pcitag_t tag,
32560a6a1f1dSLionel Sambuc #endif
32570a6a1f1dSLionel Sambuc     const pcireg_t *regs
32580a6a1f1dSLionel Sambuc #ifdef _KERNEL
32590a6a1f1dSLionel Sambuc     , int sizebars
32600a6a1f1dSLionel Sambuc #endif
32610a6a1f1dSLionel Sambuc     )
32620a6a1f1dSLionel Sambuc {
32630a6a1f1dSLionel Sambuc 	int off, width;
32640a6a1f1dSLionel Sambuc 	pcireg_t rval;
32650a6a1f1dSLionel Sambuc 	uint32_t base, limit;
32660a6a1f1dSLionel Sambuc 	uint32_t base_h, limit_h;
32670a6a1f1dSLionel Sambuc 	uint64_t pbase, plimit;
32680a6a1f1dSLionel Sambuc 	int use_upper;
32690a6a1f1dSLionel Sambuc 
32700a6a1f1dSLionel Sambuc 	/*
32710a6a1f1dSLionel Sambuc 	 * This layout was cribbed from the TI PCI2030 PCI-to-PCI
32720a6a1f1dSLionel Sambuc 	 * Bridge chip documentation, and may not be correct with
32730a6a1f1dSLionel Sambuc 	 * respect to various standards. (XXX)
32740a6a1f1dSLionel Sambuc 	 */
32750a6a1f1dSLionel Sambuc 
32760a6a1f1dSLionel Sambuc 	for (off = 0x10; off < 0x18; off += width) {
32770a6a1f1dSLionel Sambuc #ifdef _KERNEL
32780a6a1f1dSLionel Sambuc 		width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars);
32790a6a1f1dSLionel Sambuc #else
32800a6a1f1dSLionel Sambuc 		width = pci_conf_print_bar(regs, off, NULL);
32810a6a1f1dSLionel Sambuc #endif
32820a6a1f1dSLionel Sambuc 	}
32830a6a1f1dSLionel Sambuc 
32840a6a1f1dSLionel Sambuc 	rval = regs[o2i(PCI_BRIDGE_BUS_REG)];
32850a6a1f1dSLionel Sambuc 	printf("    Primary bus number: 0x%02x\n",
32860a6a1f1dSLionel Sambuc 	    PCI_BRIDGE_BUS_PRIMARY(rval));
32870a6a1f1dSLionel Sambuc 	printf("    Secondary bus number: 0x%02x\n",
32880a6a1f1dSLionel Sambuc 	    PCI_BRIDGE_BUS_SECONDARY(rval));
32890a6a1f1dSLionel Sambuc 	printf("    Subordinate bus number: 0x%02x\n",
32900a6a1f1dSLionel Sambuc 	    PCI_BRIDGE_BUS_SUBORDINATE(rval));
32910a6a1f1dSLionel Sambuc 	printf("    Secondary bus latency timer: 0x%02x\n",
32920a6a1f1dSLionel Sambuc 	    PCI_BRIDGE_BUS_SEC_LATTIMER(rval));
32930a6a1f1dSLionel Sambuc 
32940a6a1f1dSLionel Sambuc 	rval = regs[o2i(PCI_BRIDGE_STATIO_REG)];
32950a6a1f1dSLionel Sambuc 	pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16)));
32960a6a1f1dSLionel Sambuc 
32970a6a1f1dSLionel Sambuc 	/* I/O region */
32980a6a1f1dSLionel Sambuc 	printf("    I/O region:\n");
32990a6a1f1dSLionel Sambuc 	printf("      base register:  0x%02x\n", (rval >> 0) & 0xff);
33000a6a1f1dSLionel Sambuc 	printf("      limit register: 0x%02x\n", (rval >> 8) & 0xff);
33010a6a1f1dSLionel Sambuc 	if (PCI_BRIDGE_IO_32BITS(rval))
33020a6a1f1dSLionel Sambuc 		use_upper = 1;
33030a6a1f1dSLionel Sambuc 	else
33040a6a1f1dSLionel Sambuc 		use_upper = 0;
33050a6a1f1dSLionel Sambuc 	onoff("32bit I/O", rval, use_upper);
33060a6a1f1dSLionel Sambuc 	base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8;
33070a6a1f1dSLionel Sambuc 	limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT)
33080a6a1f1dSLionel Sambuc 	    & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8;
33090a6a1f1dSLionel Sambuc 	limit |= 0x00000fff;
33100a6a1f1dSLionel Sambuc 
33110a6a1f1dSLionel Sambuc 	rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)];
33120a6a1f1dSLionel Sambuc 	base_h = (rval >> 0) & 0xffff;
33130a6a1f1dSLionel Sambuc 	limit_h = (rval >> 16) & 0xffff;
33140a6a1f1dSLionel Sambuc 	printf("      base upper 16 bits register:  0x%04x\n", base_h);
33150a6a1f1dSLionel Sambuc 	printf("      limit upper 16 bits register: 0x%04x\n", limit_h);
33160a6a1f1dSLionel Sambuc 
33170a6a1f1dSLionel Sambuc 	if (use_upper == 1) {
33180a6a1f1dSLionel Sambuc 		base |= base_h << 16;
33190a6a1f1dSLionel Sambuc 		limit |= limit_h << 16;
33200a6a1f1dSLionel Sambuc 	}
33210a6a1f1dSLionel Sambuc 	if (base < limit) {
33220a6a1f1dSLionel Sambuc 		if (use_upper == 1)
33230a6a1f1dSLionel Sambuc 			printf("      range:  0x%08x-0x%08x\n", base, limit);
33240a6a1f1dSLionel Sambuc 		else
33250a6a1f1dSLionel Sambuc 			printf("      range:  0x%04x-0x%04x\n", base, limit);
33260a6a1f1dSLionel Sambuc 	} else
33270a6a1f1dSLionel Sambuc 		printf("      range:  not set\n");
33280a6a1f1dSLionel Sambuc 
33290a6a1f1dSLionel Sambuc 	/* Non-prefetchable memory region */
33300a6a1f1dSLionel Sambuc 	rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)];
33310a6a1f1dSLionel Sambuc 	printf("    Memory region:\n");
33320a6a1f1dSLionel Sambuc 	printf("      base register:  0x%04x\n",
33330a6a1f1dSLionel Sambuc 	    (rval >> 0) & 0xffff);
33340a6a1f1dSLionel Sambuc 	printf("      limit register: 0x%04x\n",
33350a6a1f1dSLionel Sambuc 	    (rval >> 16) & 0xffff);
33360a6a1f1dSLionel Sambuc 	base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT)
33370a6a1f1dSLionel Sambuc 	    & PCI_BRIDGE_MEMORY_BASE_MASK) << 20;
33380a6a1f1dSLionel Sambuc 	limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT)
33390a6a1f1dSLionel Sambuc 		& PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff;
33400a6a1f1dSLionel Sambuc 	if (base < limit)
33410a6a1f1dSLionel Sambuc 		printf("      range:  0x%08x-0x%08x\n", base, limit);
33420a6a1f1dSLionel Sambuc 	else
33430a6a1f1dSLionel Sambuc 		printf("      range:  not set\n");
33440a6a1f1dSLionel Sambuc 
33450a6a1f1dSLionel Sambuc 	/* Prefetchable memory region */
33460a6a1f1dSLionel Sambuc 	rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)];
33470a6a1f1dSLionel Sambuc 	printf("    Prefetchable memory region:\n");
33480a6a1f1dSLionel Sambuc 	printf("      base register:  0x%04x\n",
33490a6a1f1dSLionel Sambuc 	    (rval >> 0) & 0xffff);
33500a6a1f1dSLionel Sambuc 	printf("      limit register: 0x%04x\n",
33510a6a1f1dSLionel Sambuc 	    (rval >> 16) & 0xffff);
33520a6a1f1dSLionel Sambuc 	base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)];
33530a6a1f1dSLionel Sambuc 	limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)];
33540a6a1f1dSLionel Sambuc 	printf("      base upper 32 bits register:  0x%08x\n",
33550a6a1f1dSLionel Sambuc 	    base_h);
33560a6a1f1dSLionel Sambuc 	printf("      limit upper 32 bits register: 0x%08x\n",
33570a6a1f1dSLionel Sambuc 	    limit_h);
33580a6a1f1dSLionel Sambuc 	if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval))
33590a6a1f1dSLionel Sambuc 		use_upper = 1;
33600a6a1f1dSLionel Sambuc 	else
33610a6a1f1dSLionel Sambuc 		use_upper = 0;
33620a6a1f1dSLionel Sambuc 	onoff("64bit memory address", rval, use_upper);
33630a6a1f1dSLionel Sambuc 	pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT)
33640a6a1f1dSLionel Sambuc 	    & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20;
33650a6a1f1dSLionel Sambuc 	plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT)
33660a6a1f1dSLionel Sambuc 		& PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff;
33670a6a1f1dSLionel Sambuc 	if (use_upper == 1) {
33680a6a1f1dSLionel Sambuc 		pbase |= (uint64_t)base_h << 32;
33690a6a1f1dSLionel Sambuc 		plimit |= (uint64_t)limit_h << 32;
33700a6a1f1dSLionel Sambuc 	}
33710a6a1f1dSLionel Sambuc 	if (pbase < plimit) {
33720a6a1f1dSLionel Sambuc 		if (use_upper == 1)
33730a6a1f1dSLionel Sambuc 			printf("      range:  0x%016" PRIx64 "-0x%016" PRIx64
33740a6a1f1dSLionel Sambuc 			    "\n", pbase, plimit);
33750a6a1f1dSLionel Sambuc 		else
33760a6a1f1dSLionel Sambuc 			printf("      range:  0x%08x-0x%08x\n",
33770a6a1f1dSLionel Sambuc 			    (uint32_t)pbase, (uint32_t)plimit);
33780a6a1f1dSLionel Sambuc 	} else
33790a6a1f1dSLionel Sambuc 		printf("      range:  not set\n");
33800a6a1f1dSLionel Sambuc 
33810a6a1f1dSLionel Sambuc 	if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
33820a6a1f1dSLionel Sambuc 		printf("    Capability list pointer: 0x%02x\n",
33830a6a1f1dSLionel Sambuc 		    PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]));
33840a6a1f1dSLionel Sambuc 	else
33850a6a1f1dSLionel Sambuc 		printf("    Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
33860a6a1f1dSLionel Sambuc 
33870a6a1f1dSLionel Sambuc 	/* XXX */
33880a6a1f1dSLionel Sambuc 	printf("    Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]);
33890a6a1f1dSLionel Sambuc 
33900a6a1f1dSLionel Sambuc 	rval = regs[o2i(PCI_INTERRUPT_REG)];
33910a6a1f1dSLionel Sambuc 	printf("    Interrupt line: 0x%02x\n",
33920a6a1f1dSLionel Sambuc 	    (rval >> 0) & 0xff);
33930a6a1f1dSLionel Sambuc 	printf("    Interrupt pin: 0x%02x ",
33940a6a1f1dSLionel Sambuc 	    (rval >> 8) & 0xff);
33950a6a1f1dSLionel Sambuc 	switch ((rval >> 8) & 0xff) {
33960a6a1f1dSLionel Sambuc 	case PCI_INTERRUPT_PIN_NONE:
33970a6a1f1dSLionel Sambuc 		printf("(none)");
33980a6a1f1dSLionel Sambuc 		break;
33990a6a1f1dSLionel Sambuc 	case PCI_INTERRUPT_PIN_A:
34000a6a1f1dSLionel Sambuc 		printf("(pin A)");
34010a6a1f1dSLionel Sambuc 		break;
34020a6a1f1dSLionel Sambuc 	case PCI_INTERRUPT_PIN_B:
34030a6a1f1dSLionel Sambuc 		printf("(pin B)");
34040a6a1f1dSLionel Sambuc 		break;
34050a6a1f1dSLionel Sambuc 	case PCI_INTERRUPT_PIN_C:
34060a6a1f1dSLionel Sambuc 		printf("(pin C)");
34070a6a1f1dSLionel Sambuc 		break;
34080a6a1f1dSLionel Sambuc 	case PCI_INTERRUPT_PIN_D:
34090a6a1f1dSLionel Sambuc 		printf("(pin D)");
34100a6a1f1dSLionel Sambuc 		break;
34110a6a1f1dSLionel Sambuc 	default:
34120a6a1f1dSLionel Sambuc 		printf("(? ? ?)");
34130a6a1f1dSLionel Sambuc 		break;
34140a6a1f1dSLionel Sambuc 	}
34150a6a1f1dSLionel Sambuc 	printf("\n");
34160a6a1f1dSLionel Sambuc 	rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT)
34170a6a1f1dSLionel Sambuc 	    & PCI_BRIDGE_CONTROL_MASK;
34187eb99bdaSLionel Sambuc 	printf("    Bridge control register: 0x%04x\n", rval); /* XXX bits */
34190a6a1f1dSLionel Sambuc 	onoff("Parity error response", rval, 0x0001);
34200a6a1f1dSLionel Sambuc 	onoff("Secondary SERR forwarding", rval, 0x0002);
34210a6a1f1dSLionel Sambuc 	onoff("ISA enable", rval, 0x0004);
34220a6a1f1dSLionel Sambuc 	onoff("VGA enable", rval, 0x0008);
34230a6a1f1dSLionel Sambuc 	onoff("Master abort reporting", rval, 0x0020);
34240a6a1f1dSLionel Sambuc 	onoff("Secondary bus reset", rval, 0x0040);
34250a6a1f1dSLionel Sambuc 	onoff("Fast back-to-back capable", rval, 0x0080);
34267eb99bdaSLionel Sambuc }
34277eb99bdaSLionel Sambuc 
34287eb99bdaSLionel Sambuc static void
pci_conf_print_type2(pci_chipset_tag_t pc,pcitag_t tag,const pcireg_t * regs,int sizebars)34297eb99bdaSLionel Sambuc pci_conf_print_type2(
34307eb99bdaSLionel Sambuc #ifdef _KERNEL
34317eb99bdaSLionel Sambuc     pci_chipset_tag_t pc, pcitag_t tag,
34327eb99bdaSLionel Sambuc #endif
34337eb99bdaSLionel Sambuc     const pcireg_t *regs
34347eb99bdaSLionel Sambuc #ifdef _KERNEL
34357eb99bdaSLionel Sambuc     , int sizebars
34367eb99bdaSLionel Sambuc #endif
34377eb99bdaSLionel Sambuc     )
34387eb99bdaSLionel Sambuc {
34397eb99bdaSLionel Sambuc 	pcireg_t rval;
34407eb99bdaSLionel Sambuc 
34417eb99bdaSLionel Sambuc 	/*
34427eb99bdaSLionel Sambuc 	 * XXX these need to be printed in more detail, need to be
34437eb99bdaSLionel Sambuc 	 * XXX checked against specs/docs, etc.
34447eb99bdaSLionel Sambuc 	 *
34457eb99bdaSLionel Sambuc 	 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus
34467eb99bdaSLionel Sambuc 	 * controller chip documentation, and may not be correct with
34477eb99bdaSLionel Sambuc 	 * respect to various standards. (XXX)
34487eb99bdaSLionel Sambuc 	 */
34497eb99bdaSLionel Sambuc 
34507eb99bdaSLionel Sambuc #ifdef _KERNEL
34517eb99bdaSLionel Sambuc 	pci_conf_print_bar(pc, tag, regs, 0x10,
34527eb99bdaSLionel Sambuc 	    "CardBus socket/ExCA registers", sizebars);
34537eb99bdaSLionel Sambuc #else
34547eb99bdaSLionel Sambuc 	pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers");
34557eb99bdaSLionel Sambuc #endif
34567eb99bdaSLionel Sambuc 
34570a6a1f1dSLionel Sambuc 	/* Capability list pointer and secondary status register */
34580a6a1f1dSLionel Sambuc 	rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)];
34597eb99bdaSLionel Sambuc 	if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
34607eb99bdaSLionel Sambuc 		printf("    Capability list pointer: 0x%02x\n",
34610a6a1f1dSLionel Sambuc 		    PCI_CAPLIST_PTR(rval));
34627eb99bdaSLionel Sambuc 	else
34630a6a1f1dSLionel Sambuc 		printf("    Reserved @ 0x14: 0x%04x\n",
34640a6a1f1dSLionel Sambuc 		       (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0)));
34650a6a1f1dSLionel Sambuc 	pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16)));
34667eb99bdaSLionel Sambuc 
34670a6a1f1dSLionel Sambuc 	rval = regs[o2i(PCI_BRIDGE_BUS_REG)];
34687eb99bdaSLionel Sambuc 	printf("    PCI bus number: 0x%02x\n",
34690a6a1f1dSLionel Sambuc 	    (rval >> 0) & 0xff);
34707eb99bdaSLionel Sambuc 	printf("    CardBus bus number: 0x%02x\n",
34710a6a1f1dSLionel Sambuc 	    (rval >> 8) & 0xff);
34727eb99bdaSLionel Sambuc 	printf("    Subordinate bus number: 0x%02x\n",
34730a6a1f1dSLionel Sambuc 	    (rval >> 16) & 0xff);
34747eb99bdaSLionel Sambuc 	printf("    CardBus latency timer: 0x%02x\n",
34750a6a1f1dSLionel Sambuc 	    (rval >> 24) & 0xff);
34767eb99bdaSLionel Sambuc 
34777eb99bdaSLionel Sambuc 	/* XXX Print more prettily */
34787eb99bdaSLionel Sambuc 	printf("    CardBus memory region 0:\n");
34797eb99bdaSLionel Sambuc 	printf("      base register:  0x%08x\n", regs[o2i(0x1c)]);
34807eb99bdaSLionel Sambuc 	printf("      limit register: 0x%08x\n", regs[o2i(0x20)]);
34817eb99bdaSLionel Sambuc 	printf("    CardBus memory region 1:\n");
34827eb99bdaSLionel Sambuc 	printf("      base register:  0x%08x\n", regs[o2i(0x24)]);
34837eb99bdaSLionel Sambuc 	printf("      limit register: 0x%08x\n", regs[o2i(0x28)]);
34847eb99bdaSLionel Sambuc 	printf("    CardBus I/O region 0:\n");
34857eb99bdaSLionel Sambuc 	printf("      base register:  0x%08x\n", regs[o2i(0x2c)]);
34867eb99bdaSLionel Sambuc 	printf("      limit register: 0x%08x\n", regs[o2i(0x30)]);
34877eb99bdaSLionel Sambuc 	printf("    CardBus I/O region 1:\n");
34887eb99bdaSLionel Sambuc 	printf("      base register:  0x%08x\n", regs[o2i(0x34)]);
34897eb99bdaSLionel Sambuc 	printf("      limit register: 0x%08x\n", regs[o2i(0x38)]);
34907eb99bdaSLionel Sambuc 
34910a6a1f1dSLionel Sambuc 	rval = regs[o2i(PCI_INTERRUPT_REG)];
34927eb99bdaSLionel Sambuc 	printf("    Interrupt line: 0x%02x\n",
34930a6a1f1dSLionel Sambuc 	    (rval >> 0) & 0xff);
34947eb99bdaSLionel Sambuc 	printf("    Interrupt pin: 0x%02x ",
34950a6a1f1dSLionel Sambuc 	    (rval >> 8) & 0xff);
34960a6a1f1dSLionel Sambuc 	switch ((rval >> 8) & 0xff) {
34977eb99bdaSLionel Sambuc 	case PCI_INTERRUPT_PIN_NONE:
34987eb99bdaSLionel Sambuc 		printf("(none)");
34997eb99bdaSLionel Sambuc 		break;
35007eb99bdaSLionel Sambuc 	case PCI_INTERRUPT_PIN_A:
35017eb99bdaSLionel Sambuc 		printf("(pin A)");
35027eb99bdaSLionel Sambuc 		break;
35037eb99bdaSLionel Sambuc 	case PCI_INTERRUPT_PIN_B:
35047eb99bdaSLionel Sambuc 		printf("(pin B)");
35057eb99bdaSLionel Sambuc 		break;
35067eb99bdaSLionel Sambuc 	case PCI_INTERRUPT_PIN_C:
35077eb99bdaSLionel Sambuc 		printf("(pin C)");
35087eb99bdaSLionel Sambuc 		break;
35097eb99bdaSLionel Sambuc 	case PCI_INTERRUPT_PIN_D:
35107eb99bdaSLionel Sambuc 		printf("(pin D)");
35117eb99bdaSLionel Sambuc 		break;
35127eb99bdaSLionel Sambuc 	default:
35137eb99bdaSLionel Sambuc 		printf("(? ? ?)");
35147eb99bdaSLionel Sambuc 		break;
35157eb99bdaSLionel Sambuc 	}
35167eb99bdaSLionel Sambuc 	printf("\n");
35177eb99bdaSLionel Sambuc 	rval = (regs[o2i(0x3c)] >> 16) & 0xffff;
35187eb99bdaSLionel Sambuc 	printf("    Bridge control register: 0x%04x\n", rval);
35190a6a1f1dSLionel Sambuc 	onoff("Parity error response", rval, __BIT(0));
35200a6a1f1dSLionel Sambuc 	onoff("SERR# enable", rval, __BIT(1));
35210a6a1f1dSLionel Sambuc 	onoff("ISA enable", rval, __BIT(2));
35220a6a1f1dSLionel Sambuc 	onoff("VGA enable", rval, __BIT(3));
35230a6a1f1dSLionel Sambuc 	onoff("Master abort mode", rval, __BIT(5));
35240a6a1f1dSLionel Sambuc 	onoff("Secondary (CardBus) bus reset", rval, __BIT(6));
35250a6a1f1dSLionel Sambuc 	onoff("Functional interrupts routed by ExCA registers", rval,
35260a6a1f1dSLionel Sambuc 	    __BIT(7));
35270a6a1f1dSLionel Sambuc 	onoff("Memory window 0 prefetchable", rval, __BIT(8));
35280a6a1f1dSLionel Sambuc 	onoff("Memory window 1 prefetchable", rval, __BIT(9));
35290a6a1f1dSLionel Sambuc 	onoff("Write posting enable", rval, __BIT(10));
35307eb99bdaSLionel Sambuc 
35317eb99bdaSLionel Sambuc 	rval = regs[o2i(0x40)];
35327eb99bdaSLionel Sambuc 	printf("    Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
35337eb99bdaSLionel Sambuc 	printf("    Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
35347eb99bdaSLionel Sambuc 
35357eb99bdaSLionel Sambuc #ifdef _KERNEL
35367eb99bdaSLionel Sambuc 	pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers",
35377eb99bdaSLionel Sambuc 	    sizebars);
35387eb99bdaSLionel Sambuc #else
35397eb99bdaSLionel Sambuc 	pci_conf_print_bar(regs, 0x44, "legacy-mode registers");
35407eb99bdaSLionel Sambuc #endif
35417eb99bdaSLionel Sambuc }
35427eb99bdaSLionel Sambuc 
35437eb99bdaSLionel Sambuc void
pci_conf_print(pci_chipset_tag_t pc,pcitag_t tag,void (* printfn)(pci_chipset_tag_t,pcitag_t,const pcireg_t *))35447eb99bdaSLionel Sambuc pci_conf_print(
35457eb99bdaSLionel Sambuc #ifdef _KERNEL
35467eb99bdaSLionel Sambuc     pci_chipset_tag_t pc, pcitag_t tag,
35477eb99bdaSLionel Sambuc     void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *)
35487eb99bdaSLionel Sambuc #else
35497eb99bdaSLionel Sambuc     int pcifd, u_int bus, u_int dev, u_int func
35507eb99bdaSLionel Sambuc #endif
35517eb99bdaSLionel Sambuc     )
35527eb99bdaSLionel Sambuc {
35530a6a1f1dSLionel Sambuc 	pcireg_t regs[o2i(PCI_EXTCONF_SIZE)];
35547eb99bdaSLionel Sambuc 	int off, capoff, endoff, hdrtype;
35550a6a1f1dSLionel Sambuc 	const char *type_name;
35567eb99bdaSLionel Sambuc #ifdef _KERNEL
35570a6a1f1dSLionel Sambuc 	void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *,
35580a6a1f1dSLionel Sambuc 	    int);
35597eb99bdaSLionel Sambuc 	int sizebars;
35607eb99bdaSLionel Sambuc #else
35610a6a1f1dSLionel Sambuc 	void (*type_printfn)(const pcireg_t *);
35627eb99bdaSLionel Sambuc #endif
35637eb99bdaSLionel Sambuc 
35647eb99bdaSLionel Sambuc 	printf("PCI configuration registers:\n");
35657eb99bdaSLionel Sambuc 
35660a6a1f1dSLionel Sambuc 	for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) {
35677eb99bdaSLionel Sambuc #ifdef _KERNEL
35687eb99bdaSLionel Sambuc 		regs[o2i(off)] = pci_conf_read(pc, tag, off);
35697eb99bdaSLionel Sambuc #else
35707eb99bdaSLionel Sambuc 		if (pcibus_conf_read(pcifd, bus, dev, func, off,
35717eb99bdaSLionel Sambuc 		    &regs[o2i(off)]) == -1)
35727eb99bdaSLionel Sambuc 			regs[o2i(off)] = 0;
35737eb99bdaSLionel Sambuc #endif
35747eb99bdaSLionel Sambuc 	}
35757eb99bdaSLionel Sambuc 
35767eb99bdaSLionel Sambuc #ifdef _KERNEL
35777eb99bdaSLionel Sambuc 	sizebars = 1;
35787eb99bdaSLionel Sambuc 	if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE &&
35797eb99bdaSLionel Sambuc 	    PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST)
35807eb99bdaSLionel Sambuc 		sizebars = 0;
35817eb99bdaSLionel Sambuc #endif
35827eb99bdaSLionel Sambuc 
35837eb99bdaSLionel Sambuc 	/* common header */
35847eb99bdaSLionel Sambuc 	printf("  Common header:\n");
35857eb99bdaSLionel Sambuc 	pci_conf_print_regs(regs, 0, 16);
35867eb99bdaSLionel Sambuc 
35877eb99bdaSLionel Sambuc 	printf("\n");
35887eb99bdaSLionel Sambuc #ifdef _KERNEL
35897eb99bdaSLionel Sambuc 	pci_conf_print_common(pc, tag, regs);
35907eb99bdaSLionel Sambuc #else
35917eb99bdaSLionel Sambuc 	pci_conf_print_common(regs);
35927eb99bdaSLionel Sambuc #endif
35937eb99bdaSLionel Sambuc 	printf("\n");
35947eb99bdaSLionel Sambuc 
35957eb99bdaSLionel Sambuc 	/* type-dependent header */
35967eb99bdaSLionel Sambuc 	hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]);
35977eb99bdaSLionel Sambuc 	switch (hdrtype) {		/* XXX make a table, eventually */
35987eb99bdaSLionel Sambuc 	case 0:
35997eb99bdaSLionel Sambuc 		/* Standard device header */
36000a6a1f1dSLionel Sambuc 		type_name = "\"normal\" device";
36010a6a1f1dSLionel Sambuc 		type_printfn = &pci_conf_print_type0;
36027eb99bdaSLionel Sambuc 		capoff = PCI_CAPLISTPTR_REG;
36037eb99bdaSLionel Sambuc 		endoff = 64;
36047eb99bdaSLionel Sambuc 		break;
36057eb99bdaSLionel Sambuc 	case 1:
36067eb99bdaSLionel Sambuc 		/* PCI-PCI bridge header */
36070a6a1f1dSLionel Sambuc 		type_name = "PCI-PCI bridge";
36080a6a1f1dSLionel Sambuc 		type_printfn = &pci_conf_print_type1;
36097eb99bdaSLionel Sambuc 		capoff = PCI_CAPLISTPTR_REG;
36107eb99bdaSLionel Sambuc 		endoff = 64;
36117eb99bdaSLionel Sambuc 		break;
36127eb99bdaSLionel Sambuc 	case 2:
36137eb99bdaSLionel Sambuc 		/* PCI-CardBus bridge header */
36140a6a1f1dSLionel Sambuc 		type_name = "PCI-CardBus bridge";
36150a6a1f1dSLionel Sambuc 		type_printfn = &pci_conf_print_type2;
36167eb99bdaSLionel Sambuc 		capoff = PCI_CARDBUS_CAPLISTPTR_REG;
36177eb99bdaSLionel Sambuc 		endoff = 72;
36187eb99bdaSLionel Sambuc 		break;
36197eb99bdaSLionel Sambuc 	default:
36200a6a1f1dSLionel Sambuc 		type_name = NULL;
36210a6a1f1dSLionel Sambuc 		type_printfn = 0;
36227eb99bdaSLionel Sambuc 		capoff = -1;
36237eb99bdaSLionel Sambuc 		endoff = 64;
36247eb99bdaSLionel Sambuc 		break;
36257eb99bdaSLionel Sambuc 	}
36267eb99bdaSLionel Sambuc 	printf("  Type %d ", hdrtype);
36270a6a1f1dSLionel Sambuc 	if (type_name != NULL)
36280a6a1f1dSLionel Sambuc 		printf("(%s) ", type_name);
36297eb99bdaSLionel Sambuc 	printf("header:\n");
36307eb99bdaSLionel Sambuc 	pci_conf_print_regs(regs, 16, endoff);
36317eb99bdaSLionel Sambuc 	printf("\n");
36320a6a1f1dSLionel Sambuc 	if (type_printfn) {
36337eb99bdaSLionel Sambuc #ifdef _KERNEL
36340a6a1f1dSLionel Sambuc 		(*type_printfn)(pc, tag, regs, sizebars);
36357eb99bdaSLionel Sambuc #else
36360a6a1f1dSLionel Sambuc 		(*type_printfn)(regs);
36377eb99bdaSLionel Sambuc #endif
36387eb99bdaSLionel Sambuc 	} else
36397eb99bdaSLionel Sambuc 		printf("    Don't know how to pretty-print type %d header.\n",
36407eb99bdaSLionel Sambuc 		    hdrtype);
36417eb99bdaSLionel Sambuc 	printf("\n");
36427eb99bdaSLionel Sambuc 
36437eb99bdaSLionel Sambuc 	/* capability list, if present */
36447eb99bdaSLionel Sambuc 	if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
36457eb99bdaSLionel Sambuc 		&& (capoff > 0)) {
36467eb99bdaSLionel Sambuc #ifdef _KERNEL
36477eb99bdaSLionel Sambuc 		pci_conf_print_caplist(pc, tag, regs, capoff);
36487eb99bdaSLionel Sambuc #else
36497eb99bdaSLionel Sambuc 		pci_conf_print_caplist(regs, capoff);
36507eb99bdaSLionel Sambuc #endif
36517eb99bdaSLionel Sambuc 		printf("\n");
36527eb99bdaSLionel Sambuc 	}
36537eb99bdaSLionel Sambuc 
36547eb99bdaSLionel Sambuc 	/* device-dependent header */
36557eb99bdaSLionel Sambuc 	printf("  Device-dependent header:\n");
36560a6a1f1dSLionel Sambuc 	pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE);
36577eb99bdaSLionel Sambuc 	printf("\n");
36587eb99bdaSLionel Sambuc #ifdef _KERNEL
36597eb99bdaSLionel Sambuc 	if (printfn)
36607eb99bdaSLionel Sambuc 		(*printfn)(pc, tag, regs);
36617eb99bdaSLionel Sambuc 	else
36627eb99bdaSLionel Sambuc 		printf("    Don't know how to pretty-print device-dependent header.\n");
36637eb99bdaSLionel Sambuc 	printf("\n");
36647eb99bdaSLionel Sambuc #endif /* _KERNEL */
36650a6a1f1dSLionel Sambuc 
36660a6a1f1dSLionel Sambuc 	if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff ||
36670a6a1f1dSLionel Sambuc 	    regs[o2i(PCI_EXTCAPLIST_BASE)] == 0)
36680a6a1f1dSLionel Sambuc 		return;
36690a6a1f1dSLionel Sambuc 
36700a6a1f1dSLionel Sambuc #ifdef _KERNEL
36710a6a1f1dSLionel Sambuc 	pci_conf_print_extcaplist(pc, tag, regs, capoff);
36720a6a1f1dSLionel Sambuc #else
36730a6a1f1dSLionel Sambuc 	pci_conf_print_extcaplist(regs, capoff);
36740a6a1f1dSLionel Sambuc #endif
36750a6a1f1dSLionel Sambuc 	printf("\n");
36760a6a1f1dSLionel Sambuc 
36770a6a1f1dSLionel Sambuc 	/* Extended Configuration Space, if present */
36780a6a1f1dSLionel Sambuc 	printf("  Extended Configuration Space:\n");
36790a6a1f1dSLionel Sambuc 	pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE);
36807eb99bdaSLionel Sambuc }
36810a6a1f1dSLionel Sambuc #endif /* defined(__minix) && !defined(_PCI_SERVER) */
3682