xref: /minix3/sys/arch/i386/stand/lib/netif/lance.h (revision 58a2b0008e28f606a7f7f5faaeaba4faac57a1ea)
1*58a2b000SEvgeniy Ivanov /*	$NetBSD: lance.h,v 1.2 2008/12/14 18:46:33 christos Exp $	*/
2*58a2b000SEvgeniy Ivanov 
3*58a2b000SEvgeniy Ivanov /*
4*58a2b000SEvgeniy Ivanov  * source in this file came from
5*58a2b000SEvgeniy Ivanov  * the Mach ethernet boot written by Leendert van Doorn.
6*58a2b000SEvgeniy Ivanov  */
7*58a2b000SEvgeniy Ivanov 
8*58a2b000SEvgeniy Ivanov /* RAP functions as a select for RDP */
9*58a2b000SEvgeniy Ivanov #define RDP_CSR0	0
10*58a2b000SEvgeniy Ivanov #define RDP_CSR1	1
11*58a2b000SEvgeniy Ivanov #define RDP_CSR2	2
12*58a2b000SEvgeniy Ivanov #define RDP_CSR3	3
13*58a2b000SEvgeniy Ivanov 
14*58a2b000SEvgeniy Ivanov /* contents of csr0 */
15*58a2b000SEvgeniy Ivanov #define CSR_ERR		0x8000
16*58a2b000SEvgeniy Ivanov #define CSR_BABL	0x4000
17*58a2b000SEvgeniy Ivanov #define CSR_CERR	0x2000
18*58a2b000SEvgeniy Ivanov #define CSR_MISS	0x1000
19*58a2b000SEvgeniy Ivanov #define CSR_MERR	0x0800
20*58a2b000SEvgeniy Ivanov #define CSR_RINT	0x0400
21*58a2b000SEvgeniy Ivanov #define CSR_TINT	0x0200
22*58a2b000SEvgeniy Ivanov #define CSR_IDON	0x0100
23*58a2b000SEvgeniy Ivanov #define CSR_INTR	0x0080
24*58a2b000SEvgeniy Ivanov #define CSR_INEA	0x0040
25*58a2b000SEvgeniy Ivanov #define CSR_RXON	0x0020
26*58a2b000SEvgeniy Ivanov #define CSR_TXON	0x0010
27*58a2b000SEvgeniy Ivanov #define CSR_TDMD	0x0008
28*58a2b000SEvgeniy Ivanov #define CSR_STOP	0x0004
29*58a2b000SEvgeniy Ivanov #define CSR_STRT	0x0002
30*58a2b000SEvgeniy Ivanov #define CSR_INIT	0x0001
31*58a2b000SEvgeniy Ivanov 
32*58a2b000SEvgeniy Ivanov /* csr1 contains low 16 bits of address of Initialization Block */
33*58a2b000SEvgeniy Ivanov 
34*58a2b000SEvgeniy Ivanov /* csr2 contains in low byte high 8 bits of address of InitBlock */
35*58a2b000SEvgeniy Ivanov 
36*58a2b000SEvgeniy Ivanov /* contents of csr3 */
37*58a2b000SEvgeniy Ivanov #define CSR3_BSWP	0x04	/* byte swap (for big endian) */
38*58a2b000SEvgeniy Ivanov #define CSR3_ACON	0x02	/* ALE control */
39*58a2b000SEvgeniy Ivanov #define CSR3_BCON	0x01	/* byte control */
40*58a2b000SEvgeniy Ivanov 
41*58a2b000SEvgeniy Ivanov /*
42*58a2b000SEvgeniy Ivanov  * The initialization block
43*58a2b000SEvgeniy Ivanov  */
44*58a2b000SEvgeniy Ivanov typedef struct {
45*58a2b000SEvgeniy Ivanov 	u_short	ib_mode;	/* modebits, see below */
46*58a2b000SEvgeniy Ivanov 	char	ib_padr[6];	/* physical 48bit Ether-address */
47*58a2b000SEvgeniy Ivanov 	u_short	ib_ladrf[4];	/* 64bit hashtable for "logical" addresses */
48*58a2b000SEvgeniy Ivanov 	u_short	ib_rdralow;	/* low 16 bits of Receiver Descr. Ring addr */
49*58a2b000SEvgeniy Ivanov 	u_char	ib_rdrahigh;	/* high 8 bits of Receiver Descr. Ring addr */
50*58a2b000SEvgeniy Ivanov 	u_char	ib_rlen;	/* upper 3 bits are 2log Rec. Ring Length */
51*58a2b000SEvgeniy Ivanov 	u_short	ib_tdralow;	/* low 16 bits of Transm. Descr. Ring addr */
52*58a2b000SEvgeniy Ivanov 	u_char	ib_tdrahigh;	/* high 8 bits of Transm. Descr. Ring addr */
53*58a2b000SEvgeniy Ivanov 	u_char	ib_tlen;	/* upper 3 bits are 2log Transm. Ring Length */
54*58a2b000SEvgeniy Ivanov } initblock_t;
55*58a2b000SEvgeniy Ivanov 
56*58a2b000SEvgeniy Ivanov /* bits in mode */
57*58a2b000SEvgeniy Ivanov #define IB_PROM		0x8000
58*58a2b000SEvgeniy Ivanov #define IB_INTL		0x0040
59*58a2b000SEvgeniy Ivanov #define IB_DRTY		0x0020
60*58a2b000SEvgeniy Ivanov #define IB_COLL		0x0010
61*58a2b000SEvgeniy Ivanov #define IB_DTCR		0x0008
62*58a2b000SEvgeniy Ivanov #define IB_LOOP		0x0004
63*58a2b000SEvgeniy Ivanov #define IB_DTX		0x0002
64*58a2b000SEvgeniy Ivanov #define IB_DRX		0x0001
65*58a2b000SEvgeniy Ivanov 
66*58a2b000SEvgeniy Ivanov /*
67*58a2b000SEvgeniy Ivanov  * A receive message descriptor entry
68*58a2b000SEvgeniy Ivanov  */
69*58a2b000SEvgeniy Ivanov typedef struct {
70*58a2b000SEvgeniy Ivanov 	u_short	rmd_ladr;	/* low 16 bits of bufaddr */
71*58a2b000SEvgeniy Ivanov 	char	rmd_hadr;	/* high 8 bits of bufaddr */
72*58a2b000SEvgeniy Ivanov 	char	rmd_flags; 	/* see below */
73*58a2b000SEvgeniy Ivanov 	short	rmd_bcnt;	/* two's complement of buffer byte count */
74*58a2b000SEvgeniy Ivanov 	u_short	rmd_mcnt;	/* message byte count */
75*58a2b000SEvgeniy Ivanov } rmde_t;
76*58a2b000SEvgeniy Ivanov 
77*58a2b000SEvgeniy Ivanov /* bits in flags */
78*58a2b000SEvgeniy Ivanov #define RMD_OWN		0x80
79*58a2b000SEvgeniy Ivanov #define RMD_ERR		0x40
80*58a2b000SEvgeniy Ivanov #define RMD_FRAM	0x20
81*58a2b000SEvgeniy Ivanov #define RMD_OFLO	0x10
82*58a2b000SEvgeniy Ivanov #define RMD_CRC		0x08
83*58a2b000SEvgeniy Ivanov #define RMD_BUFF	0x04
84*58a2b000SEvgeniy Ivanov #define RMD_STP		0x02
85*58a2b000SEvgeniy Ivanov #define RMD_ENP		0x01
86*58a2b000SEvgeniy Ivanov 
87*58a2b000SEvgeniy Ivanov /*
88*58a2b000SEvgeniy Ivanov  * A transmit message descriptor entry
89*58a2b000SEvgeniy Ivanov  */
90*58a2b000SEvgeniy Ivanov typedef struct {
91*58a2b000SEvgeniy Ivanov 	u_short	tmd_ladr;	/* low 16 bits of bufaddr */
92*58a2b000SEvgeniy Ivanov 	u_char	tmd_hadr;	/* high 8 bits of bufaddr */
93*58a2b000SEvgeniy Ivanov 	u_char	tmd_flags;	/* see below */
94*58a2b000SEvgeniy Ivanov 	short	tmd_bcnt;	/* two's complement of buffer byte count */
95*58a2b000SEvgeniy Ivanov 	u_short	tmd_err;	/* more error bits + TDR */
96*58a2b000SEvgeniy Ivanov } tmde_t;
97*58a2b000SEvgeniy Ivanov 
98*58a2b000SEvgeniy Ivanov /* bits in flags */
99*58a2b000SEvgeniy Ivanov #define TMD_OWN		0x80
100*58a2b000SEvgeniy Ivanov #define TMD_ERR		0x40
101*58a2b000SEvgeniy Ivanov #define TMD_MORE	0x10
102*58a2b000SEvgeniy Ivanov #define TMD_ONE		0x08
103*58a2b000SEvgeniy Ivanov #define TMD_DEF		0x04
104*58a2b000SEvgeniy Ivanov #define TMD_STP		0x02
105*58a2b000SEvgeniy Ivanov #define TMD_ENP		0x01
106*58a2b000SEvgeniy Ivanov 
107*58a2b000SEvgeniy Ivanov /* bits in tmd_err */
108*58a2b000SEvgeniy Ivanov #define TMDE_BUFF	0x8000
109*58a2b000SEvgeniy Ivanov #define TMDE_UFLO	0x4000
110*58a2b000SEvgeniy Ivanov #define TMDE_LCOL	0x1000
111*58a2b000SEvgeniy Ivanov #define TMDE_LCAR	0x0800
112*58a2b000SEvgeniy Ivanov #define TMDE_RTRY	0x0400
113*58a2b000SEvgeniy Ivanov #define TMDE_TDR	0x003F	/* mask for TDR */
114