1*433d6423SLionel Sambuc #ifndef __OMAP_RTC_REGISTERS_H 2*433d6423SLionel Sambuc #define __OMAP_RTC_REGISTERS_H 3*433d6423SLionel Sambuc 4*433d6423SLionel Sambuc /* RTC Addresses for am335x (BeagleBone White / BeagleBone Black) */ 5*433d6423SLionel Sambuc 6*433d6423SLionel Sambuc /* Base Addresses */ 7*433d6423SLionel Sambuc #define AM335X_RTC_SS_BASE 0x44e3e000 8*433d6423SLionel Sambuc 9*433d6423SLionel Sambuc /* Size of RTC Register Address Range */ 10*433d6423SLionel Sambuc #define AM335X_RTC_SS_SIZE 0x1000 11*433d6423SLionel Sambuc 12*433d6423SLionel Sambuc /* Register Offsets */ 13*433d6423SLionel Sambuc #define AM335X_RTC_SS_SECONDS_REG 0x0 14*433d6423SLionel Sambuc #define AM335X_RTC_SS_MINUTES_REG 0x4 15*433d6423SLionel Sambuc #define AM335X_RTC_SS_HOURS_REG 0x8 16*433d6423SLionel Sambuc #define AM335X_RTC_SS_DAYS_REG 0xC 17*433d6423SLionel Sambuc #define AM335X_RTC_SS_MONTHS_REG 0x10 18*433d6423SLionel Sambuc #define AM335X_RTC_SS_YEARS_REG 0x14 19*433d6423SLionel Sambuc #define AM335X_RTC_SS_WEEKS_REG 0x18 20*433d6423SLionel Sambuc #define AM335X_RTC_SS_ALARM_SECONDS_REG 0x20 21*433d6423SLionel Sambuc #define AM335X_RTC_SS_ALARM_MINUTES_REG 0x24 22*433d6423SLionel Sambuc #define AM335X_RTC_SS_ALARM_HOURS_REG 0x28 23*433d6423SLionel Sambuc #define AM335X_RTC_SS_ALARM_DAYS_REG 0x2C 24*433d6423SLionel Sambuc #define AM335X_RTC_SS_ALARM_MONTHS_REG 0x30 25*433d6423SLionel Sambuc #define AM335X_RTC_SS_ALARM_YEARS_REG 0x34 26*433d6423SLionel Sambuc #define AM335X_RTC_SS_RTC_CTRL_REG 0x40 27*433d6423SLionel Sambuc #define AM335X_RTC_SS_RTC_STATUS_REG 0x44 28*433d6423SLionel Sambuc #define AM335X_RTC_SS_RTC_INTERRUPTS_REG 0x48 29*433d6423SLionel Sambuc #define AM335X_RTC_SS_RTC_COMP_LSB_REG 0x4C 30*433d6423SLionel Sambuc #define AM335X_RTC_SS_RTC_COMP_MSB_REG 0x50 31*433d6423SLionel Sambuc #define AM335X_RTC_SS_RTC_OSC_REG 0x54 32*433d6423SLionel Sambuc #define AM335X_RTC_SS_RTC_SCRATCH0_REG 0x60 33*433d6423SLionel Sambuc #define AM335X_RTC_SS_RTC_SCRATCH1_REG 0x64 34*433d6423SLionel Sambuc #define AM335X_RTC_SS_RTC_SCRATCH2_REG 0x68 35*433d6423SLionel Sambuc #define AM335X_RTC_SS_KICK0R 0x6C 36*433d6423SLionel Sambuc #define AM335X_RTC_SS_KICK1R 0x70 37*433d6423SLionel Sambuc #define AM335X_RTC_SS_RTC_REVISION 0x74 38*433d6423SLionel Sambuc #define AM335X_RTC_SS_RTC_SYSCONFIG 0x78 39*433d6423SLionel Sambuc #define AM335X_RTC_SS_RTC_IRQWAKEEN 0x7C 40*433d6423SLionel Sambuc #define AM335X_RTC_SS_ALARM2_SECONDS_REG 0x80 41*433d6423SLionel Sambuc #define AM335X_RTC_SS_ALARM2_MINUTES_REG 0x84 42*433d6423SLionel Sambuc #define AM335X_RTC_SS_ALARM2_HOURS_REG 0x88 43*433d6423SLionel Sambuc #define AM335X_RTC_SS_ALARM2_DAYS_REG 0x8C 44*433d6423SLionel Sambuc #define AM335X_RTC_SS_ALARM2_MONTHS_REG 0x90 45*433d6423SLionel Sambuc #define AM335X_RTC_SS_ALARM2_YEARS_REG 0x94 46*433d6423SLionel Sambuc #define AM335X_RTC_SS_RTC_PMIC 0x98 47*433d6423SLionel Sambuc #define AM335X_RTC_SS_RTC_DEBOUNCE 0x9C 48*433d6423SLionel Sambuc 49*433d6423SLionel Sambuc /* Constants */ 50*433d6423SLionel Sambuc #define AM335X_RTC_SS_KICK0R_UNLOCK_MASK 0x83E70B13 51*433d6423SLionel Sambuc #define AM335X_RTC_SS_KICK1R_UNLOCK_MASK 0x95A4F1E0 52*433d6423SLionel Sambuc 53*433d6423SLionel Sambuc #define AM335X_RTC_SS_KICK0R_LOCK_MASK 0x546f6d20 54*433d6423SLionel Sambuc #define AM335X_RTC_SS_KICK1R_LOCK_MASK 0x436f7274 55*433d6423SLionel Sambuc 56*433d6423SLionel Sambuc /* Bits */ 57*433d6423SLionel Sambuc 58*433d6423SLionel Sambuc /* RTC_SS_RTC_STATUS_REG */ 59*433d6423SLionel Sambuc #define RTC_BUSY_BIT 0 60*433d6423SLionel Sambuc 61*433d6423SLionel Sambuc /* RTC_SS_RTC_CTRL_REG */ 62*433d6423SLionel Sambuc #define RTC_STOP_BIT 0 63*433d6423SLionel Sambuc 64*433d6423SLionel Sambuc /* RTC_SS_RTC_SYSCONFIG */ 65*433d6423SLionel Sambuc #define NOIDLE_BIT 0 66*433d6423SLionel Sambuc 67*433d6423SLionel Sambuc /* RTC_SS_RTC_OSC_REG */ 68*433d6423SLionel Sambuc #define EN_32KCLK_BIT 6 69*433d6423SLionel Sambuc 70*433d6423SLionel Sambuc /* RTC_SS_RTC_PMIC */ 71*433d6423SLionel Sambuc #define PWR_ENABLE_EN_BIT 16 72*433d6423SLionel Sambuc 73*433d6423SLionel Sambuc /* RTC_SS_RTC_INTERRUPTS_REG */ 74*433d6423SLionel Sambuc #define IT_ALARM2_BIT 4 75*433d6423SLionel Sambuc 76*433d6423SLionel Sambuc /* Clocks */ 77*433d6423SLionel Sambuc #define CM_RTC_RTC_CLKCTRL 0x800 78*433d6423SLionel Sambuc #define CM_RTC_RTC_CLKCTRL_IDLEST ((0<<17)|(0<<16)) 79*433d6423SLionel Sambuc #define CM_RTC_RTC_CLKCTRL_MODULEMODE ((1<<1)|(0<<0)) 80*433d6423SLionel Sambuc #define CM_RTC_RTC_CLKCTRL_MASK (CM_RTC_RTC_CLKCTRL_IDLEST|CM_RTC_RTC_CLKCTRL_MODULEMODE) 81*433d6423SLionel Sambuc 82*433d6423SLionel Sambuc #define CM_RTC_CLKSTCTRL 0x804 83*433d6423SLionel Sambuc #define CLKACTIVITY_RTC_32KCLK (1<<9) 84*433d6423SLionel Sambuc #define CLKACTIVITY_L4_RTC_GCLK (1<<8) 85*433d6423SLionel Sambuc #define CLKTRCTRL ((0<<1)|(0<<0)) 86*433d6423SLionel Sambuc #define CM_RTC_CLKSTCTRL_MASK (CLKACTIVITY_RTC_32KCLK|CLKACTIVITY_L4_RTC_GCLK|CLKTRCTRL) 87*433d6423SLionel Sambuc 88*433d6423SLionel Sambuc int omap_rtc_init(void); 89*433d6423SLionel Sambuc int omap_rtc_get_time(struct tm *t, int flags); 90*433d6423SLionel Sambuc int omap_rtc_set_time(struct tm *t, int flags); 91*433d6423SLionel Sambuc int omap_rtc_pwr_off(void); 92*433d6423SLionel Sambuc void omap_rtc_exit(void); 93*433d6423SLionel Sambuc 94*433d6423SLionel Sambuc #endif /* __OMAP_RTC_REGISTERS_H */ 95