1*f4a2713aSLionel Sambuc; RUN: llc -mtriple x86_64-linux -mcpu core2 -verify-machineinstrs %s -o - | FileCheck %s 2*f4a2713aSLionel Sambucdefine i32 @f(i1 %foo, i16* %tm_year2, i8* %bar, i16 %zed, i32 %zed2) { 3*f4a2713aSLionel Sambucentry: 4*f4a2713aSLionel Sambuc br i1 %foo, label %return, label %if.end 5*f4a2713aSLionel Sambuc 6*f4a2713aSLionel Sambucif.end: 7*f4a2713aSLionel Sambuc %rem = srem i32 %zed2, 100 8*f4a2713aSLionel Sambuc %conv3 = trunc i32 %rem to i16 9*f4a2713aSLionel Sambuc store i16 %conv3, i16* %tm_year2 10*f4a2713aSLionel Sambuc %sext = shl i32 %rem, 16 11*f4a2713aSLionel Sambuc %conv5 = ashr exact i32 %sext, 16 12*f4a2713aSLionel Sambuc %div = sdiv i32 %conv5, 10 13*f4a2713aSLionel Sambuc %conv6 = trunc i32 %div to i8 14*f4a2713aSLionel Sambuc store i8 %conv6, i8* %bar 15*f4a2713aSLionel Sambuc br label %return 16*f4a2713aSLionel Sambuc 17*f4a2713aSLionel Sambucreturn: 18*f4a2713aSLionel Sambuc %retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ] 19*f4a2713aSLionel Sambuc ret i32 %retval.0 20*f4a2713aSLionel Sambuc} 21*f4a2713aSLionel Sambuc 22*f4a2713aSLionel Sambuc; We were miscompiling this and using %ax instead of %cx in the movw 23*f4a2713aSLionel Sambuc; in the following sequence: 24*f4a2713aSLionel Sambuc; movswl %cx, %ecx 25*f4a2713aSLionel Sambuc; movw %cx, (%rsi) 26*f4a2713aSLionel Sambuc; movslq %ecx, %rcx 27*f4a2713aSLionel Sambuc; 28*f4a2713aSLionel Sambuc; We can't produce the above sequence without special SD-level 29*f4a2713aSLionel Sambuc; heuristics. Now we produce this: 30*f4a2713aSLionel Sambuc; CHECK: movw %ax, (%rsi) 31*f4a2713aSLionel Sambuc; CHECK: cwtl 32*f4a2713aSLionel Sambuc; CHECK: cltq 33