1*f4a2713aSLionel Sambuc; RUN: llc < %s -march=x86 | grep sar | count 1 2*f4a2713aSLionel Sambuc; RUN: llc < %s -march=x86-64 | not grep sar 3*f4a2713aSLionel Sambuc 4*f4a2713aSLionel Sambucdefine i32 @test(i32 %f12) nounwind { 5*f4a2713aSLionel Sambuc %tmp7.25 = lshr i32 %f12, 16 6*f4a2713aSLionel Sambuc %tmp7.26 = trunc i32 %tmp7.25 to i8 7*f4a2713aSLionel Sambuc %tmp78.2 = sext i8 %tmp7.26 to i32 8*f4a2713aSLionel Sambuc ret i32 %tmp78.2 9*f4a2713aSLionel Sambuc} 10*f4a2713aSLionel Sambuc 11*f4a2713aSLionel Sambucdefine i32 @test2(i32 %f12) nounwind { 12*f4a2713aSLionel Sambuc %f11 = shl i32 %f12, 8 13*f4a2713aSLionel Sambuc %tmp7.25 = ashr i32 %f11, 24 14*f4a2713aSLionel Sambuc ret i32 %tmp7.25 15*f4a2713aSLionel Sambuc} 16*f4a2713aSLionel Sambuc 17*f4a2713aSLionel Sambucdefine i32 @test3(i32 %f12) nounwind { 18*f4a2713aSLionel Sambuc %f11 = shl i32 %f12, 13 19*f4a2713aSLionel Sambuc %tmp7.25 = ashr i32 %f11, 24 20*f4a2713aSLionel Sambuc ret i32 %tmp7.25 21*f4a2713aSLionel Sambuc} 22*f4a2713aSLionel Sambuc 23*f4a2713aSLionel Sambucdefine i64 @test4(i64 %f12) nounwind { 24*f4a2713aSLionel Sambuc %f11 = shl i64 %f12, 32 25*f4a2713aSLionel Sambuc %tmp7.25 = ashr i64 %f11, 32 26*f4a2713aSLionel Sambuc ret i64 %tmp7.25 27*f4a2713aSLionel Sambuc} 28*f4a2713aSLionel Sambuc 29*f4a2713aSLionel Sambucdefine i16 @test5(i16 %f12) nounwind { 30*f4a2713aSLionel Sambuc %f11 = shl i16 %f12, 2 31*f4a2713aSLionel Sambuc %tmp7.25 = ashr i16 %f11, 8 32*f4a2713aSLionel Sambuc ret i16 %tmp7.25 33*f4a2713aSLionel Sambuc} 34*f4a2713aSLionel Sambuc 35*f4a2713aSLionel Sambucdefine i16 @test6(i16 %f12) nounwind { 36*f4a2713aSLionel Sambuc %f11 = shl i16 %f12, 8 37*f4a2713aSLionel Sambuc %tmp7.25 = ashr i16 %f11, 8 38*f4a2713aSLionel Sambuc ret i16 %tmp7.25 39*f4a2713aSLionel Sambuc} 40