147c8ec81SMatt Arsenault //===- ReduceRegisterUses.cpp - Specialized Delta Pass --------------------===// 247c8ec81SMatt Arsenault // 347c8ec81SMatt Arsenault // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 447c8ec81SMatt Arsenault // See https://llvm.org/LICENSE.txt for license information. 547c8ec81SMatt Arsenault // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 647c8ec81SMatt Arsenault // 747c8ec81SMatt Arsenault //===----------------------------------------------------------------------===// 847c8ec81SMatt Arsenault // 947c8ec81SMatt Arsenault // This file implements a function which calls the Generic Delta pass in order 1047c8ec81SMatt Arsenault // to reduce uninteresting register uses from the MachineFunction. 1147c8ec81SMatt Arsenault // 1247c8ec81SMatt Arsenault //===----------------------------------------------------------------------===// 1347c8ec81SMatt Arsenault 1447c8ec81SMatt Arsenault #include "ReduceRegisterUses.h" 1547c8ec81SMatt Arsenault #include "llvm/CodeGen/MachineFunction.h" 16333ffafbSMatt Arsenault #include "llvm/CodeGen/MachineModuleInfo.h" 1747c8ec81SMatt Arsenault #include "llvm/CodeGen/MachineRegisterInfo.h" 1847c8ec81SMatt Arsenault 1947c8ec81SMatt Arsenault using namespace llvm; 2047c8ec81SMatt Arsenault removeUsesFromFunction(Oracle & O,MachineFunction & MF)2147c8ec81SMatt Arsenaultstatic void removeUsesFromFunction(Oracle &O, MachineFunction &MF) { 2247c8ec81SMatt Arsenault MachineRegisterInfo &MRI = MF.getRegInfo(); 2347c8ec81SMatt Arsenault 2447c8ec81SMatt Arsenault for (MachineBasicBlock &MBB : MF) { 2547c8ec81SMatt Arsenault for (MachineInstr &MI : MBB) { 26cbbc7e4aSMatt Arsenault // Generic instructions are not supposed to have undef operands. 27cbbc7e4aSMatt Arsenault if (isPreISelGenericOpcode(MI.getOpcode())) 28cbbc7e4aSMatt Arsenault continue; 29cbbc7e4aSMatt Arsenault 3047c8ec81SMatt Arsenault int NumOperands = MI.getNumOperands(); 3147c8ec81SMatt Arsenault int NumRequiredOps = MI.getNumExplicitOperands() + 32*073401e5SJay Foad MI.getDesc().implicit_defs().size() + 33*073401e5SJay Foad MI.getDesc().implicit_uses().size(); 3447c8ec81SMatt Arsenault 3547c8ec81SMatt Arsenault for (int I = NumOperands - 1; I >= 0; --I) { 3647c8ec81SMatt Arsenault MachineOperand &MO = MI.getOperand(I); 3747c8ec81SMatt Arsenault if (!MO.isReg() || !MO.readsReg()) 3847c8ec81SMatt Arsenault continue; 3947c8ec81SMatt Arsenault 4047c8ec81SMatt Arsenault Register Reg = MO.getReg(); 4147c8ec81SMatt Arsenault if (Reg.isPhysical() && MRI.isReserved(Reg)) 4247c8ec81SMatt Arsenault continue; 4347c8ec81SMatt Arsenault 4447c8ec81SMatt Arsenault if (O.shouldKeep()) 4547c8ec81SMatt Arsenault continue; 4647c8ec81SMatt Arsenault 4747c8ec81SMatt Arsenault // Remove implicit operands. If the register is part of the fixed 4847c8ec81SMatt Arsenault // operand list, set to undef. 4947c8ec81SMatt Arsenault if (I >= NumRequiredOps) 5047c8ec81SMatt Arsenault MI.removeOperand(I); 5147c8ec81SMatt Arsenault else 5247c8ec81SMatt Arsenault MO.setIsUndef(); 5347c8ec81SMatt Arsenault } 5447c8ec81SMatt Arsenault } 5547c8ec81SMatt Arsenault } 5647c8ec81SMatt Arsenault } 5747c8ec81SMatt Arsenault removeUsesFromModule(Oracle & O,ReducerWorkItem & WorkItem)5847c8ec81SMatt Arsenaultstatic void removeUsesFromModule(Oracle &O, ReducerWorkItem &WorkItem) { 5947c8ec81SMatt Arsenault for (const Function &F : WorkItem.getModule()) { 6047c8ec81SMatt Arsenault if (auto *MF = WorkItem.MMI->getMachineFunction(F)) 6147c8ec81SMatt Arsenault removeUsesFromFunction(O, *MF); 6247c8ec81SMatt Arsenault } 6347c8ec81SMatt Arsenault } 6447c8ec81SMatt Arsenault reduceRegisterUsesMIRDeltaPass(TestRunner & Test)6547c8ec81SMatt Arsenaultvoid llvm::reduceRegisterUsesMIRDeltaPass(TestRunner &Test) { 662592ccdeSArthur Eubanks runDeltaPass(Test, removeUsesFromModule, "Reducing register uses"); 6747c8ec81SMatt Arsenault } 68