1*ffdd5a33SGanesh Gopalasubramanian# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2*ffdd5a33SGanesh Gopalasubramanian# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver4 -instruction-tables < %s | FileCheck %s 3*ffdd5a33SGanesh Gopalasubramanian 4*ffdd5a33SGanesh Gopalasubramanianxgetbv 5*ffdd5a33SGanesh Gopalasubramanian 6*ffdd5a33SGanesh Gopalasubramanianxrstor (%rax) 7*ffdd5a33SGanesh Gopalasubramanian 8*ffdd5a33SGanesh Gopalasubramanianxrstors (%rax) 9*ffdd5a33SGanesh Gopalasubramanian 10*ffdd5a33SGanesh Gopalasubramanianxsave (%rax) 11*ffdd5a33SGanesh Gopalasubramanian 12*ffdd5a33SGanesh Gopalasubramanianxsetbv 13*ffdd5a33SGanesh Gopalasubramanian 14*ffdd5a33SGanesh Gopalasubramanian# CHECK: Instruction Info: 15*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [1]: #uOps 16*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [2]: Latency 17*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [3]: RThroughput 18*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [4]: MayLoad 19*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [5]: MayStore 20*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [6]: HasSideEffects (U) 21*ffdd5a33SGanesh Gopalasubramanian 22*ffdd5a33SGanesh Gopalasubramanian# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 23*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: 100 100 25.00 U xgetbv 24*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: 100 100 25.00 * * U xrstor (%rax) 25*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: 100 100 25.00 * * U xrstors (%rax) 26*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: 100 100 25.00 * * U xsave (%rax) 27*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: 100 100 25.00 * * U xsetbv 28*ffdd5a33SGanesh Gopalasubramanian 29*ffdd5a33SGanesh Gopalasubramanian# CHECK: Resources: 30*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [0] - Zn4AGU0 31*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [1] - Zn4AGU1 32*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [2] - Zn4AGU2 33*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [3] - Zn4ALU0 34*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [4] - Zn4ALU1 35*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [5] - Zn4ALU2 36*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [6] - Zn4ALU3 37*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [7] - Zn4BRU1 38*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [8] - Zn4FP0 39*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [9] - Zn4FP1 40*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [10] - Zn4FP2 41*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [11] - Zn4FP3 42*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [12.0] - Zn4FP45 43*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [12.1] - Zn4FP45 44*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [13] - Zn4FPSt 45*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [14.0] - Zn4LSU 46*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [14.1] - Zn4LSU 47*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [14.2] - Zn4LSU 48*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [15.0] - Zn4Load 49*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [15.1] - Zn4Load 50*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [15.2] - Zn4Load 51*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [16.0] - Zn4Store 52*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [16.1] - Zn4Store 53*ffdd5a33SGanesh Gopalasubramanian 54*ffdd5a33SGanesh Gopalasubramanian# CHECK: Resource pressure per iteration: 55*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] 56*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: - - - 125.00 125.00 125.00 125.00 - - - - - - - - - - - - - - - - 57*ffdd5a33SGanesh Gopalasubramanian 58*ffdd5a33SGanesh Gopalasubramanian# CHECK: Resource pressure by instruction: 59*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions: 60*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - xgetbv 61*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - xrstor (%rax) 62*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - xrstors (%rax) 63*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - xsave (%rax) 64*ffdd5a33SGanesh Gopalasubramanian# CHECK-NEXT: - - - 25.00 25.00 25.00 25.00 - - - - - - - - - - - - - - - - xsetbv 65