13408940fSGanesh Gopalasubramanian# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 23408940fSGanesh Gopalasubramanian# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver2 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s 33408940fSGanesh Gopalasubramanian 43408940fSGanesh Gopalasubramanianimul %ax, %cx 53408940fSGanesh Gopalasubramanianadd %al, %cl 63408940fSGanesh Gopalasubramanianadd %ecx, %ebx 73408940fSGanesh Gopalasubramanian 83408940fSGanesh Gopalasubramanian# CHECK: Iterations: 1 93408940fSGanesh Gopalasubramanian# CHECK-NEXT: Instructions: 3 103408940fSGanesh Gopalasubramanian# CHECK-NEXT: Total Cycles: 8 113408940fSGanesh Gopalasubramanian# CHECK-NEXT: Total uOps: 3 123408940fSGanesh Gopalasubramanian 133408940fSGanesh Gopalasubramanian# CHECK: Dispatch Width: 4 143408940fSGanesh Gopalasubramanian# CHECK-NEXT: uOps Per Cycle: 0.38 153408940fSGanesh Gopalasubramanian# CHECK-NEXT: IPC: 0.38 163408940fSGanesh Gopalasubramanian# CHECK-NEXT: Block RThroughput: 1.0 173408940fSGanesh Gopalasubramanian 183408940fSGanesh Gopalasubramanian# CHECK: Instruction Info: 193408940fSGanesh Gopalasubramanian# CHECK-NEXT: [1]: #uOps 203408940fSGanesh Gopalasubramanian# CHECK-NEXT: [2]: Latency 213408940fSGanesh Gopalasubramanian# CHECK-NEXT: [3]: RThroughput 223408940fSGanesh Gopalasubramanian# CHECK-NEXT: [4]: MayLoad 233408940fSGanesh Gopalasubramanian# CHECK-NEXT: [5]: MayStore 243408940fSGanesh Gopalasubramanian# CHECK-NEXT: [6]: HasSideEffects (U) 253408940fSGanesh Gopalasubramanian 263408940fSGanesh Gopalasubramanian# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 273408940fSGanesh Gopalasubramanian# CHECK-NEXT: 1 3 1.00 imulw %ax, %cx 283408940fSGanesh Gopalasubramanian# CHECK-NEXT: 1 1 0.25 addb %al, %cl 293408940fSGanesh Gopalasubramanian# CHECK-NEXT: 1 1 0.25 addl %ecx, %ebx 303408940fSGanesh Gopalasubramanian 313408940fSGanesh Gopalasubramanian# CHECK: Timeline view: 323408940fSGanesh Gopalasubramanian# CHECK-NEXT: Index 01234567 333408940fSGanesh Gopalasubramanian 343408940fSGanesh Gopalasubramanian# CHECK: [0,0] DeeeER . imulw %ax, %cx 353408940fSGanesh Gopalasubramanian# CHECK-NEXT: [0,1] D===eER. addb %al, %cl 363408940fSGanesh Gopalasubramanian# CHECK-NEXT: [0,2] D====eER addl %ecx, %ebx 373408940fSGanesh Gopalasubramanian 383408940fSGanesh Gopalasubramanian# CHECK: Average Wait times (based on the timeline view): 393408940fSGanesh Gopalasubramanian# CHECK-NEXT: [0]: Executions 403408940fSGanesh Gopalasubramanian# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue 413408940fSGanesh Gopalasubramanian# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready 423408940fSGanesh Gopalasubramanian# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage 433408940fSGanesh Gopalasubramanian 443408940fSGanesh Gopalasubramanian# CHECK: [0] [1] [2] [3] 453408940fSGanesh Gopalasubramanian# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulw %ax, %cx 463408940fSGanesh Gopalasubramanian# CHECK-NEXT: 1. 1 4.0 0.0 0.0 addb %al, %cl 473408940fSGanesh Gopalasubramanian# CHECK-NEXT: 2. 1 5.0 0.0 0.0 addl %ecx, %ebx 48*2accdb6aSClement Courbet# CHECK-NEXT: 1 3.3 0.3 0.0 <total> 49