xref: /llvm-project/llvm/test/tools/llvm-mca/X86/BdVer2/resources-prefetchw.s (revision 9db0e72570f73e4e8aaf870201f2c1bc738baee3)
1a5192187SRoman Lebedev# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2a5baf867SRoman Lebedev# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -instruction-tables < %s | FileCheck %s
3a5192187SRoman Lebedev
4a5192187SRoman Lebedevprefetch    (%rax)
5a5192187SRoman Lebedevprefetchw   (%rax)
6a5192187SRoman Lebedev
7a5192187SRoman Lebedev# CHECK:      Instruction Info:
8a5192187SRoman Lebedev# CHECK-NEXT: [1]: #uOps
9a5192187SRoman Lebedev# CHECK-NEXT: [2]: Latency
10a5192187SRoman Lebedev# CHECK-NEXT: [3]: RThroughput
11a5192187SRoman Lebedev# CHECK-NEXT: [4]: MayLoad
12a5192187SRoman Lebedev# CHECK-NEXT: [5]: MayStore
13a5192187SRoman Lebedev# CHECK-NEXT: [6]: HasSideEffects (U)
14a5192187SRoman Lebedev
15a5192187SRoman Lebedev# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
16*9db0e725SRoman Lebedev# CHECK-NEXT:  1      5     1.00    *      *            prefetch	(%rax)
17*9db0e725SRoman Lebedev# CHECK-NEXT:  1      5     1.00    *      *            prefetchw	(%rax)
18a5192187SRoman Lebedev
19a5192187SRoman Lebedev# CHECK:      Resources:
20a5baf867SRoman Lebedev# CHECK-NEXT: [0.0] - PdAGLU01
21a5baf867SRoman Lebedev# CHECK-NEXT: [0.1] - PdAGLU01
22a5baf867SRoman Lebedev# CHECK-NEXT: [1]   - PdBranch
23a5baf867SRoman Lebedev# CHECK-NEXT: [2]   - PdCount
24a5baf867SRoman Lebedev# CHECK-NEXT: [3]   - PdDiv
25a5baf867SRoman Lebedev# CHECK-NEXT: [4]   - PdEX0
26a5baf867SRoman Lebedev# CHECK-NEXT: [5]   - PdEX1
27a5baf867SRoman Lebedev# CHECK-NEXT: [6]   - PdFPCVT
28a5baf867SRoman Lebedev# CHECK-NEXT: [7.0] - PdFPFMA
29a5baf867SRoman Lebedev# CHECK-NEXT: [7.1] - PdFPFMA
30a5baf867SRoman Lebedev# CHECK-NEXT: [8.0] - PdFPMAL
31a5baf867SRoman Lebedev# CHECK-NEXT: [8.1] - PdFPMAL
32a5baf867SRoman Lebedev# CHECK-NEXT: [9]   - PdFPMMA
33a5baf867SRoman Lebedev# CHECK-NEXT: [10]  - PdFPSTO
34a5baf867SRoman Lebedev# CHECK-NEXT: [11]  - PdFPU0
35a5baf867SRoman Lebedev# CHECK-NEXT: [12]  - PdFPU1
36a5baf867SRoman Lebedev# CHECK-NEXT: [13]  - PdFPU2
37a5baf867SRoman Lebedev# CHECK-NEXT: [14]  - PdFPU3
38a5baf867SRoman Lebedev# CHECK-NEXT: [15]  - PdFPXBR
39b428b8b2SRoman Lebedev# CHECK-NEXT: [16.0] - PdLoad
40b428b8b2SRoman Lebedev# CHECK-NEXT: [16.1] - PdLoad
41b428b8b2SRoman Lebedev# CHECK-NEXT: [17]  - PdMul
42b428b8b2SRoman Lebedev# CHECK-NEXT: [18]  - PdStore
43a5192187SRoman Lebedev
44a5192187SRoman Lebedev# CHECK:      Resource pressure per iteration:
45b428b8b2SRoman Lebedev# CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]
46*9db0e725SRoman Lebedev# CHECK-NEXT: 2.00   2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00   2.00    -      -
47a5192187SRoman Lebedev
48a5192187SRoman Lebedev# CHECK:      Resource pressure by instruction:
49b428b8b2SRoman Lebedev# CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
50*9db0e725SRoman Lebedev# CHECK-NEXT: 1.00   1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   1.00    -      -     prefetch	(%rax)
51*9db0e725SRoman Lebedev# CHECK-NEXT: 1.00   1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   1.00    -      -     prefetchw	(%rax)
52