1a5192187SRoman Lebedev# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2a5baf867SRoman Lebedev# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=22 -dispatch-stats -register-file-stats -resource-pressure=false -timeline -timeline-max-iterations=3 < %s | FileCheck %s 3a5192187SRoman Lebedev 4a5192187SRoman Lebedevidiv %eax 5a5192187SRoman Lebedev 6a5192187SRoman Lebedev# CHECK: Iterations: 22 7a5192187SRoman Lebedev# CHECK-NEXT: Instructions: 22 8a5baf867SRoman Lebedev# CHECK-NEXT: Total Cycles: 542 9a5baf867SRoman Lebedev# CHECK-NEXT: Total uOps: 44 10a5192187SRoman Lebedev 11a5192187SRoman Lebedev# CHECK: Dispatch Width: 4 12a5baf867SRoman Lebedev# CHECK-NEXT: uOps Per Cycle: 0.08 13a5192187SRoman Lebedev# CHECK-NEXT: IPC: 0.04 14a5baf867SRoman Lebedev# CHECK-NEXT: Block RThroughput: 25.0 15a5192187SRoman Lebedev 16a5192187SRoman Lebedev# CHECK: Instruction Info: 17a5192187SRoman Lebedev# CHECK-NEXT: [1]: #uOps 18a5192187SRoman Lebedev# CHECK-NEXT: [2]: Latency 19a5192187SRoman Lebedev# CHECK-NEXT: [3]: RThroughput 20a5192187SRoman Lebedev# CHECK-NEXT: [4]: MayLoad 21a5192187SRoman Lebedev# CHECK-NEXT: [5]: MayStore 22a5192187SRoman Lebedev# CHECK-NEXT: [6]: HasSideEffects (U) 23a5192187SRoman Lebedev 24a5192187SRoman Lebedev# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 25a5baf867SRoman Lebedev# CHECK-NEXT: 2 14 25.00 U idivl %eax 26a5192187SRoman Lebedev 27a5192187SRoman Lebedev# CHECK: Dynamic Dispatch Stall Cycles: 28a5192187SRoman Lebedev# CHECK-NEXT: RAT - Register unavailable: 0 29a5192187SRoman Lebedev# CHECK-NEXT: RCU - Retire tokens unavailable: 0 30a5192187SRoman Lebedev# CHECK-NEXT: SCHEDQ - Scheduler full: 0 31a5192187SRoman Lebedev# CHECK-NEXT: LQ - Load queue full: 0 32a5192187SRoman Lebedev# CHECK-NEXT: SQ - Store queue full: 0 33a5192187SRoman Lebedev# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 34*f0658c7aSAndrea Di Biagio# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0 35a5192187SRoman Lebedev 36a5192187SRoman Lebedev# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: 37a5192187SRoman Lebedev# CHECK-NEXT: [# dispatched], [# cycles] 38a5baf867SRoman Lebedev# CHECK-NEXT: 0, 531 (98.0%) 39a5baf867SRoman Lebedev# CHECK-NEXT: 4, 11 (2.0%) 40a5192187SRoman Lebedev 41a5192187SRoman Lebedev# CHECK: Register File statistics: 42a5192187SRoman Lebedev# CHECK-NEXT: Total number of mappings created: 66 43a5192187SRoman Lebedev# CHECK-NEXT: Max number of mappings used: 66 44a5192187SRoman Lebedev 45a5baf867SRoman Lebedev# CHECK: * Register File #1 -- PdFpuPRF: 46a5baf867SRoman Lebedev# CHECK-NEXT: Number of physical registers: 160 47a5baf867SRoman Lebedev# CHECK-NEXT: Total number of mappings created: 0 48a5baf867SRoman Lebedev# CHECK-NEXT: Max number of mappings used: 0 49a5192187SRoman Lebedev 50a5baf867SRoman Lebedev# CHECK: * Register File #2 -- PdIntegerPRF: 51a5baf867SRoman Lebedev# CHECK-NEXT: Number of physical registers: 96 52a5baf867SRoman Lebedev# CHECK-NEXT: Total number of mappings created: 66 53a5baf867SRoman Lebedev# CHECK-NEXT: Max number of mappings used: 66 54a5baf867SRoman Lebedev 55a5baf867SRoman Lebedev# CHECK: Timeline view: 56a5baf867SRoman Lebedev# CHECK-NEXT: 0123456789 0123456789 0123456789 57a5baf867SRoman Lebedev# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456 58a5baf867SRoman Lebedev 59a5baf867SRoman Lebedev# CHECK: [0,0] DeeeeeeeeeeeeeeER . . . . . . . . . .. idivl %eax 60a5baf867SRoman Lebedev# CHECK-NEXT: [1,0] D=========================eeeeeeeeeeeeeeER . . . . .. idivl %eax 61a5baf867SRoman Lebedev# CHECK-NEXT: [2,0] .D=================================================eeeeeeeeeeeeeeER idivl %eax 62a5192187SRoman Lebedev 63a5192187SRoman Lebedev# CHECK: Average Wait times (based on the timeline view): 64a5192187SRoman Lebedev# CHECK-NEXT: [0]: Executions 65a5192187SRoman Lebedev# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue 66a5192187SRoman Lebedev# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready 67a5192187SRoman Lebedev# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage 68a5192187SRoman Lebedev 69a5192187SRoman Lebedev# CHECK: [0] [1] [2] [3] 70a5baf867SRoman Lebedev# CHECK-NEXT: 0. 3 25.7 7.7 0.0 idivl %eax 71