19f9691c0SRoman Lebedev# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 29f9691c0SRoman Lebedev# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -scheduler-stats -dispatch-stats -iterations=100 -timeline -timeline-max-iterations=1 < %s | FileCheck %s 39f9691c0SRoman Lebedev 49f9691c0SRoman Lebedev# LLVM-MCA-BEGIN 59f9691c0SRoman Lebedevmovb %spl, (%rax) 69f9691c0SRoman Lebedevmovb (%rcx), %bpl 79f9691c0SRoman Lebedevmovb (%rdx), %sil 89f9691c0SRoman Lebedevmovb %dil, (%rbx) 99f9691c0SRoman Lebedev# LLVM-MCA-END 109f9691c0SRoman Lebedev 119f9691c0SRoman Lebedev# LLVM-MCA-BEGIN 129f9691c0SRoman Lebedevmovw %sp, (%rax) 139f9691c0SRoman Lebedevmovw (%rcx), %bp 149f9691c0SRoman Lebedevmovw (%rdx), %si 159f9691c0SRoman Lebedevmovw %di, (%rbx) 169f9691c0SRoman Lebedev# LLVM-MCA-END 179f9691c0SRoman Lebedev 189f9691c0SRoman Lebedev# LLVM-MCA-BEGIN 199f9691c0SRoman Lebedevmovl %esp, (%rax) 209f9691c0SRoman Lebedevmovl (%rcx), %ebp 219f9691c0SRoman Lebedevmovl (%rdx), %esi 229f9691c0SRoman Lebedevmovl %edi, (%rbx) 239f9691c0SRoman Lebedev# LLVM-MCA-END 249f9691c0SRoman Lebedev 259f9691c0SRoman Lebedev# LLVM-MCA-BEGIN 269f9691c0SRoman Lebedevmovq %rsp, (%rax) 279f9691c0SRoman Lebedevmovq (%rcx), %rbp 289f9691c0SRoman Lebedevmovq (%rdx), %rsi 299f9691c0SRoman Lebedevmovq %rdi, (%rbx) 309f9691c0SRoman Lebedev# LLVM-MCA-END 319f9691c0SRoman Lebedev 329f9691c0SRoman Lebedev# LLVM-MCA-BEGIN 339f9691c0SRoman Lebedevmovd %mm0, (%rax) 349f9691c0SRoman Lebedevmovd (%rcx), %mm1 359f9691c0SRoman Lebedevmovd (%rdx), %mm2 369f9691c0SRoman Lebedevmovd %mm3, (%rbx) 379f9691c0SRoman Lebedev# LLVM-MCA-END 389f9691c0SRoman Lebedev 399f9691c0SRoman Lebedev# LLVM-MCA-BEGIN 409f9691c0SRoman Lebedevmovaps %xmm0, (%rax) 419f9691c0SRoman Lebedevmovaps (%rcx), %xmm1 429f9691c0SRoman Lebedevmovaps (%rdx), %xmm2 439f9691c0SRoman Lebedevmovaps %xmm3, (%rbx) 449f9691c0SRoman Lebedev# LLVM-MCA-END 459f9691c0SRoman Lebedev 469f9691c0SRoman Lebedev# CHECK: [0] Code Region 479f9691c0SRoman Lebedev 489f9691c0SRoman Lebedev# CHECK: Iterations: 100 499f9691c0SRoman Lebedev# CHECK-NEXT: Instructions: 400 505578ec32SAndrea Di Biagio# CHECK-NEXT: Total Cycles: 207 519f9691c0SRoman Lebedev# CHECK-NEXT: Total uOps: 400 529f9691c0SRoman Lebedev 539f9691c0SRoman Lebedev# CHECK: Dispatch Width: 4 545578ec32SAndrea Di Biagio# CHECK-NEXT: uOps Per Cycle: 1.93 555578ec32SAndrea Di Biagio# CHECK-NEXT: IPC: 1.93 569f9691c0SRoman Lebedev# CHECK-NEXT: Block RThroughput: 2.0 579f9691c0SRoman Lebedev 589f9691c0SRoman Lebedev# CHECK: Instruction Info: 599f9691c0SRoman Lebedev# CHECK-NEXT: [1]: #uOps 609f9691c0SRoman Lebedev# CHECK-NEXT: [2]: Latency 619f9691c0SRoman Lebedev# CHECK-NEXT: [3]: RThroughput 629f9691c0SRoman Lebedev# CHECK-NEXT: [4]: MayLoad 639f9691c0SRoman Lebedev# CHECK-NEXT: [5]: MayStore 649f9691c0SRoman Lebedev# CHECK-NEXT: [6]: HasSideEffects (U) 659f9691c0SRoman Lebedev 669f9691c0SRoman Lebedev# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 679f9691c0SRoman Lebedev# CHECK-NEXT: 1 1 1.00 * movb %spl, (%rax) 689f9691c0SRoman Lebedev# CHECK-NEXT: 1 5 0.50 * movb (%rcx), %bpl 699f9691c0SRoman Lebedev# CHECK-NEXT: 1 5 0.50 * movb (%rdx), %sil 709f9691c0SRoman Lebedev# CHECK-NEXT: 1 1 1.00 * movb %dil, (%rbx) 719f9691c0SRoman Lebedev 729f9691c0SRoman Lebedev# CHECK: Dynamic Dispatch Stall Cycles: 739f9691c0SRoman Lebedev# CHECK-NEXT: RAT - Register unavailable: 0 749f9691c0SRoman Lebedev# CHECK-NEXT: RCU - Retire tokens unavailable: 0 755578ec32SAndrea Di Biagio# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (71.0%) 769f9691c0SRoman Lebedev# CHECK-NEXT: LQ - Load queue full: 0 779f9691c0SRoman Lebedev# CHECK-NEXT: SQ - Store queue full: 0 789f9691c0SRoman Lebedev# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 79*f0658c7aSAndrea Di Biagio# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0 809f9691c0SRoman Lebedev 819f9691c0SRoman Lebedev# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: 829f9691c0SRoman Lebedev# CHECK-NEXT: [# dispatched], [# cycles] 835578ec32SAndrea Di Biagio# CHECK-NEXT: 0, 33 (15.9%) 845578ec32SAndrea Di Biagio# CHECK-NEXT: 2, 148 (71.5%) 855578ec32SAndrea Di Biagio# CHECK-NEXT: 4, 26 (12.6%) 869f9691c0SRoman Lebedev 879f9691c0SRoman Lebedev# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: 889f9691c0SRoman Lebedev# CHECK-NEXT: [# issued], [# cycles] 895578ec32SAndrea Di Biagio# CHECK-NEXT: 0, 7 (3.4%) 905578ec32SAndrea Di Biagio# CHECK-NEXT: 2, 200 (96.6%) 919f9691c0SRoman Lebedev 929f9691c0SRoman Lebedev# CHECK: Scheduler's queue usage: 939f9691c0SRoman Lebedev# CHECK-NEXT: [1] Resource name. 949f9691c0SRoman Lebedev# CHECK-NEXT: [2] Average number of used buffer entries. 959f9691c0SRoman Lebedev# CHECK-NEXT: [3] Maximum number of used buffer entries. 969f9691c0SRoman Lebedev# CHECK-NEXT: [4] Total number of buffer entries. 979f9691c0SRoman Lebedev 989f9691c0SRoman Lebedev# CHECK: [1] [2] [3] [4] 999f9691c0SRoman Lebedev# CHECK-NEXT: SBPortAny 45 54 54 1009f9691c0SRoman Lebedev 1019f9691c0SRoman Lebedev# CHECK: Resources: 1029f9691c0SRoman Lebedev# CHECK-NEXT: [0] - SBDivider 1039f9691c0SRoman Lebedev# CHECK-NEXT: [1] - SBFPDivider 1049f9691c0SRoman Lebedev# CHECK-NEXT: [2] - SBPort0 1059f9691c0SRoman Lebedev# CHECK-NEXT: [3] - SBPort1 1069f9691c0SRoman Lebedev# CHECK-NEXT: [4] - SBPort4 1079f9691c0SRoman Lebedev# CHECK-NEXT: [5] - SBPort5 1089f9691c0SRoman Lebedev# CHECK-NEXT: [6.0] - SBPort23 1099f9691c0SRoman Lebedev# CHECK-NEXT: [6.1] - SBPort23 1109f9691c0SRoman Lebedev 1119f9691c0SRoman Lebedev# CHECK: Resource pressure per iteration: 1129f9691c0SRoman Lebedev# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] 1139f9691c0SRoman Lebedev# CHECK-NEXT: - - - - 2.00 - 2.00 2.00 1149f9691c0SRoman Lebedev 1159f9691c0SRoman Lebedev# CHECK: Resource pressure by instruction: 1169f9691c0SRoman Lebedev# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: 1179f9691c0SRoman Lebedev# CHECK-NEXT: - - - - 1.00 - - 1.00 movb %spl, (%rax) 1189f9691c0SRoman Lebedev# CHECK-NEXT: - - - - - - 1.00 - movb (%rcx), %bpl 1195578ec32SAndrea Di Biagio# CHECK-NEXT: - - - - - - - 1.00 movb (%rdx), %sil 1205578ec32SAndrea Di Biagio# CHECK-NEXT: - - - - 1.00 - 1.00 - movb %dil, (%rbx) 1219f9691c0SRoman Lebedev 1229f9691c0SRoman Lebedev# CHECK: Timeline view: 1235578ec32SAndrea Di Biagio# CHECK-NEXT: Index 012345678 1249f9691c0SRoman Lebedev 1259f9691c0SRoman Lebedev# CHECK: [0,0] DeER . . movb %spl, (%rax) 1269f9691c0SRoman Lebedev# CHECK-NEXT: [0,1] DeeeeeER. movb (%rcx), %bpl 1275578ec32SAndrea Di Biagio# CHECK-NEXT: [0,2] D=eeeeeER movb (%rdx), %sil 1285578ec32SAndrea Di Biagio# CHECK-NEXT: [0,3] D=eE----R movb %dil, (%rbx) 1299f9691c0SRoman Lebedev 1309f9691c0SRoman Lebedev# CHECK: Average Wait times (based on the timeline view): 1319f9691c0SRoman Lebedev# CHECK-NEXT: [0]: Executions 1329f9691c0SRoman Lebedev# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue 1339f9691c0SRoman Lebedev# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready 1349f9691c0SRoman Lebedev# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage 1359f9691c0SRoman Lebedev 1369f9691c0SRoman Lebedev# CHECK: [0] [1] [2] [3] 1379f9691c0SRoman Lebedev# CHECK-NEXT: 0. 1 1.0 1.0 0.0 movb %spl, (%rax) 1389f9691c0SRoman Lebedev# CHECK-NEXT: 1. 1 1.0 1.0 0.0 movb (%rcx), %bpl 1399f9691c0SRoman Lebedev# CHECK-NEXT: 2. 1 2.0 2.0 0.0 movb (%rdx), %sil 1405578ec32SAndrea Di Biagio# CHECK-NEXT: 3. 1 2.0 0.0 4.0 movb %dil, (%rbx) 1415578ec32SAndrea Di Biagio# CHECK-NEXT: 1 1.5 1.0 1.0 <total> 1429f9691c0SRoman Lebedev 1439f9691c0SRoman Lebedev# CHECK: [1] Code Region 1449f9691c0SRoman Lebedev 1459f9691c0SRoman Lebedev# CHECK: Iterations: 100 1469f9691c0SRoman Lebedev# CHECK-NEXT: Instructions: 400 1475578ec32SAndrea Di Biagio# CHECK-NEXT: Total Cycles: 207 1489f9691c0SRoman Lebedev# CHECK-NEXT: Total uOps: 400 1499f9691c0SRoman Lebedev 1509f9691c0SRoman Lebedev# CHECK: Dispatch Width: 4 1515578ec32SAndrea Di Biagio# CHECK-NEXT: uOps Per Cycle: 1.93 1525578ec32SAndrea Di Biagio# CHECK-NEXT: IPC: 1.93 1539f9691c0SRoman Lebedev# CHECK-NEXT: Block RThroughput: 2.0 1549f9691c0SRoman Lebedev 1559f9691c0SRoman Lebedev# CHECK: Instruction Info: 1569f9691c0SRoman Lebedev# CHECK-NEXT: [1]: #uOps 1579f9691c0SRoman Lebedev# CHECK-NEXT: [2]: Latency 1589f9691c0SRoman Lebedev# CHECK-NEXT: [3]: RThroughput 1599f9691c0SRoman Lebedev# CHECK-NEXT: [4]: MayLoad 1609f9691c0SRoman Lebedev# CHECK-NEXT: [5]: MayStore 1619f9691c0SRoman Lebedev# CHECK-NEXT: [6]: HasSideEffects (U) 1629f9691c0SRoman Lebedev 1639f9691c0SRoman Lebedev# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 1649f9691c0SRoman Lebedev# CHECK-NEXT: 1 1 1.00 * movw %sp, (%rax) 1659f9691c0SRoman Lebedev# CHECK-NEXT: 1 5 0.50 * movw (%rcx), %bp 1669f9691c0SRoman Lebedev# CHECK-NEXT: 1 5 0.50 * movw (%rdx), %si 1679f9691c0SRoman Lebedev# CHECK-NEXT: 1 1 1.00 * movw %di, (%rbx) 1689f9691c0SRoman Lebedev 1699f9691c0SRoman Lebedev# CHECK: Dynamic Dispatch Stall Cycles: 1709f9691c0SRoman Lebedev# CHECK-NEXT: RAT - Register unavailable: 0 1719f9691c0SRoman Lebedev# CHECK-NEXT: RCU - Retire tokens unavailable: 0 1725578ec32SAndrea Di Biagio# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (71.0%) 1739f9691c0SRoman Lebedev# CHECK-NEXT: LQ - Load queue full: 0 1749f9691c0SRoman Lebedev# CHECK-NEXT: SQ - Store queue full: 0 1759f9691c0SRoman Lebedev# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 176*f0658c7aSAndrea Di Biagio# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0 1779f9691c0SRoman Lebedev 1789f9691c0SRoman Lebedev# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: 1799f9691c0SRoman Lebedev# CHECK-NEXT: [# dispatched], [# cycles] 1805578ec32SAndrea Di Biagio# CHECK-NEXT: 0, 33 (15.9%) 1815578ec32SAndrea Di Biagio# CHECK-NEXT: 2, 148 (71.5%) 1825578ec32SAndrea Di Biagio# CHECK-NEXT: 4, 26 (12.6%) 1839f9691c0SRoman Lebedev 1849f9691c0SRoman Lebedev# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: 1859f9691c0SRoman Lebedev# CHECK-NEXT: [# issued], [# cycles] 1865578ec32SAndrea Di Biagio# CHECK-NEXT: 0, 7 (3.4%) 1875578ec32SAndrea Di Biagio# CHECK-NEXT: 2, 200 (96.6%) 1889f9691c0SRoman Lebedev 1899f9691c0SRoman Lebedev# CHECK: Scheduler's queue usage: 1909f9691c0SRoman Lebedev# CHECK-NEXT: [1] Resource name. 1919f9691c0SRoman Lebedev# CHECK-NEXT: [2] Average number of used buffer entries. 1929f9691c0SRoman Lebedev# CHECK-NEXT: [3] Maximum number of used buffer entries. 1939f9691c0SRoman Lebedev# CHECK-NEXT: [4] Total number of buffer entries. 1949f9691c0SRoman Lebedev 1959f9691c0SRoman Lebedev# CHECK: [1] [2] [3] [4] 1969f9691c0SRoman Lebedev# CHECK-NEXT: SBPortAny 45 54 54 1979f9691c0SRoman Lebedev 1989f9691c0SRoman Lebedev# CHECK: Resources: 1999f9691c0SRoman Lebedev# CHECK-NEXT: [0] - SBDivider 2009f9691c0SRoman Lebedev# CHECK-NEXT: [1] - SBFPDivider 2019f9691c0SRoman Lebedev# CHECK-NEXT: [2] - SBPort0 2029f9691c0SRoman Lebedev# CHECK-NEXT: [3] - SBPort1 2039f9691c0SRoman Lebedev# CHECK-NEXT: [4] - SBPort4 2049f9691c0SRoman Lebedev# CHECK-NEXT: [5] - SBPort5 2059f9691c0SRoman Lebedev# CHECK-NEXT: [6.0] - SBPort23 2069f9691c0SRoman Lebedev# CHECK-NEXT: [6.1] - SBPort23 2079f9691c0SRoman Lebedev 2089f9691c0SRoman Lebedev# CHECK: Resource pressure per iteration: 2099f9691c0SRoman Lebedev# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] 2109f9691c0SRoman Lebedev# CHECK-NEXT: - - - - 2.00 - 2.00 2.00 2119f9691c0SRoman Lebedev 2129f9691c0SRoman Lebedev# CHECK: Resource pressure by instruction: 2139f9691c0SRoman Lebedev# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: 2149f9691c0SRoman Lebedev# CHECK-NEXT: - - - - 1.00 - - 1.00 movw %sp, (%rax) 2159f9691c0SRoman Lebedev# CHECK-NEXT: - - - - - - 1.00 - movw (%rcx), %bp 2165578ec32SAndrea Di Biagio# CHECK-NEXT: - - - - - - - 1.00 movw (%rdx), %si 2175578ec32SAndrea Di Biagio# CHECK-NEXT: - - - - 1.00 - 1.00 - movw %di, (%rbx) 2189f9691c0SRoman Lebedev 2199f9691c0SRoman Lebedev# CHECK: Timeline view: 2205578ec32SAndrea Di Biagio# CHECK-NEXT: Index 012345678 2219f9691c0SRoman Lebedev 2229f9691c0SRoman Lebedev# CHECK: [0,0] DeER . . movw %sp, (%rax) 2239f9691c0SRoman Lebedev# CHECK-NEXT: [0,1] DeeeeeER. movw (%rcx), %bp 2245578ec32SAndrea Di Biagio# CHECK-NEXT: [0,2] D=eeeeeER movw (%rdx), %si 2255578ec32SAndrea Di Biagio# CHECK-NEXT: [0,3] D=eE----R movw %di, (%rbx) 2269f9691c0SRoman Lebedev 2279f9691c0SRoman Lebedev# CHECK: Average Wait times (based on the timeline view): 2289f9691c0SRoman Lebedev# CHECK-NEXT: [0]: Executions 2299f9691c0SRoman Lebedev# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue 2309f9691c0SRoman Lebedev# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready 2319f9691c0SRoman Lebedev# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage 2329f9691c0SRoman Lebedev 2339f9691c0SRoman Lebedev# CHECK: [0] [1] [2] [3] 2349f9691c0SRoman Lebedev# CHECK-NEXT: 0. 1 1.0 1.0 0.0 movw %sp, (%rax) 2359f9691c0SRoman Lebedev# CHECK-NEXT: 1. 1 1.0 1.0 0.0 movw (%rcx), %bp 2369f9691c0SRoman Lebedev# CHECK-NEXT: 2. 1 2.0 2.0 0.0 movw (%rdx), %si 2375578ec32SAndrea Di Biagio# CHECK-NEXT: 3. 1 2.0 0.0 4.0 movw %di, (%rbx) 2385578ec32SAndrea Di Biagio# CHECK-NEXT: 1 1.5 1.0 1.0 <total> 2399f9691c0SRoman Lebedev 2409f9691c0SRoman Lebedev# CHECK: [2] Code Region 2419f9691c0SRoman Lebedev 2429f9691c0SRoman Lebedev# CHECK: Iterations: 100 2439f9691c0SRoman Lebedev# CHECK-NEXT: Instructions: 400 2445578ec32SAndrea Di Biagio# CHECK-NEXT: Total Cycles: 207 2459f9691c0SRoman Lebedev# CHECK-NEXT: Total uOps: 400 2469f9691c0SRoman Lebedev 2479f9691c0SRoman Lebedev# CHECK: Dispatch Width: 4 2485578ec32SAndrea Di Biagio# CHECK-NEXT: uOps Per Cycle: 1.93 2495578ec32SAndrea Di Biagio# CHECK-NEXT: IPC: 1.93 2509f9691c0SRoman Lebedev# CHECK-NEXT: Block RThroughput: 2.0 2519f9691c0SRoman Lebedev 2529f9691c0SRoman Lebedev# CHECK: Instruction Info: 2539f9691c0SRoman Lebedev# CHECK-NEXT: [1]: #uOps 2549f9691c0SRoman Lebedev# CHECK-NEXT: [2]: Latency 2559f9691c0SRoman Lebedev# CHECK-NEXT: [3]: RThroughput 2569f9691c0SRoman Lebedev# CHECK-NEXT: [4]: MayLoad 2579f9691c0SRoman Lebedev# CHECK-NEXT: [5]: MayStore 2589f9691c0SRoman Lebedev# CHECK-NEXT: [6]: HasSideEffects (U) 2599f9691c0SRoman Lebedev 2609f9691c0SRoman Lebedev# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 2619f9691c0SRoman Lebedev# CHECK-NEXT: 1 1 1.00 * movl %esp, (%rax) 2629f9691c0SRoman Lebedev# CHECK-NEXT: 1 5 0.50 * movl (%rcx), %ebp 2639f9691c0SRoman Lebedev# CHECK-NEXT: 1 5 0.50 * movl (%rdx), %esi 2649f9691c0SRoman Lebedev# CHECK-NEXT: 1 1 1.00 * movl %edi, (%rbx) 2659f9691c0SRoman Lebedev 2669f9691c0SRoman Lebedev# CHECK: Dynamic Dispatch Stall Cycles: 2679f9691c0SRoman Lebedev# CHECK-NEXT: RAT - Register unavailable: 0 2689f9691c0SRoman Lebedev# CHECK-NEXT: RCU - Retire tokens unavailable: 0 2695578ec32SAndrea Di Biagio# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (71.0%) 2709f9691c0SRoman Lebedev# CHECK-NEXT: LQ - Load queue full: 0 2719f9691c0SRoman Lebedev# CHECK-NEXT: SQ - Store queue full: 0 2729f9691c0SRoman Lebedev# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 273*f0658c7aSAndrea Di Biagio# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0 2749f9691c0SRoman Lebedev 2759f9691c0SRoman Lebedev# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: 2769f9691c0SRoman Lebedev# CHECK-NEXT: [# dispatched], [# cycles] 2775578ec32SAndrea Di Biagio# CHECK-NEXT: 0, 33 (15.9%) 2785578ec32SAndrea Di Biagio# CHECK-NEXT: 2, 148 (71.5%) 2795578ec32SAndrea Di Biagio# CHECK-NEXT: 4, 26 (12.6%) 2809f9691c0SRoman Lebedev 2819f9691c0SRoman Lebedev# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: 2829f9691c0SRoman Lebedev# CHECK-NEXT: [# issued], [# cycles] 2835578ec32SAndrea Di Biagio# CHECK-NEXT: 0, 7 (3.4%) 2845578ec32SAndrea Di Biagio# CHECK-NEXT: 2, 200 (96.6%) 2859f9691c0SRoman Lebedev 2869f9691c0SRoman Lebedev# CHECK: Scheduler's queue usage: 2879f9691c0SRoman Lebedev# CHECK-NEXT: [1] Resource name. 2889f9691c0SRoman Lebedev# CHECK-NEXT: [2] Average number of used buffer entries. 2899f9691c0SRoman Lebedev# CHECK-NEXT: [3] Maximum number of used buffer entries. 2909f9691c0SRoman Lebedev# CHECK-NEXT: [4] Total number of buffer entries. 2919f9691c0SRoman Lebedev 2929f9691c0SRoman Lebedev# CHECK: [1] [2] [3] [4] 2939f9691c0SRoman Lebedev# CHECK-NEXT: SBPortAny 45 54 54 2949f9691c0SRoman Lebedev 2959f9691c0SRoman Lebedev# CHECK: Resources: 2969f9691c0SRoman Lebedev# CHECK-NEXT: [0] - SBDivider 2979f9691c0SRoman Lebedev# CHECK-NEXT: [1] - SBFPDivider 2989f9691c0SRoman Lebedev# CHECK-NEXT: [2] - SBPort0 2999f9691c0SRoman Lebedev# CHECK-NEXT: [3] - SBPort1 3009f9691c0SRoman Lebedev# CHECK-NEXT: [4] - SBPort4 3019f9691c0SRoman Lebedev# CHECK-NEXT: [5] - SBPort5 3029f9691c0SRoman Lebedev# CHECK-NEXT: [6.0] - SBPort23 3039f9691c0SRoman Lebedev# CHECK-NEXT: [6.1] - SBPort23 3049f9691c0SRoman Lebedev 3059f9691c0SRoman Lebedev# CHECK: Resource pressure per iteration: 3069f9691c0SRoman Lebedev# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] 3079f9691c0SRoman Lebedev# CHECK-NEXT: - - - - 2.00 - 2.00 2.00 3089f9691c0SRoman Lebedev 3099f9691c0SRoman Lebedev# CHECK: Resource pressure by instruction: 3109f9691c0SRoman Lebedev# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: 3119f9691c0SRoman Lebedev# CHECK-NEXT: - - - - 1.00 - - 1.00 movl %esp, (%rax) 3129f9691c0SRoman Lebedev# CHECK-NEXT: - - - - - - 1.00 - movl (%rcx), %ebp 3135578ec32SAndrea Di Biagio# CHECK-NEXT: - - - - - - - 1.00 movl (%rdx), %esi 3145578ec32SAndrea Di Biagio# CHECK-NEXT: - - - - 1.00 - 1.00 - movl %edi, (%rbx) 3159f9691c0SRoman Lebedev 3169f9691c0SRoman Lebedev# CHECK: Timeline view: 3175578ec32SAndrea Di Biagio# CHECK-NEXT: Index 012345678 3189f9691c0SRoman Lebedev 3199f9691c0SRoman Lebedev# CHECK: [0,0] DeER . . movl %esp, (%rax) 3209f9691c0SRoman Lebedev# CHECK-NEXT: [0,1] DeeeeeER. movl (%rcx), %ebp 3215578ec32SAndrea Di Biagio# CHECK-NEXT: [0,2] D=eeeeeER movl (%rdx), %esi 3225578ec32SAndrea Di Biagio# CHECK-NEXT: [0,3] D=eE----R movl %edi, (%rbx) 3239f9691c0SRoman Lebedev 3249f9691c0SRoman Lebedev# CHECK: Average Wait times (based on the timeline view): 3259f9691c0SRoman Lebedev# CHECK-NEXT: [0]: Executions 3269f9691c0SRoman Lebedev# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue 3279f9691c0SRoman Lebedev# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready 3289f9691c0SRoman Lebedev# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage 3299f9691c0SRoman Lebedev 3309f9691c0SRoman Lebedev# CHECK: [0] [1] [2] [3] 3319f9691c0SRoman Lebedev# CHECK-NEXT: 0. 1 1.0 1.0 0.0 movl %esp, (%rax) 3329f9691c0SRoman Lebedev# CHECK-NEXT: 1. 1 1.0 1.0 0.0 movl (%rcx), %ebp 3339f9691c0SRoman Lebedev# CHECK-NEXT: 2. 1 2.0 2.0 0.0 movl (%rdx), %esi 3345578ec32SAndrea Di Biagio# CHECK-NEXT: 3. 1 2.0 0.0 4.0 movl %edi, (%rbx) 3355578ec32SAndrea Di Biagio# CHECK-NEXT: 1 1.5 1.0 1.0 <total> 3369f9691c0SRoman Lebedev 3379f9691c0SRoman Lebedev# CHECK: [3] Code Region 3389f9691c0SRoman Lebedev 3399f9691c0SRoman Lebedev# CHECK: Iterations: 100 3409f9691c0SRoman Lebedev# CHECK-NEXT: Instructions: 400 3415578ec32SAndrea Di Biagio# CHECK-NEXT: Total Cycles: 207 3429f9691c0SRoman Lebedev# CHECK-NEXT: Total uOps: 400 3439f9691c0SRoman Lebedev 3449f9691c0SRoman Lebedev# CHECK: Dispatch Width: 4 3455578ec32SAndrea Di Biagio# CHECK-NEXT: uOps Per Cycle: 1.93 3465578ec32SAndrea Di Biagio# CHECK-NEXT: IPC: 1.93 3479f9691c0SRoman Lebedev# CHECK-NEXT: Block RThroughput: 2.0 3489f9691c0SRoman Lebedev 3499f9691c0SRoman Lebedev# CHECK: Instruction Info: 3509f9691c0SRoman Lebedev# CHECK-NEXT: [1]: #uOps 3519f9691c0SRoman Lebedev# CHECK-NEXT: [2]: Latency 3529f9691c0SRoman Lebedev# CHECK-NEXT: [3]: RThroughput 3539f9691c0SRoman Lebedev# CHECK-NEXT: [4]: MayLoad 3549f9691c0SRoman Lebedev# CHECK-NEXT: [5]: MayStore 3559f9691c0SRoman Lebedev# CHECK-NEXT: [6]: HasSideEffects (U) 3569f9691c0SRoman Lebedev 3579f9691c0SRoman Lebedev# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 3589f9691c0SRoman Lebedev# CHECK-NEXT: 1 1 1.00 * movq %rsp, (%rax) 3599f9691c0SRoman Lebedev# CHECK-NEXT: 1 5 0.50 * movq (%rcx), %rbp 3609f9691c0SRoman Lebedev# CHECK-NEXT: 1 5 0.50 * movq (%rdx), %rsi 3619f9691c0SRoman Lebedev# CHECK-NEXT: 1 1 1.00 * movq %rdi, (%rbx) 3629f9691c0SRoman Lebedev 3639f9691c0SRoman Lebedev# CHECK: Dynamic Dispatch Stall Cycles: 3649f9691c0SRoman Lebedev# CHECK-NEXT: RAT - Register unavailable: 0 3659f9691c0SRoman Lebedev# CHECK-NEXT: RCU - Retire tokens unavailable: 0 3665578ec32SAndrea Di Biagio# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (71.0%) 3679f9691c0SRoman Lebedev# CHECK-NEXT: LQ - Load queue full: 0 3689f9691c0SRoman Lebedev# CHECK-NEXT: SQ - Store queue full: 0 3699f9691c0SRoman Lebedev# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 370*f0658c7aSAndrea Di Biagio# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0 3719f9691c0SRoman Lebedev 3729f9691c0SRoman Lebedev# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: 3739f9691c0SRoman Lebedev# CHECK-NEXT: [# dispatched], [# cycles] 3745578ec32SAndrea Di Biagio# CHECK-NEXT: 0, 33 (15.9%) 3755578ec32SAndrea Di Biagio# CHECK-NEXT: 2, 148 (71.5%) 3765578ec32SAndrea Di Biagio# CHECK-NEXT: 4, 26 (12.6%) 3779f9691c0SRoman Lebedev 3789f9691c0SRoman Lebedev# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: 3799f9691c0SRoman Lebedev# CHECK-NEXT: [# issued], [# cycles] 3805578ec32SAndrea Di Biagio# CHECK-NEXT: 0, 7 (3.4%) 3815578ec32SAndrea Di Biagio# CHECK-NEXT: 2, 200 (96.6%) 3829f9691c0SRoman Lebedev 3839f9691c0SRoman Lebedev# CHECK: Scheduler's queue usage: 3849f9691c0SRoman Lebedev# CHECK-NEXT: [1] Resource name. 3859f9691c0SRoman Lebedev# CHECK-NEXT: [2] Average number of used buffer entries. 3869f9691c0SRoman Lebedev# CHECK-NEXT: [3] Maximum number of used buffer entries. 3879f9691c0SRoman Lebedev# CHECK-NEXT: [4] Total number of buffer entries. 3889f9691c0SRoman Lebedev 3899f9691c0SRoman Lebedev# CHECK: [1] [2] [3] [4] 3909f9691c0SRoman Lebedev# CHECK-NEXT: SBPortAny 45 54 54 3919f9691c0SRoman Lebedev 3929f9691c0SRoman Lebedev# CHECK: Resources: 3939f9691c0SRoman Lebedev# CHECK-NEXT: [0] - SBDivider 3949f9691c0SRoman Lebedev# CHECK-NEXT: [1] - SBFPDivider 3959f9691c0SRoman Lebedev# CHECK-NEXT: [2] - SBPort0 3969f9691c0SRoman Lebedev# CHECK-NEXT: [3] - SBPort1 3979f9691c0SRoman Lebedev# CHECK-NEXT: [4] - SBPort4 3989f9691c0SRoman Lebedev# CHECK-NEXT: [5] - SBPort5 3999f9691c0SRoman Lebedev# CHECK-NEXT: [6.0] - SBPort23 4009f9691c0SRoman Lebedev# CHECK-NEXT: [6.1] - SBPort23 4019f9691c0SRoman Lebedev 4029f9691c0SRoman Lebedev# CHECK: Resource pressure per iteration: 4039f9691c0SRoman Lebedev# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] 4049f9691c0SRoman Lebedev# CHECK-NEXT: - - - - 2.00 - 2.00 2.00 4059f9691c0SRoman Lebedev 4069f9691c0SRoman Lebedev# CHECK: Resource pressure by instruction: 4079f9691c0SRoman Lebedev# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: 4089f9691c0SRoman Lebedev# CHECK-NEXT: - - - - 1.00 - - 1.00 movq %rsp, (%rax) 4099f9691c0SRoman Lebedev# CHECK-NEXT: - - - - - - 1.00 - movq (%rcx), %rbp 4105578ec32SAndrea Di Biagio# CHECK-NEXT: - - - - - - - 1.00 movq (%rdx), %rsi 4115578ec32SAndrea Di Biagio# CHECK-NEXT: - - - - 1.00 - 1.00 - movq %rdi, (%rbx) 4129f9691c0SRoman Lebedev 4139f9691c0SRoman Lebedev# CHECK: Timeline view: 4145578ec32SAndrea Di Biagio# CHECK-NEXT: Index 012345678 4159f9691c0SRoman Lebedev 4169f9691c0SRoman Lebedev# CHECK: [0,0] DeER . . movq %rsp, (%rax) 4179f9691c0SRoman Lebedev# CHECK-NEXT: [0,1] DeeeeeER. movq (%rcx), %rbp 4185578ec32SAndrea Di Biagio# CHECK-NEXT: [0,2] D=eeeeeER movq (%rdx), %rsi 4195578ec32SAndrea Di Biagio# CHECK-NEXT: [0,3] D=eE----R movq %rdi, (%rbx) 4209f9691c0SRoman Lebedev 4219f9691c0SRoman Lebedev# CHECK: Average Wait times (based on the timeline view): 4229f9691c0SRoman Lebedev# CHECK-NEXT: [0]: Executions 4239f9691c0SRoman Lebedev# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue 4249f9691c0SRoman Lebedev# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready 4259f9691c0SRoman Lebedev# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage 4269f9691c0SRoman Lebedev 4279f9691c0SRoman Lebedev# CHECK: [0] [1] [2] [3] 4289f9691c0SRoman Lebedev# CHECK-NEXT: 0. 1 1.0 1.0 0.0 movq %rsp, (%rax) 4299f9691c0SRoman Lebedev# CHECK-NEXT: 1. 1 1.0 1.0 0.0 movq (%rcx), %rbp 4309f9691c0SRoman Lebedev# CHECK-NEXT: 2. 1 2.0 2.0 0.0 movq (%rdx), %rsi 4315578ec32SAndrea Di Biagio# CHECK-NEXT: 3. 1 2.0 0.0 4.0 movq %rdi, (%rbx) 4325578ec32SAndrea Di Biagio# CHECK-NEXT: 1 1.5 1.0 1.0 <total> 4339f9691c0SRoman Lebedev 4349f9691c0SRoman Lebedev# CHECK: [4] Code Region 4359f9691c0SRoman Lebedev 4369f9691c0SRoman Lebedev# CHECK: Iterations: 100 4379f9691c0SRoman Lebedev# CHECK-NEXT: Instructions: 400 4385578ec32SAndrea Di Biagio# CHECK-NEXT: Total Cycles: 207 4399f9691c0SRoman Lebedev# CHECK-NEXT: Total uOps: 400 4409f9691c0SRoman Lebedev 4419f9691c0SRoman Lebedev# CHECK: Dispatch Width: 4 4425578ec32SAndrea Di Biagio# CHECK-NEXT: uOps Per Cycle: 1.93 4435578ec32SAndrea Di Biagio# CHECK-NEXT: IPC: 1.93 4449f9691c0SRoman Lebedev# CHECK-NEXT: Block RThroughput: 2.0 4459f9691c0SRoman Lebedev 4469f9691c0SRoman Lebedev# CHECK: Instruction Info: 4479f9691c0SRoman Lebedev# CHECK-NEXT: [1]: #uOps 4489f9691c0SRoman Lebedev# CHECK-NEXT: [2]: Latency 4499f9691c0SRoman Lebedev# CHECK-NEXT: [3]: RThroughput 4509f9691c0SRoman Lebedev# CHECK-NEXT: [4]: MayLoad 4519f9691c0SRoman Lebedev# CHECK-NEXT: [5]: MayStore 4529f9691c0SRoman Lebedev# CHECK-NEXT: [6]: HasSideEffects (U) 4539f9691c0SRoman Lebedev 4549f9691c0SRoman Lebedev# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 4559f9691c0SRoman Lebedev# CHECK-NEXT: 1 1 1.00 * U movd %mm0, (%rax) 4569f9691c0SRoman Lebedev# CHECK-NEXT: 1 5 0.50 * movd (%rcx), %mm1 4579f9691c0SRoman Lebedev# CHECK-NEXT: 1 5 0.50 * movd (%rdx), %mm2 4589f9691c0SRoman Lebedev# CHECK-NEXT: 1 1 1.00 * U movd %mm3, (%rbx) 4599f9691c0SRoman Lebedev 4609f9691c0SRoman Lebedev# CHECK: Dynamic Dispatch Stall Cycles: 4619f9691c0SRoman Lebedev# CHECK-NEXT: RAT - Register unavailable: 0 4629f9691c0SRoman Lebedev# CHECK-NEXT: RCU - Retire tokens unavailable: 0 4635578ec32SAndrea Di Biagio# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (71.0%) 4649f9691c0SRoman Lebedev# CHECK-NEXT: LQ - Load queue full: 0 4659f9691c0SRoman Lebedev# CHECK-NEXT: SQ - Store queue full: 0 4669f9691c0SRoman Lebedev# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 467*f0658c7aSAndrea Di Biagio# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0 4689f9691c0SRoman Lebedev 4699f9691c0SRoman Lebedev# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: 4709f9691c0SRoman Lebedev# CHECK-NEXT: [# dispatched], [# cycles] 4715578ec32SAndrea Di Biagio# CHECK-NEXT: 0, 33 (15.9%) 4725578ec32SAndrea Di Biagio# CHECK-NEXT: 2, 148 (71.5%) 4735578ec32SAndrea Di Biagio# CHECK-NEXT: 4, 26 (12.6%) 4749f9691c0SRoman Lebedev 4759f9691c0SRoman Lebedev# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: 4769f9691c0SRoman Lebedev# CHECK-NEXT: [# issued], [# cycles] 4775578ec32SAndrea Di Biagio# CHECK-NEXT: 0, 7 (3.4%) 4785578ec32SAndrea Di Biagio# CHECK-NEXT: 2, 200 (96.6%) 4799f9691c0SRoman Lebedev 4809f9691c0SRoman Lebedev# CHECK: Scheduler's queue usage: 4819f9691c0SRoman Lebedev# CHECK-NEXT: [1] Resource name. 4829f9691c0SRoman Lebedev# CHECK-NEXT: [2] Average number of used buffer entries. 4839f9691c0SRoman Lebedev# CHECK-NEXT: [3] Maximum number of used buffer entries. 4849f9691c0SRoman Lebedev# CHECK-NEXT: [4] Total number of buffer entries. 4859f9691c0SRoman Lebedev 4869f9691c0SRoman Lebedev# CHECK: [1] [2] [3] [4] 4879f9691c0SRoman Lebedev# CHECK-NEXT: SBPortAny 45 54 54 4889f9691c0SRoman Lebedev 4899f9691c0SRoman Lebedev# CHECK: Resources: 4909f9691c0SRoman Lebedev# CHECK-NEXT: [0] - SBDivider 4919f9691c0SRoman Lebedev# CHECK-NEXT: [1] - SBFPDivider 4929f9691c0SRoman Lebedev# CHECK-NEXT: [2] - SBPort0 4939f9691c0SRoman Lebedev# CHECK-NEXT: [3] - SBPort1 4949f9691c0SRoman Lebedev# CHECK-NEXT: [4] - SBPort4 4959f9691c0SRoman Lebedev# CHECK-NEXT: [5] - SBPort5 4969f9691c0SRoman Lebedev# CHECK-NEXT: [6.0] - SBPort23 4979f9691c0SRoman Lebedev# CHECK-NEXT: [6.1] - SBPort23 4989f9691c0SRoman Lebedev 4999f9691c0SRoman Lebedev# CHECK: Resource pressure per iteration: 5009f9691c0SRoman Lebedev# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] 5019f9691c0SRoman Lebedev# CHECK-NEXT: - - - - 2.00 - 2.00 2.00 5029f9691c0SRoman Lebedev 5039f9691c0SRoman Lebedev# CHECK: Resource pressure by instruction: 5049f9691c0SRoman Lebedev# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: 5059f9691c0SRoman Lebedev# CHECK-NEXT: - - - - 1.00 - - 1.00 movd %mm0, (%rax) 5069f9691c0SRoman Lebedev# CHECK-NEXT: - - - - - - 1.00 - movd (%rcx), %mm1 5075578ec32SAndrea Di Biagio# CHECK-NEXT: - - - - - - - 1.00 movd (%rdx), %mm2 5085578ec32SAndrea Di Biagio# CHECK-NEXT: - - - - 1.00 - 1.00 - movd %mm3, (%rbx) 5099f9691c0SRoman Lebedev 5109f9691c0SRoman Lebedev# CHECK: Timeline view: 5115578ec32SAndrea Di Biagio# CHECK-NEXT: Index 012345678 5129f9691c0SRoman Lebedev 5139f9691c0SRoman Lebedev# CHECK: [0,0] DeER . . movd %mm0, (%rax) 5149f9691c0SRoman Lebedev# CHECK-NEXT: [0,1] DeeeeeER. movd (%rcx), %mm1 5155578ec32SAndrea Di Biagio# CHECK-NEXT: [0,2] D=eeeeeER movd (%rdx), %mm2 5165578ec32SAndrea Di Biagio# CHECK-NEXT: [0,3] D=eE----R movd %mm3, (%rbx) 5179f9691c0SRoman Lebedev 5189f9691c0SRoman Lebedev# CHECK: Average Wait times (based on the timeline view): 5199f9691c0SRoman Lebedev# CHECK-NEXT: [0]: Executions 5209f9691c0SRoman Lebedev# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue 5219f9691c0SRoman Lebedev# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready 5229f9691c0SRoman Lebedev# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage 5239f9691c0SRoman Lebedev 5249f9691c0SRoman Lebedev# CHECK: [0] [1] [2] [3] 5259f9691c0SRoman Lebedev# CHECK-NEXT: 0. 1 1.0 1.0 0.0 movd %mm0, (%rax) 5269f9691c0SRoman Lebedev# CHECK-NEXT: 1. 1 1.0 1.0 0.0 movd (%rcx), %mm1 5279f9691c0SRoman Lebedev# CHECK-NEXT: 2. 1 2.0 2.0 0.0 movd (%rdx), %mm2 5285578ec32SAndrea Di Biagio# CHECK-NEXT: 3. 1 2.0 0.0 4.0 movd %mm3, (%rbx) 5295578ec32SAndrea Di Biagio# CHECK-NEXT: 1 1.5 1.0 1.0 <total> 5309f9691c0SRoman Lebedev 5319f9691c0SRoman Lebedev# CHECK: [5] Code Region 5329f9691c0SRoman Lebedev 5339f9691c0SRoman Lebedev# CHECK: Iterations: 100 5349f9691c0SRoman Lebedev# CHECK-NEXT: Instructions: 400 5355578ec32SAndrea Di Biagio# CHECK-NEXT: Total Cycles: 208 5369f9691c0SRoman Lebedev# CHECK-NEXT: Total uOps: 400 5379f9691c0SRoman Lebedev 5389f9691c0SRoman Lebedev# CHECK: Dispatch Width: 4 5395578ec32SAndrea Di Biagio# CHECK-NEXT: uOps Per Cycle: 1.92 5405578ec32SAndrea Di Biagio# CHECK-NEXT: IPC: 1.92 5419f9691c0SRoman Lebedev# CHECK-NEXT: Block RThroughput: 2.0 5429f9691c0SRoman Lebedev 5439f9691c0SRoman Lebedev# CHECK: Instruction Info: 5449f9691c0SRoman Lebedev# CHECK-NEXT: [1]: #uOps 5459f9691c0SRoman Lebedev# CHECK-NEXT: [2]: Latency 5469f9691c0SRoman Lebedev# CHECK-NEXT: [3]: RThroughput 5479f9691c0SRoman Lebedev# CHECK-NEXT: [4]: MayLoad 5489f9691c0SRoman Lebedev# CHECK-NEXT: [5]: MayStore 5499f9691c0SRoman Lebedev# CHECK-NEXT: [6]: HasSideEffects (U) 5509f9691c0SRoman Lebedev 5519f9691c0SRoman Lebedev# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 5529f9691c0SRoman Lebedev# CHECK-NEXT: 1 1 1.00 * movaps %xmm0, (%rax) 5539f9691c0SRoman Lebedev# CHECK-NEXT: 1 6 0.50 * movaps (%rcx), %xmm1 5549f9691c0SRoman Lebedev# CHECK-NEXT: 1 6 0.50 * movaps (%rdx), %xmm2 5559f9691c0SRoman Lebedev# CHECK-NEXT: 1 1 1.00 * movaps %xmm3, (%rbx) 5569f9691c0SRoman Lebedev 5579f9691c0SRoman Lebedev# CHECK: Dynamic Dispatch Stall Cycles: 5589f9691c0SRoman Lebedev# CHECK-NEXT: RAT - Register unavailable: 0 5599f9691c0SRoman Lebedev# CHECK-NEXT: RCU - Retire tokens unavailable: 0 5605578ec32SAndrea Di Biagio# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (70.7%) 5619f9691c0SRoman Lebedev# CHECK-NEXT: LQ - Load queue full: 0 5629f9691c0SRoman Lebedev# CHECK-NEXT: SQ - Store queue full: 0 5639f9691c0SRoman Lebedev# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 564*f0658c7aSAndrea Di Biagio# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0 5659f9691c0SRoman Lebedev 5669f9691c0SRoman Lebedev# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: 5679f9691c0SRoman Lebedev# CHECK-NEXT: [# dispatched], [# cycles] 5685578ec32SAndrea Di Biagio# CHECK-NEXT: 0, 34 (16.3%) 5695578ec32SAndrea Di Biagio# CHECK-NEXT: 2, 148 (71.2%) 5705578ec32SAndrea Di Biagio# CHECK-NEXT: 4, 26 (12.5%) 5719f9691c0SRoman Lebedev 5729f9691c0SRoman Lebedev# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: 5739f9691c0SRoman Lebedev# CHECK-NEXT: [# issued], [# cycles] 5745578ec32SAndrea Di Biagio# CHECK-NEXT: 0, 8 (3.8%) 5755578ec32SAndrea Di Biagio# CHECK-NEXT: 2, 200 (96.2%) 5769f9691c0SRoman Lebedev 5779f9691c0SRoman Lebedev# CHECK: Scheduler's queue usage: 5789f9691c0SRoman Lebedev# CHECK-NEXT: [1] Resource name. 5799f9691c0SRoman Lebedev# CHECK-NEXT: [2] Average number of used buffer entries. 5809f9691c0SRoman Lebedev# CHECK-NEXT: [3] Maximum number of used buffer entries. 5819f9691c0SRoman Lebedev# CHECK-NEXT: [4] Total number of buffer entries. 5829f9691c0SRoman Lebedev 5839f9691c0SRoman Lebedev# CHECK: [1] [2] [3] [4] 5849f9691c0SRoman Lebedev# CHECK-NEXT: SBPortAny 45 54 54 5859f9691c0SRoman Lebedev 5869f9691c0SRoman Lebedev# CHECK: Resources: 5879f9691c0SRoman Lebedev# CHECK-NEXT: [0] - SBDivider 5889f9691c0SRoman Lebedev# CHECK-NEXT: [1] - SBFPDivider 5899f9691c0SRoman Lebedev# CHECK-NEXT: [2] - SBPort0 5909f9691c0SRoman Lebedev# CHECK-NEXT: [3] - SBPort1 5919f9691c0SRoman Lebedev# CHECK-NEXT: [4] - SBPort4 5929f9691c0SRoman Lebedev# CHECK-NEXT: [5] - SBPort5 5939f9691c0SRoman Lebedev# CHECK-NEXT: [6.0] - SBPort23 5949f9691c0SRoman Lebedev# CHECK-NEXT: [6.1] - SBPort23 5959f9691c0SRoman Lebedev 5969f9691c0SRoman Lebedev# CHECK: Resource pressure per iteration: 5979f9691c0SRoman Lebedev# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] 5989f9691c0SRoman Lebedev# CHECK-NEXT: - - - - 2.00 - 2.00 2.00 5999f9691c0SRoman Lebedev 6009f9691c0SRoman Lebedev# CHECK: Resource pressure by instruction: 6019f9691c0SRoman Lebedev# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: 6029f9691c0SRoman Lebedev# CHECK-NEXT: - - - - 1.00 - - 1.00 movaps %xmm0, (%rax) 6039f9691c0SRoman Lebedev# CHECK-NEXT: - - - - - - 1.00 - movaps (%rcx), %xmm1 6045578ec32SAndrea Di Biagio# CHECK-NEXT: - - - - - - - 1.00 movaps (%rdx), %xmm2 6055578ec32SAndrea Di Biagio# CHECK-NEXT: - - - - 1.00 - 1.00 - movaps %xmm3, (%rbx) 6069f9691c0SRoman Lebedev 6079f9691c0SRoman Lebedev# CHECK: Timeline view: 6089f9691c0SRoman Lebedev# CHECK-NEXT: Index 0123456789 6099f9691c0SRoman Lebedev 6109f9691c0SRoman Lebedev# CHECK: [0,0] DeER . . movaps %xmm0, (%rax) 6119f9691c0SRoman Lebedev# CHECK-NEXT: [0,1] DeeeeeeER. movaps (%rcx), %xmm1 6125578ec32SAndrea Di Biagio# CHECK-NEXT: [0,2] D=eeeeeeER movaps (%rdx), %xmm2 6135578ec32SAndrea Di Biagio# CHECK-NEXT: [0,3] D=eE-----R movaps %xmm3, (%rbx) 6149f9691c0SRoman Lebedev 6159f9691c0SRoman Lebedev# CHECK: Average Wait times (based on the timeline view): 6169f9691c0SRoman Lebedev# CHECK-NEXT: [0]: Executions 6179f9691c0SRoman Lebedev# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue 6189f9691c0SRoman Lebedev# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready 6199f9691c0SRoman Lebedev# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage 6209f9691c0SRoman Lebedev 6219f9691c0SRoman Lebedev# CHECK: [0] [1] [2] [3] 6229f9691c0SRoman Lebedev# CHECK-NEXT: 0. 1 1.0 1.0 0.0 movaps %xmm0, (%rax) 6239f9691c0SRoman Lebedev# CHECK-NEXT: 1. 1 1.0 1.0 0.0 movaps (%rcx), %xmm1 6249f9691c0SRoman Lebedev# CHECK-NEXT: 2. 1 2.0 2.0 0.0 movaps (%rdx), %xmm2 6255578ec32SAndrea Di Biagio# CHECK-NEXT: 3. 1 2.0 0.0 5.0 movaps %xmm3, (%rbx) 6265578ec32SAndrea Di Biagio# CHECK-NEXT: 1 1.5 1.0 1.3 <total> 627