12db4979cSQiu Chaofan; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2ad35d916SBen Shi; RUN: opt -S -passes=vector-combine -data-layout=e < %s | FileCheck %s 3ad35d916SBen Shi; RUN: opt -S -passes=vector-combine -data-layout=E < %s | FileCheck %s 42db4979cSQiu Chaofan 5c00ffbe0SNikita Popovdefine void @insert_store(ptr %q, i8 zeroext %s) { 62db4979cSQiu Chaofan; CHECK-LABEL: @insert_store( 72db4979cSQiu Chaofan; CHECK-NEXT: entry: 8c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, ptr [[Q:%.*]], i32 0, i32 3 9c00ffbe0SNikita Popov; CHECK-NEXT: store i8 [[S:%.*]], ptr [[TMP0]], align 1 102db4979cSQiu Chaofan; CHECK-NEXT: ret void 112db4979cSQiu Chaofan; 122db4979cSQiu Chaofanentry: 13c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 142db4979cSQiu Chaofan %vecins = insertelement <16 x i8> %0, i8 %s, i32 3 15c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q, align 16 162db4979cSQiu Chaofan ret void 172db4979cSQiu Chaofan} 182db4979cSQiu Chaofan 19c00ffbe0SNikita Popovdefine void @insert_store_i16_align1(ptr %q, i16 zeroext %s) { 202db4979cSQiu Chaofan; CHECK-LABEL: @insert_store_i16_align1( 212db4979cSQiu Chaofan; CHECK-NEXT: entry: 22c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <8 x i16>, ptr [[Q:%.*]], i32 0, i32 3 23c00ffbe0SNikita Popov; CHECK-NEXT: store i16 [[S:%.*]], ptr [[TMP0]], align 2 242db4979cSQiu Chaofan; CHECK-NEXT: ret void 252db4979cSQiu Chaofan; 262db4979cSQiu Chaofanentry: 27c00ffbe0SNikita Popov %0 = load <8 x i16>, ptr %q 282db4979cSQiu Chaofan %vecins = insertelement <8 x i16> %0, i16 %s, i32 3 29c00ffbe0SNikita Popov store <8 x i16> %vecins, ptr %q, align 1 302db4979cSQiu Chaofan ret void 312db4979cSQiu Chaofan} 322db4979cSQiu Chaofan 336d2df181SQiu Chaofan; To verify case when index is out of bounds 34c00ffbe0SNikita Popovdefine void @insert_store_outofbounds(ptr %q, i16 zeroext %s) { 356d2df181SQiu Chaofan; CHECK-LABEL: @insert_store_outofbounds( 366d2df181SQiu Chaofan; CHECK-NEXT: entry: 37c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr [[Q:%.*]], align 16 386d2df181SQiu Chaofan; CHECK-NEXT: [[VECINS:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[S:%.*]], i32 9 39c00ffbe0SNikita Popov; CHECK-NEXT: store <8 x i16> [[VECINS]], ptr [[Q]], align 16 406d2df181SQiu Chaofan; CHECK-NEXT: ret void 416d2df181SQiu Chaofan; 426d2df181SQiu Chaofanentry: 43c00ffbe0SNikita Popov %0 = load <8 x i16>, ptr %q 446d2df181SQiu Chaofan %vecins = insertelement <8 x i16> %0, i16 %s, i32 9 45c00ffbe0SNikita Popov store <8 x i16> %vecins, ptr %q 466d2df181SQiu Chaofan ret void 476d2df181SQiu Chaofan} 486d2df181SQiu Chaofan 49c00ffbe0SNikita Popovdefine void @insert_store_vscale(ptr %q, i16 zeroext %s) { 506d2df181SQiu Chaofan; CHECK-LABEL: @insert_store_vscale( 516d2df181SQiu Chaofan; CHECK-NEXT: entry: 52ad35d916SBen Shi; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <vscale x 8 x i16>, ptr [[Q:%.*]], i32 0, i32 3 53ad35d916SBen Shi; CHECK-NEXT: store i16 [[S:%.*]], ptr [[TMP0]], align 2 546d2df181SQiu Chaofan; CHECK-NEXT: ret void 556d2df181SQiu Chaofan; 566d2df181SQiu Chaofanentry: 57c00ffbe0SNikita Popov %0 = load <vscale x 8 x i16>, ptr %q 586d2df181SQiu Chaofan %vecins = insertelement <vscale x 8 x i16> %0, i16 %s, i32 3 59c00ffbe0SNikita Popov store <vscale x 8 x i16> %vecins, ptr %q 606d2df181SQiu Chaofan ret void 616d2df181SQiu Chaofan} 626d2df181SQiu Chaofan 63*e2fc68c3SHans Wennborg; To verify the case that index exceeds the minimum number 64ad648c97SBen Shi; of elements of a scalable vector type. 65ad648c97SBen Shidefine void @insert_store_vscale_exceeds(ptr %q, i16 zeroext %s) { 66ad648c97SBen Shi; CHECK-LABEL: @insert_store_vscale_exceeds( 67ad648c97SBen Shi; CHECK-NEXT: entry: 68ad648c97SBen Shi; CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 8 x i16>, ptr [[Q:%.*]], align 16 69ad648c97SBen Shi; CHECK-NEXT: [[VECINS:%.*]] = insertelement <vscale x 8 x i16> [[TMP0]], i16 [[S:%.*]], i32 9 70ad648c97SBen Shi; CHECK-NEXT: store <vscale x 8 x i16> [[VECINS]], ptr [[Q]], align 16 71ad648c97SBen Shi; CHECK-NEXT: ret void 72ad648c97SBen Shi; 73ad648c97SBen Shientry: 74ad648c97SBen Shi %0 = load <vscale x 8 x i16>, ptr %q 75ad648c97SBen Shi %vecins = insertelement <vscale x 8 x i16> %0, i16 %s, i32 9 76ad648c97SBen Shi store <vscale x 8 x i16> %vecins, ptr %q 77ad648c97SBen Shi ret void 78ad648c97SBen Shi} 79ad648c97SBen Shi 80c00ffbe0SNikita Popovdefine void @insert_store_v9i4(ptr %q, i4 zeroext %s) { 812db4979cSQiu Chaofan; CHECK-LABEL: @insert_store_v9i4( 822db4979cSQiu Chaofan; CHECK-NEXT: entry: 83c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = load <9 x i4>, ptr [[Q:%.*]], align 8 842db4979cSQiu Chaofan; CHECK-NEXT: [[VECINS:%.*]] = insertelement <9 x i4> [[TMP0]], i4 [[S:%.*]], i32 3 85c00ffbe0SNikita Popov; CHECK-NEXT: store <9 x i4> [[VECINS]], ptr [[Q]], align 1 862db4979cSQiu Chaofan; CHECK-NEXT: ret void 872db4979cSQiu Chaofan; 882db4979cSQiu Chaofanentry: 89c00ffbe0SNikita Popov %0 = load <9 x i4>, ptr %q 902db4979cSQiu Chaofan %vecins = insertelement <9 x i4> %0, i4 %s, i32 3 91c00ffbe0SNikita Popov store <9 x i4> %vecins, ptr %q, align 1 922db4979cSQiu Chaofan ret void 932db4979cSQiu Chaofan} 942db4979cSQiu Chaofan 95c00ffbe0SNikita Popovdefine void @insert_store_v4i27(ptr %q, i27 zeroext %s) { 962db4979cSQiu Chaofan; CHECK-LABEL: @insert_store_v4i27( 972db4979cSQiu Chaofan; CHECK-NEXT: entry: 98c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i27>, ptr [[Q:%.*]], align 16 992db4979cSQiu Chaofan; CHECK-NEXT: [[VECINS:%.*]] = insertelement <4 x i27> [[TMP0]], i27 [[S:%.*]], i32 3 100c00ffbe0SNikita Popov; CHECK-NEXT: store <4 x i27> [[VECINS]], ptr [[Q]], align 1 1012db4979cSQiu Chaofan; CHECK-NEXT: ret void 1022db4979cSQiu Chaofan; 1032db4979cSQiu Chaofanentry: 104c00ffbe0SNikita Popov %0 = load <4 x i27>, ptr %q 1052db4979cSQiu Chaofan %vecins = insertelement <4 x i27> %0, i27 %s, i32 3 106c00ffbe0SNikita Popov store <4 x i27> %vecins, ptr %q, align 1 1072db4979cSQiu Chaofan ret void 1082db4979cSQiu Chaofan} 1092db4979cSQiu Chaofan 11095606a58SNikita Popovdefine void @insert_store_v32i1(ptr %p) { 11195606a58SNikita Popov; CHECK-LABEL: @insert_store_v32i1( 1123b823979SNikita Popov; CHECK-NEXT: [[VEC:%.*]] = load <32 x i1>, ptr [[P:%.*]], align 4 1133b823979SNikita Popov; CHECK-NEXT: [[INS:%.*]] = insertelement <32 x i1> [[VEC]], i1 true, i64 0 1143b823979SNikita Popov; CHECK-NEXT: store <32 x i1> [[INS]], ptr [[P]], align 4 11595606a58SNikita Popov; CHECK-NEXT: ret void 11695606a58SNikita Popov; 11795606a58SNikita Popov %vec = load <32 x i1>, ptr %p 11895606a58SNikita Popov %ins = insertelement <32 x i1> %vec, i1 true, i64 0 11995606a58SNikita Popov store <32 x i1> %ins, ptr %p 12095606a58SNikita Popov ret void 12195606a58SNikita Popov} 12295606a58SNikita Popov 123c00ffbe0SNikita Popovdefine void @insert_store_blk_differ(ptr %q, i16 zeroext %s) { 1242db4979cSQiu Chaofan; CHECK-LABEL: @insert_store_blk_differ( 1252db4979cSQiu Chaofan; CHECK-NEXT: entry: 126c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr [[Q:%.*]], align 16 1272db4979cSQiu Chaofan; CHECK-NEXT: br label [[CONT:%.*]] 1282db4979cSQiu Chaofan; CHECK: cont: 1292db4979cSQiu Chaofan; CHECK-NEXT: [[VECINS:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[S:%.*]], i32 3 130c00ffbe0SNikita Popov; CHECK-NEXT: store <8 x i16> [[VECINS]], ptr [[Q]], align 16 1312db4979cSQiu Chaofan; CHECK-NEXT: ret void 1322db4979cSQiu Chaofan; 1332db4979cSQiu Chaofanentry: 134c00ffbe0SNikita Popov %0 = load <8 x i16>, ptr %q 1352db4979cSQiu Chaofan br label %cont 1362db4979cSQiu Chaofancont: 1372db4979cSQiu Chaofan %vecins = insertelement <8 x i16> %0, i16 %s, i32 3 138c00ffbe0SNikita Popov store <8 x i16> %vecins, ptr %q 1392db4979cSQiu Chaofan ret void 1402db4979cSQiu Chaofan} 1412db4979cSQiu Chaofan 142c00ffbe0SNikita Popovdefine void @insert_store_nonconst(ptr %q, i8 zeroext %s, i32 %idx) { 1432db4979cSQiu Chaofan; CHECK-LABEL: @insert_store_nonconst( 1442db4979cSQiu Chaofan; CHECK-NEXT: entry: 145c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[Q:%.*]], align 16 1466d2df181SQiu Chaofan; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX:%.*]] 147c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> [[VECINS]], ptr [[Q]], align 16 1482db4979cSQiu Chaofan; CHECK-NEXT: ret void 1492db4979cSQiu Chaofan; 1502db4979cSQiu Chaofanentry: 151c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 1522db4979cSQiu Chaofan %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx 153c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 1542db4979cSQiu Chaofan ret void 1552db4979cSQiu Chaofan} 1562db4979cSQiu Chaofan 157ad648c97SBen Shi; To verify the case that the index is not a constant, and 158ad648c97SBen Shi; the vector type is scalable. 159ad648c97SBen Shidefine void @insert_store_vscale_nonconst(ptr %q, i8 zeroext %s, i32 %idx) { 160ad648c97SBen Shi; CHECK-LABEL: @insert_store_vscale_nonconst( 161ad648c97SBen Shi; CHECK-NEXT: entry: 162ad648c97SBen Shi; CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 16 x i8>, ptr [[Q:%.*]], align 16 163ad648c97SBen Shi; CHECK-NEXT: [[VECINS:%.*]] = insertelement <vscale x 16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX:%.*]] 164ad648c97SBen Shi; CHECK-NEXT: store <vscale x 16 x i8> [[VECINS]], ptr [[Q]], align 16 165ad648c97SBen Shi; CHECK-NEXT: ret void 166ad648c97SBen Shi; 167ad648c97SBen Shientry: 168ad648c97SBen Shi %0 = load <vscale x 16 x i8>, ptr %q 169ad648c97SBen Shi %vecins = insertelement <vscale x 16 x i8> %0, i8 %s, i32 %idx 170ad648c97SBen Shi store <vscale x 16 x i8> %vecins, ptr %q 171ad648c97SBen Shi ret void 172ad648c97SBen Shi} 173ad648c97SBen Shi 1742670c7ddSQiu Chaofan; To verify align here is narrowed to scalar store size 175c00ffbe0SNikita Popovdefine void @insert_store_nonconst_large_alignment(ptr %q, i32 zeroext %s, i32 %idx) { 176a115c524SQiu Chaofan; CHECK-LABEL: @insert_store_nonconst_large_alignment( 177a115c524SQiu Chaofan; CHECK-NEXT: entry: 178a115c524SQiu Chaofan; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 4 179a115c524SQiu Chaofan; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) 180c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <4 x i32>, ptr [[Q:%.*]], i32 0, i32 [[IDX]] 181c00ffbe0SNikita Popov; CHECK-NEXT: store i32 [[S:%.*]], ptr [[TMP0]], align 4 182a115c524SQiu Chaofan; CHECK-NEXT: ret void 183a115c524SQiu Chaofan; 184a115c524SQiu Chaofanentry: 185a115c524SQiu Chaofan %cmp = icmp ult i32 %idx, 4 186a115c524SQiu Chaofan call void @llvm.assume(i1 %cmp) 187c00ffbe0SNikita Popov %i = load <4 x i32>, ptr %q, align 128 188a115c524SQiu Chaofan %vecins = insertelement <4 x i32> %i, i32 %s, i32 %idx 189c00ffbe0SNikita Popov store <4 x i32> %vecins, ptr %q, align 128 190a115c524SQiu Chaofan ret void 191a115c524SQiu Chaofan} 192a115c524SQiu Chaofan 193c00ffbe0SNikita Popovdefine void @insert_store_nonconst_align_maximum_8(ptr %q, i64 %s, i32 %idx) { 194a115c524SQiu Chaofan; CHECK-LABEL: @insert_store_nonconst_align_maximum_8( 195a115c524SQiu Chaofan; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 2 196a115c524SQiu Chaofan; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) 197c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds <8 x i64>, ptr [[Q:%.*]], i32 0, i32 [[IDX]] 198c00ffbe0SNikita Popov; CHECK-NEXT: store i64 [[S:%.*]], ptr [[TMP1]], align 8 199a115c524SQiu Chaofan; CHECK-NEXT: ret void 200a115c524SQiu Chaofan; 201a115c524SQiu Chaofan %cmp = icmp ult i32 %idx, 2 202a115c524SQiu Chaofan call void @llvm.assume(i1 %cmp) 203c00ffbe0SNikita Popov %i = load <8 x i64>, ptr %q, align 8 204a115c524SQiu Chaofan %vecins = insertelement <8 x i64> %i, i64 %s, i32 %idx 205c00ffbe0SNikita Popov store <8 x i64> %vecins, ptr %q, align 8 206a115c524SQiu Chaofan ret void 207a115c524SQiu Chaofan} 208a115c524SQiu Chaofan 209c00ffbe0SNikita Popovdefine void @insert_store_nonconst_align_maximum_4(ptr %q, i64 %s, i32 %idx) { 210a115c524SQiu Chaofan; CHECK-LABEL: @insert_store_nonconst_align_maximum_4( 211a115c524SQiu Chaofan; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 2 212a115c524SQiu Chaofan; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) 213c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds <8 x i64>, ptr [[Q:%.*]], i32 0, i32 [[IDX]] 214c00ffbe0SNikita Popov; CHECK-NEXT: store i64 [[S:%.*]], ptr [[TMP1]], align 4 215a115c524SQiu Chaofan; CHECK-NEXT: ret void 216a115c524SQiu Chaofan; 217a115c524SQiu Chaofan %cmp = icmp ult i32 %idx, 2 218a115c524SQiu Chaofan call void @llvm.assume(i1 %cmp) 219c00ffbe0SNikita Popov %i = load <8 x i64>, ptr %q, align 4 220a115c524SQiu Chaofan %vecins = insertelement <8 x i64> %i, i64 %s, i32 %idx 221c00ffbe0SNikita Popov store <8 x i64> %vecins, ptr %q, align 4 222a115c524SQiu Chaofan ret void 223a115c524SQiu Chaofan} 224a115c524SQiu Chaofan 225c00ffbe0SNikita Popovdefine void @insert_store_nonconst_align_larger(ptr %q, i64 %s, i32 %idx) { 226a115c524SQiu Chaofan; CHECK-LABEL: @insert_store_nonconst_align_larger( 227a115c524SQiu Chaofan; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 2 228a115c524SQiu Chaofan; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) 229c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds <8 x i64>, ptr [[Q:%.*]], i32 0, i32 [[IDX]] 230c00ffbe0SNikita Popov; CHECK-NEXT: store i64 [[S:%.*]], ptr [[TMP1]], align 4 231a115c524SQiu Chaofan; CHECK-NEXT: ret void 232a115c524SQiu Chaofan; 233a115c524SQiu Chaofan %cmp = icmp ult i32 %idx, 2 234a115c524SQiu Chaofan call void @llvm.assume(i1 %cmp) 235c00ffbe0SNikita Popov %i = load <8 x i64>, ptr %q, align 4 236a115c524SQiu Chaofan %vecins = insertelement <8 x i64> %i, i64 %s, i32 %idx 237c00ffbe0SNikita Popov store <8 x i64> %vecins, ptr %q, align 2 238a115c524SQiu Chaofan ret void 239a115c524SQiu Chaofan} 240a115c524SQiu Chaofan 241c00ffbe0SNikita Popovdefine void @insert_store_nonconst_index_known_valid_by_assume(ptr %q, i8 zeroext %s, i32 %idx) { 2427ba0e99aSFlorian Hahn; CHECK-LABEL: @insert_store_nonconst_index_known_valid_by_assume( 2437ba0e99aSFlorian Hahn; CHECK-NEXT: entry: 2447ba0e99aSFlorian Hahn; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 4 2457ba0e99aSFlorian Hahn; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) 246c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, ptr [[Q:%.*]], i32 0, i32 [[IDX]] 247c00ffbe0SNikita Popov; CHECK-NEXT: store i8 [[S:%.*]], ptr [[TMP0]], align 1 2487ba0e99aSFlorian Hahn; CHECK-NEXT: ret void 2497ba0e99aSFlorian Hahn; 2507ba0e99aSFlorian Hahnentry: 2517ba0e99aSFlorian Hahn %cmp = icmp ult i32 %idx, 4 2527ba0e99aSFlorian Hahn call void @llvm.assume(i1 %cmp) 253c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 2547ba0e99aSFlorian Hahn %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx 255c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 2567ba0e99aSFlorian Hahn ret void 2577ba0e99aSFlorian Hahn} 2587ba0e99aSFlorian Hahn 259ad648c97SBen Shi; To verify the index is not a constant but valid by assume, 260ad648c97SBen Shi; for scalable vector types. 261ad648c97SBen Shidefine void @insert_store_vscale_nonconst_index_known_valid_by_assume(ptr %q, i8 zeroext %s, i32 %idx) { 262ad648c97SBen Shi; CHECK-LABEL: @insert_store_vscale_nonconst_index_known_valid_by_assume( 263ad648c97SBen Shi; CHECK-NEXT: entry: 264ad648c97SBen Shi; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 4 265ad648c97SBen Shi; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) 266ad35d916SBen Shi; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <vscale x 16 x i8>, ptr [[Q:%.*]], i32 0, i32 [[IDX]] 267ad35d916SBen Shi; CHECK-NEXT: store i8 [[S:%.*]], ptr [[TMP0]], align 1 268ad648c97SBen Shi; CHECK-NEXT: ret void 269ad648c97SBen Shi; 270ad648c97SBen Shientry: 271ad648c97SBen Shi %cmp = icmp ult i32 %idx, 4 272ad648c97SBen Shi call void @llvm.assume(i1 %cmp) 273ad648c97SBen Shi %0 = load <vscale x 16 x i8>, ptr %q 274ad648c97SBen Shi %vecins = insertelement <vscale x 16 x i8> %0, i8 %s, i32 %idx 275ad648c97SBen Shi store <vscale x 16 x i8> %vecins, ptr %q 276ad648c97SBen Shi ret void 277ad648c97SBen Shi} 278ad648c97SBen Shi 2797ba0e99aSFlorian Hahndeclare void @maythrow() readnone 2807ba0e99aSFlorian Hahn 281c00ffbe0SNikita Popovdefine void @insert_store_nonconst_index_not_known_valid_by_assume_after_load(ptr %q, i8 zeroext %s, i32 %idx) { 2827ba0e99aSFlorian Hahn; CHECK-LABEL: @insert_store_nonconst_index_not_known_valid_by_assume_after_load( 2837ba0e99aSFlorian Hahn; CHECK-NEXT: entry: 2847ba0e99aSFlorian Hahn; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 4 285c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[Q:%.*]], align 16 2867ba0e99aSFlorian Hahn; CHECK-NEXT: call void @maythrow() 2877ba0e99aSFlorian Hahn; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) 2887ba0e99aSFlorian Hahn; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX]] 289c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> [[VECINS]], ptr [[Q]], align 16 2907ba0e99aSFlorian Hahn; CHECK-NEXT: ret void 2917ba0e99aSFlorian Hahn; 2927ba0e99aSFlorian Hahnentry: 2937ba0e99aSFlorian Hahn %cmp = icmp ult i32 %idx, 4 294c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 2957ba0e99aSFlorian Hahn call void @maythrow() 2967ba0e99aSFlorian Hahn call void @llvm.assume(i1 %cmp) 2977ba0e99aSFlorian Hahn %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx 298c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 2997ba0e99aSFlorian Hahn ret void 3007ba0e99aSFlorian Hahn} 3017ba0e99aSFlorian Hahn 302c00ffbe0SNikita Popovdefine void @insert_store_nonconst_index_not_known_valid_by_assume(ptr %q, i8 zeroext %s, i32 %idx) { 3037ba0e99aSFlorian Hahn; CHECK-LABEL: @insert_store_nonconst_index_not_known_valid_by_assume( 3047ba0e99aSFlorian Hahn; CHECK-NEXT: entry: 3057ba0e99aSFlorian Hahn; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 17 3067ba0e99aSFlorian Hahn; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) 307c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[Q:%.*]], align 16 3087ba0e99aSFlorian Hahn; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX]] 309c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> [[VECINS]], ptr [[Q]], align 16 3107ba0e99aSFlorian Hahn; CHECK-NEXT: ret void 3117ba0e99aSFlorian Hahn; 3127ba0e99aSFlorian Hahnentry: 3137ba0e99aSFlorian Hahn %cmp = icmp ult i32 %idx, 17 3147ba0e99aSFlorian Hahn call void @llvm.assume(i1 %cmp) 315c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 3167ba0e99aSFlorian Hahn %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx 317c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 3187ba0e99aSFlorian Hahn ret void 3197ba0e99aSFlorian Hahn} 3207ba0e99aSFlorian Hahn 321ad648c97SBen Shi; To verify the index is not a constant and may not be valid by assume, 322ad648c97SBen Shi; for scalable vector types. 323ad648c97SBen Shidefine void @insert_store_vscale_nonconst_index_not_known_valid_by_assume(ptr %q, i8 zeroext %s, i32 %idx) { 324ad648c97SBen Shi; CHECK-LABEL: @insert_store_vscale_nonconst_index_not_known_valid_by_assume( 325ad648c97SBen Shi; CHECK-NEXT: entry: 326ad648c97SBen Shi; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 17 327ad648c97SBen Shi; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) 328ad648c97SBen Shi; CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 16 x i8>, ptr [[Q:%.*]], align 16 329ad648c97SBen Shi; CHECK-NEXT: [[VECINS:%.*]] = insertelement <vscale x 16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX]] 330ad648c97SBen Shi; CHECK-NEXT: store <vscale x 16 x i8> [[VECINS]], ptr [[Q]], align 16 331ad648c97SBen Shi; CHECK-NEXT: ret void 332ad648c97SBen Shi; 333ad648c97SBen Shientry: 334ad648c97SBen Shi %cmp = icmp ult i32 %idx, 17 335ad648c97SBen Shi call void @llvm.assume(i1 %cmp) 336ad648c97SBen Shi %0 = load <vscale x 16 x i8>, ptr %q 337ad648c97SBen Shi %vecins = insertelement <vscale x 16 x i8> %0, i8 %s, i32 %idx 338ad648c97SBen Shi store <vscale x 16 x i8> %vecins, ptr %q 339ad648c97SBen Shi ret void 340ad648c97SBen Shi} 341ad648c97SBen Shi 3427ba0e99aSFlorian Hahndeclare void @llvm.assume(i1) 3437ba0e99aSFlorian Hahn 344c00ffbe0SNikita Popovdefine void @insert_store_nonconst_index_known_noundef_and_valid_by_and(ptr %q, i8 zeroext %s, i32 noundef %idx) { 345ccf1038aSFlorian Hahn; CHECK-LABEL: @insert_store_nonconst_index_known_noundef_and_valid_by_and( 346ccf1038aSFlorian Hahn; CHECK-NEXT: entry: 347ccf1038aSFlorian Hahn; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = and i32 [[IDX:%.*]], 7 348c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, ptr [[Q:%.*]], i32 0, i32 [[IDX_CLAMPED]] 349c00ffbe0SNikita Popov; CHECK-NEXT: store i8 [[S:%.*]], ptr [[TMP0]], align 1 350ccf1038aSFlorian Hahn; CHECK-NEXT: ret void 351ccf1038aSFlorian Hahn; 352ccf1038aSFlorian Hahnentry: 353c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 354ccf1038aSFlorian Hahn %idx.clamped = and i32 %idx, 7 355ccf1038aSFlorian Hahn %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx.clamped 356c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 357ccf1038aSFlorian Hahn ret void 358ccf1038aSFlorian Hahn} 359ccf1038aSFlorian Hahn 360ad648c97SBen Shi; To verify the index is not a constant but valid by and, 361ad648c97SBen Shi; for scalable vector types. 362ad648c97SBen Shidefine void @insert_store_vscale_nonconst_index_known_noundef_and_valid_by_and(ptr %q, i8 zeroext %s, i32 noundef %idx) { 363ad648c97SBen Shi; CHECK-LABEL: @insert_store_vscale_nonconst_index_known_noundef_and_valid_by_and( 364ad648c97SBen Shi; CHECK-NEXT: entry: 365ad648c97SBen Shi; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = and i32 [[IDX:%.*]], 7 366ad35d916SBen Shi; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <vscale x 16 x i8>, ptr [[Q:%.*]], i32 0, i32 [[IDX_CLAMPED]] 367ad35d916SBen Shi; CHECK-NEXT: store i8 [[S:%.*]], ptr [[TMP0]], align 1 368ad648c97SBen Shi; CHECK-NEXT: ret void 369ad648c97SBen Shi; 370ad648c97SBen Shientry: 371ad648c97SBen Shi %0 = load <vscale x 16 x i8>, ptr %q 372ad648c97SBen Shi %idx.clamped = and i32 %idx, 7 373ad648c97SBen Shi %vecins = insertelement <vscale x 16 x i8> %0, i8 %s, i32 %idx.clamped 374ad648c97SBen Shi store <vscale x 16 x i8> %vecins, ptr %q 375ad648c97SBen Shi ret void 376ad648c97SBen Shi} 377ad648c97SBen Shi 378c00ffbe0SNikita Popovdefine void @insert_store_nonconst_index_base_frozen_and_valid_by_and(ptr %q, i8 zeroext %s, i32 %idx) { 3798d2a8cedSFlorian Hahn; CHECK-LABEL: @insert_store_nonconst_index_base_frozen_and_valid_by_and( 3808d2a8cedSFlorian Hahn; CHECK-NEXT: entry: 3818d2a8cedSFlorian Hahn; CHECK-NEXT: [[IDX_FROZEN:%.*]] = freeze i32 [[IDX:%.*]] 3828d2a8cedSFlorian Hahn; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = and i32 [[IDX_FROZEN]], 7 383c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, ptr [[Q:%.*]], i32 0, i32 [[IDX_CLAMPED]] 384c00ffbe0SNikita Popov; CHECK-NEXT: store i8 [[S:%.*]], ptr [[TMP0]], align 1 3858d2a8cedSFlorian Hahn; CHECK-NEXT: ret void 3868d2a8cedSFlorian Hahn; 3878d2a8cedSFlorian Hahnentry: 388c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 3898d2a8cedSFlorian Hahn %idx.frozen = freeze i32 %idx 3908d2a8cedSFlorian Hahn %idx.clamped = and i32 %idx.frozen, 7 3918d2a8cedSFlorian Hahn %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx.clamped 392c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 3938d2a8cedSFlorian Hahn ret void 3948d2a8cedSFlorian Hahn} 3958d2a8cedSFlorian Hahn 396c00ffbe0SNikita Popovdefine void @insert_store_nonconst_index_frozen_and_valid_by_and(ptr %q, i8 zeroext %s, i32 %idx) { 3978d2a8cedSFlorian Hahn; CHECK-LABEL: @insert_store_nonconst_index_frozen_and_valid_by_and( 3988d2a8cedSFlorian Hahn; CHECK-NEXT: entry: 399c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[Q:%.*]], align 16 4008d2a8cedSFlorian Hahn; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = and i32 [[IDX:%.*]], 7 4018d2a8cedSFlorian Hahn; CHECK-NEXT: [[IDX_CLAMPED_FROZEN:%.*]] = freeze i32 [[IDX_CLAMPED]] 4028d2a8cedSFlorian Hahn; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX_CLAMPED_FROZEN]] 403c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> [[VECINS]], ptr [[Q]], align 16 4048d2a8cedSFlorian Hahn; CHECK-NEXT: ret void 4058d2a8cedSFlorian Hahn; 4068d2a8cedSFlorian Hahnentry: 407c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 4088d2a8cedSFlorian Hahn %idx.clamped = and i32 %idx, 7 4098d2a8cedSFlorian Hahn %idx.clamped.frozen = freeze i32 %idx.clamped 4108d2a8cedSFlorian Hahn %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx.clamped.frozen 411c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 4128d2a8cedSFlorian Hahn ret void 4138d2a8cedSFlorian Hahn} 4148d2a8cedSFlorian Hahn 415c00ffbe0SNikita Popovdefine void @insert_store_nonconst_index_known_valid_by_and_but_may_be_poison(ptr %q, i8 zeroext %s, i32 %idx) { 416ccf1038aSFlorian Hahn; CHECK-LABEL: @insert_store_nonconst_index_known_valid_by_and_but_may_be_poison( 4172f69b78aSFlorian Hahn; CHECK-NEXT: entry: 418ad648c97SBen Shi; CHECK-NEXT: [[IDX_FROZEN:%.*]] = freeze i32 [[IDX:%.*]] 419ad648c97SBen Shi; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = and i32 [[IDX_FROZEN]], 7 420ad648c97SBen Shi; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, ptr [[Q:%.*]], i32 0, i32 [[IDX_CLAMPED]] 421ad648c97SBen Shi; CHECK-NEXT: store i8 [[S:%.*]], ptr [[TMP0]], align 1 4222f69b78aSFlorian Hahn; CHECK-NEXT: ret void 4232f69b78aSFlorian Hahn; 4242f69b78aSFlorian Hahnentry: 425c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 4262f69b78aSFlorian Hahn %idx.clamped = and i32 %idx, 7 4272f69b78aSFlorian Hahn %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx.clamped 428c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 4292f69b78aSFlorian Hahn ret void 4302f69b78aSFlorian Hahn} 4312f69b78aSFlorian Hahn 432c00ffbe0SNikita Popovdefine void @insert_store_nonconst_index_not_known_valid_by_and(ptr %q, i8 zeroext %s, i32 %idx) { 4332f69b78aSFlorian Hahn; CHECK-LABEL: @insert_store_nonconst_index_not_known_valid_by_and( 4342f69b78aSFlorian Hahn; CHECK-NEXT: entry: 435c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[Q:%.*]], align 16 4362f69b78aSFlorian Hahn; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = and i32 [[IDX:%.*]], 16 4372f69b78aSFlorian Hahn; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX_CLAMPED]] 438c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> [[VECINS]], ptr [[Q]], align 16 4392f69b78aSFlorian Hahn; CHECK-NEXT: ret void 4402f69b78aSFlorian Hahn; 4412f69b78aSFlorian Hahnentry: 442c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 4432f69b78aSFlorian Hahn %idx.clamped = and i32 %idx, 16 4442f69b78aSFlorian Hahn %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx.clamped 445c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 4462f69b78aSFlorian Hahn ret void 4472f69b78aSFlorian Hahn} 4482f69b78aSFlorian Hahn 449c00ffbe0SNikita Popovdefine void @insert_store_nonconst_index_known_noundef_not_known_valid_by_and(ptr %q, i8 zeroext %s, i32 noundef %idx) { 4508d2a8cedSFlorian Hahn; CHECK-LABEL: @insert_store_nonconst_index_known_noundef_not_known_valid_by_and( 4518d2a8cedSFlorian Hahn; CHECK-NEXT: entry: 452c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[Q:%.*]], align 16 4538d2a8cedSFlorian Hahn; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = and i32 [[IDX:%.*]], 16 4548d2a8cedSFlorian Hahn; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX_CLAMPED]] 455c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> [[VECINS]], ptr [[Q]], align 16 4568d2a8cedSFlorian Hahn; CHECK-NEXT: ret void 4578d2a8cedSFlorian Hahn; 4588d2a8cedSFlorian Hahnentry: 459c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 4608d2a8cedSFlorian Hahn %idx.clamped = and i32 %idx, 16 4618d2a8cedSFlorian Hahn %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx.clamped 462c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 4638d2a8cedSFlorian Hahn ret void 4648d2a8cedSFlorian Hahn} 465ad648c97SBen Shi 466ad648c97SBen Shi; To verify the index is not a constant and may not be valid by and, 467ad648c97SBen Shi; for scalable vector types. 468ad648c97SBen Shidefine void @insert_store_vscale_nonconst_index_not_known_valid_by_and(ptr %q, i8 zeroext %s, i32 %idx) { 469ad648c97SBen Shi; CHECK-LABEL: @insert_store_vscale_nonconst_index_not_known_valid_by_and( 470ad648c97SBen Shi; CHECK-NEXT: entry: 471ad648c97SBen Shi; CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 16 x i8>, ptr [[Q:%.*]], align 16 472ad648c97SBen Shi; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = and i32 [[IDX:%.*]], 31 473ad648c97SBen Shi; CHECK-NEXT: [[VECINS:%.*]] = insertelement <vscale x 16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX_CLAMPED]] 474ad648c97SBen Shi; CHECK-NEXT: store <vscale x 16 x i8> [[VECINS]], ptr [[Q]], align 16 475ad648c97SBen Shi; CHECK-NEXT: ret void 476ad648c97SBen Shi; 477ad648c97SBen Shientry: 478ad648c97SBen Shi %0 = load <vscale x 16 x i8>, ptr %q 479ad648c97SBen Shi %idx.clamped = and i32 %idx, 31 480ad648c97SBen Shi %vecins = insertelement <vscale x 16 x i8> %0, i8 %s, i32 %idx.clamped 481ad648c97SBen Shi store <vscale x 16 x i8> %vecins, ptr %q 482ad648c97SBen Shi ret void 483ad648c97SBen Shi} 484ad648c97SBen Shi 485c00ffbe0SNikita Popovdefine void @insert_store_nonconst_index_known_noundef_and_valid_by_urem(ptr %q, i8 zeroext %s, i32 noundef %idx) { 486ccf1038aSFlorian Hahn; CHECK-LABEL: @insert_store_nonconst_index_known_noundef_and_valid_by_urem( 487ccf1038aSFlorian Hahn; CHECK-NEXT: entry: 488ccf1038aSFlorian Hahn; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = urem i32 [[IDX:%.*]], 16 489c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, ptr [[Q:%.*]], i32 0, i32 [[IDX_CLAMPED]] 490c00ffbe0SNikita Popov; CHECK-NEXT: store i8 [[S:%.*]], ptr [[TMP0]], align 1 491ccf1038aSFlorian Hahn; CHECK-NEXT: ret void 492ccf1038aSFlorian Hahn; 493ccf1038aSFlorian Hahnentry: 494c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 495ccf1038aSFlorian Hahn %idx.clamped = urem i32 %idx, 16 496ccf1038aSFlorian Hahn %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx.clamped 497c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 498ccf1038aSFlorian Hahn ret void 499ccf1038aSFlorian Hahn} 500ccf1038aSFlorian Hahn 501ad648c97SBen Shi; To verify the index is not a constant but valid by urem, 502ad648c97SBen Shi; for scalable vector types. 503ad648c97SBen Shidefine void @insert_store_vscale_nonconst_index_known_noundef_and_valid_by_urem(ptr %q, i8 zeroext %s, i32 noundef %idx) { 504ad648c97SBen Shi; CHECK-LABEL: @insert_store_vscale_nonconst_index_known_noundef_and_valid_by_urem( 505ad648c97SBen Shi; CHECK-NEXT: entry: 506ad648c97SBen Shi; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = urem i32 [[IDX:%.*]], 16 507ad35d916SBen Shi; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <vscale x 16 x i8>, ptr [[Q:%.*]], i32 0, i32 [[IDX_CLAMPED]] 508ad35d916SBen Shi; CHECK-NEXT: store i8 [[S:%.*]], ptr [[TMP0]], align 1 509ad648c97SBen Shi; CHECK-NEXT: ret void 510ad648c97SBen Shi; 511ad648c97SBen Shientry: 512ad648c97SBen Shi %0 = load <vscale x 16 x i8>, ptr %q 513ad648c97SBen Shi %idx.clamped = urem i32 %idx, 16 514ad648c97SBen Shi %vecins = insertelement <vscale x 16 x i8> %0, i8 %s, i32 %idx.clamped 515ad648c97SBen Shi store <vscale x 16 x i8> %vecins, ptr %q 516ad648c97SBen Shi ret void 517ad648c97SBen Shi} 518ad648c97SBen Shi 519c00ffbe0SNikita Popovdefine void @insert_store_nonconst_index_base_frozen_and_valid_by_urem(ptr %q, i8 zeroext %s, i32 %idx) { 5208d2a8cedSFlorian Hahn; CHECK-LABEL: @insert_store_nonconst_index_base_frozen_and_valid_by_urem( 5218d2a8cedSFlorian Hahn; CHECK-NEXT: entry: 5228d2a8cedSFlorian Hahn; CHECK-NEXT: [[IDX_FROZEN:%.*]] = freeze i32 [[IDX:%.*]] 5238d2a8cedSFlorian Hahn; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = urem i32 [[IDX_FROZEN]], 16 524c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, ptr [[Q:%.*]], i32 0, i32 [[IDX_CLAMPED]] 525c00ffbe0SNikita Popov; CHECK-NEXT: store i8 [[S:%.*]], ptr [[TMP0]], align 1 5268d2a8cedSFlorian Hahn; CHECK-NEXT: ret void 5278d2a8cedSFlorian Hahn; 5288d2a8cedSFlorian Hahnentry: 529c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 5308d2a8cedSFlorian Hahn %idx.frozen = freeze i32 %idx 5318d2a8cedSFlorian Hahn %idx.clamped = urem i32 %idx.frozen, 16 5328d2a8cedSFlorian Hahn %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx.clamped 533c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 5348d2a8cedSFlorian Hahn ret void 5358d2a8cedSFlorian Hahn} 5368d2a8cedSFlorian Hahn 537c00ffbe0SNikita Popovdefine void @insert_store_nonconst_index_frozen_and_valid_by_urem(ptr %q, i8 zeroext %s, i32 %idx) { 5388d2a8cedSFlorian Hahn; CHECK-LABEL: @insert_store_nonconst_index_frozen_and_valid_by_urem( 5398d2a8cedSFlorian Hahn; CHECK-NEXT: entry: 540c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[Q:%.*]], align 16 5418d2a8cedSFlorian Hahn; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = urem i32 [[IDX:%.*]], 16 5428d2a8cedSFlorian Hahn; CHECK-NEXT: [[IDX_CLAMPED_FROZEN:%.*]] = freeze i32 [[IDX_CLAMPED]] 5438d2a8cedSFlorian Hahn; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX_CLAMPED_FROZEN]] 544c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> [[VECINS]], ptr [[Q]], align 16 5458d2a8cedSFlorian Hahn; CHECK-NEXT: ret void 5468d2a8cedSFlorian Hahn; 5478d2a8cedSFlorian Hahnentry: 548c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 5498d2a8cedSFlorian Hahn %idx.clamped = urem i32 %idx, 16 5508d2a8cedSFlorian Hahn %idx.clamped.frozen = freeze i32 %idx.clamped 5518d2a8cedSFlorian Hahn %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx.clamped.frozen 552c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 5538d2a8cedSFlorian Hahn ret void 5548d2a8cedSFlorian Hahn} 5558d2a8cedSFlorian Hahn 556c00ffbe0SNikita Popovdefine void @insert_store_nonconst_index_known_valid_by_urem_but_may_be_poison(ptr %q, i8 zeroext %s, i32 %idx) { 557ccf1038aSFlorian Hahn; CHECK-LABEL: @insert_store_nonconst_index_known_valid_by_urem_but_may_be_poison( 5582f69b78aSFlorian Hahn; CHECK-NEXT: entry: 559ad648c97SBen Shi; CHECK-NEXT: [[IDX_FROZEN:%.*]] = freeze i32 [[IDX:%.*]] 560ad648c97SBen Shi; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = urem i32 [[IDX_FROZEN]], 16 561ad648c97SBen Shi; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, ptr [[Q:%.*]], i32 0, i32 [[IDX_CLAMPED]] 562ad648c97SBen Shi; CHECK-NEXT: store i8 [[S:%.*]], ptr [[TMP0]], align 1 5632f69b78aSFlorian Hahn; CHECK-NEXT: ret void 5642f69b78aSFlorian Hahn; 5652f69b78aSFlorian Hahnentry: 566c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 5672f69b78aSFlorian Hahn %idx.clamped = urem i32 %idx, 16 5682f69b78aSFlorian Hahn %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx.clamped 569c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 5702f69b78aSFlorian Hahn ret void 5712f69b78aSFlorian Hahn} 5722f69b78aSFlorian Hahn 573c00ffbe0SNikita Popovdefine void @insert_store_nonconst_index_not_known_valid_by_urem(ptr %q, i8 zeroext %s, i32 %idx) { 5742f69b78aSFlorian Hahn; CHECK-LABEL: @insert_store_nonconst_index_not_known_valid_by_urem( 5752f69b78aSFlorian Hahn; CHECK-NEXT: entry: 576c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[Q:%.*]], align 16 5772f69b78aSFlorian Hahn; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = urem i32 [[IDX:%.*]], 17 5782f69b78aSFlorian Hahn; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX_CLAMPED]] 579c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> [[VECINS]], ptr [[Q]], align 16 5802f69b78aSFlorian Hahn; CHECK-NEXT: ret void 5812f69b78aSFlorian Hahn; 5822f69b78aSFlorian Hahnentry: 583c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 5842f69b78aSFlorian Hahn %idx.clamped = urem i32 %idx, 17 5852f69b78aSFlorian Hahn %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx.clamped 586c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 5872f69b78aSFlorian Hahn ret void 5882f69b78aSFlorian Hahn} 5892f69b78aSFlorian Hahn 590ad648c97SBen Shi; To verify the index is not a constant and may not be vaild by urem, 591ad648c97SBen Shi; for scalable vector types. 592ad648c97SBen Shidefine void @insert_store_vscale_nonconst_index_not_known_valid_by_urem(ptr %q, i8 zeroext %s, i32 %idx) { 593ad648c97SBen Shi; CHECK-LABEL: @insert_store_vscale_nonconst_index_not_known_valid_by_urem( 594ad648c97SBen Shi; CHECK-NEXT: entry: 595ad648c97SBen Shi; CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 16 x i8>, ptr [[Q:%.*]], align 16 596ad648c97SBen Shi; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = urem i32 [[IDX:%.*]], 17 597ad648c97SBen Shi; CHECK-NEXT: [[VECINS:%.*]] = insertelement <vscale x 16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX_CLAMPED]] 598ad648c97SBen Shi; CHECK-NEXT: store <vscale x 16 x i8> [[VECINS]], ptr [[Q]], align 16 599ad648c97SBen Shi; CHECK-NEXT: ret void 600ad648c97SBen Shi; 601ad648c97SBen Shientry: 602ad648c97SBen Shi %0 = load <vscale x 16 x i8>, ptr %q 603ad648c97SBen Shi %idx.clamped = urem i32 %idx, 17 604ad648c97SBen Shi %vecins = insertelement <vscale x 16 x i8> %0, i8 %s, i32 %idx.clamped 605ad648c97SBen Shi store <vscale x 16 x i8> %vecins, ptr %q 606ad648c97SBen Shi ret void 607ad648c97SBen Shi} 608ad648c97SBen Shi 609c00ffbe0SNikita Popovdefine void @insert_store_nonconst_index_known_noundef_not_known_valid_by_urem(ptr %q, i8 zeroext %s, i32 noundef %idx) { 6108d2a8cedSFlorian Hahn; CHECK-LABEL: @insert_store_nonconst_index_known_noundef_not_known_valid_by_urem( 6118d2a8cedSFlorian Hahn; CHECK-NEXT: entry: 612c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[Q:%.*]], align 16 6138d2a8cedSFlorian Hahn; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = urem i32 [[IDX:%.*]], 17 6148d2a8cedSFlorian Hahn; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 [[IDX_CLAMPED]] 615c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> [[VECINS]], ptr [[Q]], align 16 6168d2a8cedSFlorian Hahn; CHECK-NEXT: ret void 6178d2a8cedSFlorian Hahn; 6188d2a8cedSFlorian Hahnentry: 619c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 6208d2a8cedSFlorian Hahn %idx.clamped = urem i32 %idx, 17 6218d2a8cedSFlorian Hahn %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx.clamped 622c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 6238d2a8cedSFlorian Hahn ret void 6248d2a8cedSFlorian Hahn} 6258d2a8cedSFlorian Hahn 626c00ffbe0SNikita Popovdefine void @insert_store_ptr_strip(ptr %q, i8 zeroext %s) { 6272db4979cSQiu Chaofan; CHECK-LABEL: @insert_store_ptr_strip( 6282db4979cSQiu Chaofan; CHECK-NEXT: entry: 629c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, ptr [[Q:%.*]], i32 0, i32 3 630c00ffbe0SNikita Popov; CHECK-NEXT: store i8 [[S:%.*]], ptr [[TMP0]], align 1 6312db4979cSQiu Chaofan; CHECK-NEXT: ret void 6322db4979cSQiu Chaofan; 6332db4979cSQiu Chaofanentry: 634c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 6356d2df181SQiu Chaofan %vecins = insertelement <16 x i8> %0, i8 %s, i32 3 636c00ffbe0SNikita Popov store <16 x i8> %vecins, ptr %q 6372db4979cSQiu Chaofan ret void 6382db4979cSQiu Chaofan} 6392db4979cSQiu Chaofan 640c00ffbe0SNikita Popovdefine void @volatile_update(ptr %q, ptr %p, i8 zeroext %s) { 6412db4979cSQiu Chaofan; CHECK-LABEL: @volatile_update( 6422db4979cSQiu Chaofan; CHECK-NEXT: entry: 643c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[Q:%.*]], align 16 6442db4979cSQiu Chaofan; CHECK-NEXT: [[VECINS0:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 3 645c00ffbe0SNikita Popov; CHECK-NEXT: store volatile <16 x i8> [[VECINS0]], ptr [[Q]], align 16 646c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr [[P:%.*]], align 16 6472db4979cSQiu Chaofan; CHECK-NEXT: [[VECINS1:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[S]], i32 1 648c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> [[VECINS1]], ptr [[P]], align 16 6492db4979cSQiu Chaofan; CHECK-NEXT: ret void 6502db4979cSQiu Chaofan; 6512db4979cSQiu Chaofanentry: 652c00ffbe0SNikita Popov %0 = load <16 x i8>, ptr %q 6532db4979cSQiu Chaofan %vecins0 = insertelement <16 x i8> %0, i8 %s, i32 3 654c00ffbe0SNikita Popov store volatile <16 x i8> %vecins0, ptr %q 6552db4979cSQiu Chaofan 656c00ffbe0SNikita Popov %1 = load volatile <16 x i8>, ptr %p 6572db4979cSQiu Chaofan %vecins1 = insertelement <16 x i8> %1, i8 %s, i32 1 658c00ffbe0SNikita Popov store <16 x i8> %vecins1, ptr %p 6592db4979cSQiu Chaofan ret void 6602db4979cSQiu Chaofan} 6612db4979cSQiu Chaofan 662c00ffbe0SNikita Popovdefine void @insert_store_addr_differ(ptr %p, ptr %q, i8 %s) { 6632db4979cSQiu Chaofan; CHECK-LABEL: @insert_store_addr_differ( 6642db4979cSQiu Chaofan; CHECK-NEXT: entry: 665c00ffbe0SNikita Popov; CHECK-NEXT: [[LD:%.*]] = load <16 x i8>, ptr [[P:%.*]], align 16 6662db4979cSQiu Chaofan; CHECK-NEXT: [[INS:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i32 3 667c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> [[INS]], ptr [[Q:%.*]], align 16 6682db4979cSQiu Chaofan; CHECK-NEXT: ret void 6692db4979cSQiu Chaofan; 6702db4979cSQiu Chaofanentry: 671c00ffbe0SNikita Popov %ld = load <16 x i8>, ptr %p 6722db4979cSQiu Chaofan %ins = insertelement <16 x i8> %ld, i8 %s, i32 3 673c00ffbe0SNikita Popov store <16 x i8> %ins, ptr %q 6742db4979cSQiu Chaofan ret void 6752db4979cSQiu Chaofan} 6762db4979cSQiu Chaofan 6772db4979cSQiu Chaofan; We can't transform if any instr could modify memory in between. 678c00ffbe0SNikita Popovdefine void @insert_store_mem_modify(ptr %p, ptr %q, ptr noalias %r, i8 %s, i32 %m) { 6792db4979cSQiu Chaofan; CHECK-LABEL: @insert_store_mem_modify( 6802db4979cSQiu Chaofan; CHECK-NEXT: entry: 681c00ffbe0SNikita Popov; CHECK-NEXT: [[LD:%.*]] = load <16 x i8>, ptr [[P:%.*]], align 16 682c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr [[Q:%.*]], align 16 6832db4979cSQiu Chaofan; CHECK-NEXT: [[INS:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i32 3 684c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> [[INS]], ptr [[P]], align 16 685c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr [[R:%.*]], align 16 686c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, ptr [[Q]], i32 0, i32 7 687c00ffbe0SNikita Popov; CHECK-NEXT: store i8 [[S]], ptr [[TMP0]], align 1 688c00ffbe0SNikita Popov; CHECK-NEXT: [[LD3:%.*]] = load <4 x i32>, ptr [[P]], align 16 689c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr [[P]], align 16 6902db4979cSQiu Chaofan; CHECK-NEXT: [[INS3:%.*]] = insertelement <4 x i32> [[LD3]], i32 [[M:%.*]], i32 0 691c00ffbe0SNikita Popov; CHECK-NEXT: store <4 x i32> [[INS3]], ptr [[P]], align 16 6922db4979cSQiu Chaofan; CHECK-NEXT: ret void 6932db4979cSQiu Chaofan; 6942db4979cSQiu Chaofanentry: 6952db4979cSQiu Chaofan ; p may alias q 696c00ffbe0SNikita Popov %ld = load <16 x i8>, ptr %p 697c00ffbe0SNikita Popov store <16 x i8> zeroinitializer, ptr %q 6982db4979cSQiu Chaofan %ins = insertelement <16 x i8> %ld, i8 %s, i32 3 699c00ffbe0SNikita Popov store <16 x i8> %ins, ptr %p 7002db4979cSQiu Chaofan 7012db4979cSQiu Chaofan ; p never aliases r 702c00ffbe0SNikita Popov %ld2 = load <16 x i8>, ptr %q 703c00ffbe0SNikita Popov store <16 x i8> zeroinitializer, ptr %r 7042db4979cSQiu Chaofan %ins2 = insertelement <16 x i8> %ld2, i8 %s, i32 7 705c00ffbe0SNikita Popov store <16 x i8> %ins2, ptr %q 7062db4979cSQiu Chaofan 7072db4979cSQiu Chaofan ; p must alias ptr0 708c00ffbe0SNikita Popov %ld3 = load <4 x i32>, ptr %p 709c00ffbe0SNikita Popov store <16 x i8> zeroinitializer, ptr %p 7102db4979cSQiu Chaofan %ins3 = insertelement <4 x i32> %ld3, i32 %m, i32 0 711c00ffbe0SNikita Popov store <4 x i32> %ins3, ptr %p 7122db4979cSQiu Chaofan 7132db4979cSQiu Chaofan ret void 7142db4979cSQiu Chaofan} 7152db4979cSQiu Chaofan 7162db4979cSQiu Chaofan; Check cases when calls may modify memory 717c00ffbe0SNikita Popovdefine void @insert_store_with_call(ptr %p, ptr %q, i8 %s) { 7182db4979cSQiu Chaofan; CHECK-LABEL: @insert_store_with_call( 7192db4979cSQiu Chaofan; CHECK-NEXT: entry: 720c00ffbe0SNikita Popov; CHECK-NEXT: [[LD:%.*]] = load <16 x i8>, ptr [[P:%.*]], align 16 721c00ffbe0SNikita Popov; CHECK-NEXT: call void @maywrite(ptr [[P]]) 7222db4979cSQiu Chaofan; CHECK-NEXT: [[INS:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i32 3 723c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> [[INS]], ptr [[P]], align 16 7242db4979cSQiu Chaofan; CHECK-NEXT: call void @foo() 725c00ffbe0SNikita Popov; CHECK-NEXT: call void @nowrite(ptr [[P]]) 726c00ffbe0SNikita Popov; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, ptr [[P]], i32 0, i32 7 727c00ffbe0SNikita Popov; CHECK-NEXT: store i8 [[S]], ptr [[TMP0]], align 1 7282db4979cSQiu Chaofan; CHECK-NEXT: ret void 7292db4979cSQiu Chaofan; 7302db4979cSQiu Chaofanentry: 731c00ffbe0SNikita Popov %ld = load <16 x i8>, ptr %p 732c00ffbe0SNikita Popov call void @maywrite(ptr %p) 7332db4979cSQiu Chaofan %ins = insertelement <16 x i8> %ld, i8 %s, i32 3 734c00ffbe0SNikita Popov store <16 x i8> %ins, ptr %p 7352db4979cSQiu Chaofan call void @foo() ; Barrier 736c00ffbe0SNikita Popov %ld2 = load <16 x i8>, ptr %p 737c00ffbe0SNikita Popov call void @nowrite(ptr %p) 7382db4979cSQiu Chaofan %ins2 = insertelement <16 x i8> %ld2, i8 %s, i32 7 739c00ffbe0SNikita Popov store <16 x i8> %ins2, ptr %p 7402db4979cSQiu Chaofan ret void 7412db4979cSQiu Chaofan} 7422db4979cSQiu Chaofan 7432db4979cSQiu Chaofandeclare void @foo() 744c00ffbe0SNikita Popovdeclare void @maywrite(ptr) 745c00ffbe0SNikita Popovdeclare void @nowrite(ptr) readonly 7462db4979cSQiu Chaofan 7472db4979cSQiu Chaofan; To test if number of instructions in-between exceeds the limit (default 30), 7482db4979cSQiu Chaofan; the combine will quit. 749c00ffbe0SNikita Popovdefine i32 @insert_store_maximum_scan_instrs(i32 %arg, ptr %arg1, ptr %arg2, i8 zeroext %arg3) { 7502db4979cSQiu Chaofan; CHECK-LABEL: @insert_store_maximum_scan_instrs( 7512db4979cSQiu Chaofan; CHECK-NEXT: bb: 7522db4979cSQiu Chaofan; CHECK-NEXT: [[I:%.*]] = or i32 [[ARG:%.*]], 1 753c00ffbe0SNikita Popov; CHECK-NEXT: [[I4:%.*]] = load <16 x i8>, ptr [[ARG2:%.*]], align 16 7542db4979cSQiu Chaofan; CHECK-NEXT: [[I5:%.*]] = tail call i32 @bar(i32 [[I]], i1 true) 7552db4979cSQiu Chaofan; CHECK-NEXT: [[I6:%.*]] = shl i32 [[ARG]], [[I5]] 7562db4979cSQiu Chaofan; CHECK-NEXT: [[I7:%.*]] = lshr i32 [[I6]], 26 7572db4979cSQiu Chaofan; CHECK-NEXT: [[I8:%.*]] = trunc i32 [[I7]] to i8 7582db4979cSQiu Chaofan; CHECK-NEXT: [[I9:%.*]] = and i8 [[I8]], 31 7592db4979cSQiu Chaofan; CHECK-NEXT: [[I10:%.*]] = lshr i32 [[I6]], 11 7602db4979cSQiu Chaofan; CHECK-NEXT: [[I11:%.*]] = and i32 [[I10]], 32767 7612db4979cSQiu Chaofan; CHECK-NEXT: [[I12:%.*]] = zext i8 [[I9]] to i64 762c00ffbe0SNikita Popov; CHECK-NEXT: [[I13:%.*]] = getelementptr inbounds i16, ptr [[ARG1:%.*]], i64 [[I12]] 763c00ffbe0SNikita Popov; CHECK-NEXT: [[I14:%.*]] = load i16, ptr [[I13]], align 2 7642db4979cSQiu Chaofan; CHECK-NEXT: [[I15:%.*]] = zext i16 [[I14]] to i32 7652db4979cSQiu Chaofan; CHECK-NEXT: [[I16:%.*]] = add nuw nsw i8 [[I9]], 1 7662db4979cSQiu Chaofan; CHECK-NEXT: [[I17:%.*]] = zext i8 [[I16]] to i64 767c00ffbe0SNikita Popov; CHECK-NEXT: [[I18:%.*]] = getelementptr inbounds i16, ptr [[ARG1]], i64 [[I17]] 768c00ffbe0SNikita Popov; CHECK-NEXT: [[I19:%.*]] = load i16, ptr [[I18]], align 2 7692db4979cSQiu Chaofan; CHECK-NEXT: [[I20:%.*]] = zext i16 [[I19]] to i32 7702db4979cSQiu Chaofan; CHECK-NEXT: [[I21:%.*]] = sub nsw i32 [[I20]], [[I15]] 7712db4979cSQiu Chaofan; CHECK-NEXT: [[I22:%.*]] = mul nsw i32 [[I11]], [[I21]] 7722db4979cSQiu Chaofan; CHECK-NEXT: [[I23:%.*]] = ashr i32 [[I22]], 15 7732db4979cSQiu Chaofan; CHECK-NEXT: [[I24:%.*]] = shl nuw nsw i32 [[I5]], 15 7742db4979cSQiu Chaofan; CHECK-NEXT: [[I25:%.*]] = xor i32 [[I24]], 1015808 7752db4979cSQiu Chaofan; CHECK-NEXT: [[I26:%.*]] = add nuw nsw i32 [[I25]], [[I15]] 7762db4979cSQiu Chaofan; CHECK-NEXT: [[I27:%.*]] = add nsw i32 [[I26]], [[I23]] 7772db4979cSQiu Chaofan; CHECK-NEXT: [[I28:%.*]] = sitofp i32 [[ARG]] to double 7782db4979cSQiu Chaofan; CHECK-NEXT: [[I29:%.*]] = tail call double @llvm.log2.f64(double [[I28]]) 7792db4979cSQiu Chaofan; CHECK-NEXT: [[I30:%.*]] = fptosi double [[I29]] to i32 7802db4979cSQiu Chaofan; CHECK-NEXT: [[I31:%.*]] = shl nsw i32 [[I30]], 15 7812db4979cSQiu Chaofan; CHECK-NEXT: [[I32:%.*]] = or i32 [[I31]], 4 7822db4979cSQiu Chaofan; CHECK-NEXT: [[I33:%.*]] = icmp eq i32 [[I27]], [[I32]] 7832db4979cSQiu Chaofan; CHECK-NEXT: [[I34:%.*]] = select i1 [[I33]], i32 [[ARG]], i32 [[I31]] 7842db4979cSQiu Chaofan; CHECK-NEXT: [[I35:%.*]] = lshr i32 [[I34]], 1 7852db4979cSQiu Chaofan; CHECK-NEXT: [[I36:%.*]] = insertelement <16 x i8> [[I4]], i8 [[ARG3:%.*]], i32 3 786c00ffbe0SNikita Popov; CHECK-NEXT: store <16 x i8> [[I36]], ptr [[ARG2]], align 16 7872db4979cSQiu Chaofan; CHECK-NEXT: ret i32 [[I35]] 7882db4979cSQiu Chaofan; 7892db4979cSQiu Chaofanbb: 7902db4979cSQiu Chaofan %i = or i32 %arg, 1 791c00ffbe0SNikita Popov %i4 = load <16 x i8>, ptr %arg2, align 16 7922db4979cSQiu Chaofan %i5 = tail call i32 @bar(i32 %i, i1 true) 7932db4979cSQiu Chaofan %i6 = shl i32 %arg, %i5 7942db4979cSQiu Chaofan %i7 = lshr i32 %i6, 26 7952db4979cSQiu Chaofan %i8 = trunc i32 %i7 to i8 7962db4979cSQiu Chaofan %i9 = and i8 %i8, 31 7972db4979cSQiu Chaofan %i10 = lshr i32 %i6, 11 7982db4979cSQiu Chaofan %i11 = and i32 %i10, 32767 7992db4979cSQiu Chaofan %i12 = zext i8 %i9 to i64 800c00ffbe0SNikita Popov %i13 = getelementptr inbounds i16, ptr %arg1, i64 %i12 801c00ffbe0SNikita Popov %i14 = load i16, ptr %i13, align 2 8022db4979cSQiu Chaofan %i15 = zext i16 %i14 to i32 8032db4979cSQiu Chaofan %i16 = add nuw nsw i8 %i9, 1 8042db4979cSQiu Chaofan %i17 = zext i8 %i16 to i64 805c00ffbe0SNikita Popov %i18 = getelementptr inbounds i16, ptr %arg1, i64 %i17 806c00ffbe0SNikita Popov %i19 = load i16, ptr %i18, align 2 8072db4979cSQiu Chaofan %i20 = zext i16 %i19 to i32 8082db4979cSQiu Chaofan %i21 = sub nsw i32 %i20, %i15 8092db4979cSQiu Chaofan %i22 = mul nsw i32 %i11, %i21 8102db4979cSQiu Chaofan %i23 = ashr i32 %i22, 15 8112db4979cSQiu Chaofan %i24 = shl nuw nsw i32 %i5, 15 8122db4979cSQiu Chaofan %i25 = xor i32 %i24, 1015808 8132db4979cSQiu Chaofan %i26 = add nuw nsw i32 %i25, %i15 8142db4979cSQiu Chaofan %i27 = add nsw i32 %i26, %i23 8152db4979cSQiu Chaofan %i28 = sitofp i32 %arg to double 8162db4979cSQiu Chaofan %i29 = tail call double @llvm.log2.f64(double %i28) 8172db4979cSQiu Chaofan %i30 = fptosi double %i29 to i32 8182db4979cSQiu Chaofan %i31 = shl nsw i32 %i30, 15 8192db4979cSQiu Chaofan %i32 = or i32 %i31, 4 8202db4979cSQiu Chaofan %i33 = icmp eq i32 %i27, %i32 8212db4979cSQiu Chaofan %i34 = select i1 %i33, i32 %arg, i32 %i31 8222db4979cSQiu Chaofan %i35 = lshr i32 %i34, 1 8232db4979cSQiu Chaofan %i36 = insertelement <16 x i8> %i4, i8 %arg3, i32 3 824c00ffbe0SNikita Popov store <16 x i8> %i36, ptr %arg2, align 16 8252db4979cSQiu Chaofan ret i32 %i35 8262db4979cSQiu Chaofan} 8272db4979cSQiu Chaofan 8282db4979cSQiu Chaofandeclare i32 @bar(i32, i1) readonly 8292db4979cSQiu Chaofandeclare double @llvm.log2.f64(double) 830