1*15ee17c3SElvina Yakubova; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 2*15ee17c3SElvina Yakubova; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s %} 3*15ee17c3SElvina Yakubova; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s %} 4*15ee17c3SElvina Yakubova 5*15ee17c3SElvina Yakubova%struct.UFP = type { i32, i32, i32, [4 x i32] } 6*15ee17c3SElvina Yakubova 7*15ee17c3SElvina Yakubovadefine void @test(ptr %u) { 8*15ee17c3SElvina Yakubova; CHECK-LABEL: define void @test( 9*15ee17c3SElvina Yakubova; CHECK-SAME: ptr [[U:%.*]]) { 10*15ee17c3SElvina Yakubova; CHECK-NEXT: entry: 11*15ee17c3SElvina Yakubova; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr null, align 4 12*15ee17c3SElvina Yakubova; CHECK-NEXT: [[IDX:%.*]] = getelementptr [[STRUCT_UFP:%.*]], ptr [[U]], i64 0, i32 3, i64 3 13*15ee17c3SElvina Yakubova; CHECK-NEXT: [[IDX1:%.*]] = getelementptr [[STRUCT_UFP]], ptr [[U]], i64 0, i32 3, i64 2 14*15ee17c3SElvina Yakubova; CHECK-NEXT: [[IDX2:%.*]] = load i32, ptr [[IDX]], align 4 15*15ee17c3SElvina Yakubova; CHECK-NEXT: [[IDX3:%.*]] = load i32, ptr [[IDX1]], align 4 16*15ee17c3SElvina Yakubova; CHECK-NEXT: br label [[WHILE:%.*]] 17*15ee17c3SElvina Yakubova; CHECK: bb: 18*15ee17c3SElvina Yakubova; CHECK-NEXT: store i32 [[OR_I_I:%.*]], ptr [[IDX]], align 4 19*15ee17c3SElvina Yakubova; CHECK-NEXT: store i32 [[OR19_I_I:%.*]], ptr [[IDX1]], align 4 20*15ee17c3SElvina Yakubova; CHECK-NEXT: ret void 21*15ee17c3SElvina Yakubova; CHECK: while: 22*15ee17c3SElvina Yakubova; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[OR26_I_I:%.*]], [[WHILE]] ] 23*15ee17c3SElvina Yakubova; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ [[IDX3]], [[ENTRY]] ], [ [[OR19_I_I]], [[WHILE]] ] 24*15ee17c3SElvina Yakubova; CHECK-NEXT: [[TMP3:%.*]] = phi i32 [ [[IDX2]], [[ENTRY]] ], [ 0, [[WHILE]] ] 25*15ee17c3SElvina Yakubova; CHECK-NEXT: [[OR_I_I]] = tail call i32 @llvm.fshl.i32(i32 [[TMP2]], i32 0, i32 0) 26*15ee17c3SElvina Yakubova; CHECK-NEXT: [[OR19_I_I]] = tail call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP2]], i32 0) 27*15ee17c3SElvina Yakubova; CHECK-NEXT: [[OR26_I_I]] = tail call i32 @llvm.fshl.i32(i32 0, i32 [[TMP1]], i32 0) 28*15ee17c3SElvina Yakubova; CHECK-NEXT: br i1 false, label [[BB:%.*]], label [[WHILE]] 29*15ee17c3SElvina Yakubova; 30*15ee17c3SElvina Yakubovaentry: 31*15ee17c3SElvina Yakubova %0 = load i32, ptr null, align 4 32*15ee17c3SElvina Yakubova %idx = getelementptr %struct.UFP, ptr %u, i64 0, i32 3, i64 3 33*15ee17c3SElvina Yakubova %idx1 = getelementptr %struct.UFP, ptr %u, i64 0, i32 3, i64 2 34*15ee17c3SElvina Yakubova %idx2 = load i32, ptr %idx, align 4 35*15ee17c3SElvina Yakubova %idx3 = load i32, ptr %idx1, align 4 36*15ee17c3SElvina Yakubova br label %while 37*15ee17c3SElvina Yakubova 38*15ee17c3SElvina Yakubovabb: 39*15ee17c3SElvina Yakubova store i32 %or.i.i, ptr %idx, align 4 40*15ee17c3SElvina Yakubova store i32 %or19.i.i, ptr %idx1, align 4 41*15ee17c3SElvina Yakubova ret void 42*15ee17c3SElvina Yakubova 43*15ee17c3SElvina Yakubovawhile: 44*15ee17c3SElvina Yakubova %1 = phi i32 [ %0, %entry ], [ %or26.i.i, %while ] 45*15ee17c3SElvina Yakubova %2 = phi i32 [ %idx3, %entry ], [ %or19.i.i, %while ] 46*15ee17c3SElvina Yakubova %3 = phi i32 [ %idx2, %entry ], [ 0, %while ] 47*15ee17c3SElvina Yakubova %or.i.i = tail call i32 @llvm.fshl.i32(i32 %2, i32 0, i32 0) 48*15ee17c3SElvina Yakubova %or19.i.i = tail call i32 @llvm.fshl.i32(i32 %1, i32 %2, i32 0) 49*15ee17c3SElvina Yakubova %or26.i.i = tail call i32 @llvm.fshl.i32(i32 0, i32 %1, i32 0) 50*15ee17c3SElvina Yakubova br i1 false, label %bb, label %while 51*15ee17c3SElvina Yakubova} 52*15ee17c3SElvina Yakubova 53*15ee17c3SElvina Yakubovadeclare i32 @llvm.fshl.i32(i32, i32, i32) 54