1*15ee17c3SElvina Yakubova; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2*15ee17c3SElvina Yakubova; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-linux-gnu < %s | FileCheck %s %} 3*15ee17c3SElvina Yakubova; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-linux-gnu < %s | FileCheck %s %} 4*15ee17c3SElvina Yakubova 5*15ee17c3SElvina Yakubovadefine void @test(ptr noalias %arg, ptr noalias %arg1, ptr %arg2) { 6*15ee17c3SElvina Yakubova; CHECK-LABEL: define void @test( 7*15ee17c3SElvina Yakubova; CHECK-SAME: ptr noalias [[ARG:%.*]], ptr noalias [[ARG1:%.*]], ptr [[ARG2:%.*]]) { 8*15ee17c3SElvina Yakubova; CHECK-NEXT: bb: 9*15ee17c3SElvina Yakubova; CHECK-NEXT: [[TMP_I_I:%.*]] = getelementptr i8, ptr [[ARG1]], i64 24 10*15ee17c3SElvina Yakubova; CHECK-NEXT: [[TMP_I_I4:%.*]] = getelementptr i8, ptr [[ARG]], i64 24 11*15ee17c3SElvina Yakubova; CHECK-NEXT: [[TMP_I_I13:%.*]] = getelementptr i8, ptr [[ARG1]], i64 28 12*15ee17c3SElvina Yakubova; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[TMP_I_I13]], align 4 13*15ee17c3SElvina Yakubova; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[TMP_I_I]], align 8 14*15ee17c3SElvina Yakubova; CHECK-NEXT: store float [[TMP1]], ptr [[ARG2]], align 4 15*15ee17c3SElvina Yakubova; CHECK-NEXT: [[TMP2:%.*]] = fcmp olt <4 x float> [[TMP0]], zeroinitializer 16*15ee17c3SElvina Yakubova; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[TMP0]], <4 x float> poison, <4 x i32> <i32 2, i32 3, i32 2, i32 3> 17*15ee17c3SElvina Yakubova; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x float> [[TMP0]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1> 18*15ee17c3SElvina Yakubova; CHECK-NEXT: [[TMP5:%.*]] = select <4 x i1> [[TMP2]], <4 x float> [[TMP3]], <4 x float> [[TMP4]] 19*15ee17c3SElvina Yakubova; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> poison, <4 x i32> <i32 2, i32 0, i32 3, i32 1> 20*15ee17c3SElvina Yakubova; CHECK-NEXT: store <4 x float> [[TMP6]], ptr [[TMP_I_I4]], align 8 21*15ee17c3SElvina Yakubova; CHECK-NEXT: ret void 22*15ee17c3SElvina Yakubova; 23*15ee17c3SElvina Yakubovabb: 24*15ee17c3SElvina Yakubova %tmp.i.i = getelementptr i8, ptr %arg1, i64 24 25*15ee17c3SElvina Yakubova %tmp1.i.i = load float, ptr %tmp.i.i, align 8 26*15ee17c3SElvina Yakubova %tmp.i.i2 = getelementptr i8, ptr %arg1, i64 32 27*15ee17c3SElvina Yakubova %tmp1.i.i3 = load float, ptr %tmp.i.i2, align 8 28*15ee17c3SElvina Yakubova %tmp1.i.i.i = fcmp olt float %tmp1.i.i3, 0.000000e+00 29*15ee17c3SElvina Yakubova %tmp9 = select i1 %tmp1.i.i.i, float %tmp1.i.i3, float %tmp1.i.i 30*15ee17c3SElvina Yakubova %tmp.i.i4 = getelementptr i8, ptr %arg, i64 24 31*15ee17c3SElvina Yakubova store float %tmp9, ptr %tmp.i.i4, align 8 32*15ee17c3SElvina Yakubova %tmp1.i.i.i10 = fcmp olt float %tmp1.i.i, 0.000000e+00 33*15ee17c3SElvina Yakubova %tmp13 = select i1 %tmp1.i.i.i10, float %tmp1.i.i3, float %tmp1.i.i 34*15ee17c3SElvina Yakubova %tmp.i.i12 = getelementptr i8, ptr %arg, i64 28 35*15ee17c3SElvina Yakubova store float %tmp13, ptr %tmp.i.i12, align 4 36*15ee17c3SElvina Yakubova %tmp.i.i13 = getelementptr i8, ptr %arg1, i64 28 37*15ee17c3SElvina Yakubova %tmp1.i.i14 = load float, ptr %tmp.i.i13, align 4 38*15ee17c3SElvina Yakubova %tmp.i.i15 = getelementptr i8, ptr %arg1, i64 36 39*15ee17c3SElvina Yakubova %tmp1.i.i16 = load float, ptr %tmp.i.i15, align 4 40*15ee17c3SElvina Yakubova %tmp1.i.i.i18 = fcmp olt float %tmp1.i.i16, 0.000000e+00 41*15ee17c3SElvina Yakubova %tmp17 = select i1 %tmp1.i.i.i18, float %tmp1.i.i16, float %tmp1.i.i14 42*15ee17c3SElvina Yakubova %tmp.i.i20 = getelementptr i8, ptr %arg, i64 32 43*15ee17c3SElvina Yakubova store float %tmp17, ptr %tmp.i.i20, align 8 44*15ee17c3SElvina Yakubova store float %tmp1.i.i14, ptr %arg2, align 4 45*15ee17c3SElvina Yakubova %tmp1.i.i.i24 = fcmp olt float %tmp1.i.i14, 0.000000e+00 46*15ee17c3SElvina Yakubova %tmp20 = select i1 %tmp1.i.i.i24, float %tmp1.i.i16, float %tmp1.i.i14 47*15ee17c3SElvina Yakubova %tmp.i.i26 = getelementptr i8, ptr %arg, i64 36 48*15ee17c3SElvina Yakubova store float %tmp20, ptr %tmp.i.i26, align 4 49*15ee17c3SElvina Yakubova ret void 50*15ee17c3SElvina Yakubova} 51