1*706e7107SElvina Yakubova; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2*706e7107SElvina Yakubova; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s %} 3*706e7107SElvina Yakubova; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s %} 4*706e7107SElvina Yakubova 5*706e7107SElvina Yakubova@e = global i8 0 6*706e7107SElvina Yakubova@c = global i16 0 7*706e7107SElvina Yakubova@d = global i32 0 8*706e7107SElvina Yakubova 9*706e7107SElvina Yakubovadefine i8 @test() { 10*706e7107SElvina Yakubova; CHECK-LABEL: define i8 @test() { 11*706e7107SElvina Yakubova; CHECK-NEXT: entry: 12*706e7107SElvina Yakubova; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr @e, align 1 13*706e7107SElvina Yakubova; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP0]] to i32 14*706e7107SElvina Yakubova; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr @c, align 2 15*706e7107SElvina Yakubova; CHECK-NEXT: [[CONV1:%.*]] = zext i16 [[TMP1]] to i32 16*706e7107SElvina Yakubova; CHECK-NEXT: [[TMP13:%.*]] = or i32 [[CONV]], 32769 17*706e7107SElvina Yakubova; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> poison, i32 [[CONV]], i32 0 18*706e7107SElvina Yakubova; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> poison, <8 x i32> zeroinitializer 19*706e7107SElvina Yakubova; CHECK-NEXT: [[TMP4:%.*]] = or <8 x i32> [[TMP3]], <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 32769> 20*706e7107SElvina Yakubova; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> poison, i32 [[CONV1]], i32 0 21*706e7107SElvina Yakubova; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i32> [[TMP6]], <8 x i32> poison, <8 x i32> zeroinitializer 22*706e7107SElvina Yakubova; CHECK-NEXT: [[TMP8:%.*]] = add nsw <8 x i32> [[TMP4]], [[TMP7]] 23*706e7107SElvina Yakubova; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> [[TMP8]]) 24*706e7107SElvina Yakubova; CHECK-NEXT: [[CONV4_30:%.*]] = trunc i32 [[TMP11]] to i8 25*706e7107SElvina Yakubova; CHECK-NEXT: [[XOR_31:%.*]] = and i32 [[TMP13]], -2 26*706e7107SElvina Yakubova; CHECK-NEXT: store i32 [[XOR_31]], ptr @d, align 4 27*706e7107SElvina Yakubova; CHECK-NEXT: ret i8 [[CONV4_30]] 28*706e7107SElvina Yakubova; 29*706e7107SElvina Yakubovaentry: 30*706e7107SElvina Yakubova %0 = load i8, ptr @e, align 1 31*706e7107SElvina Yakubova %conv = sext i8 %0 to i32 32*706e7107SElvina Yakubova %1 = load i16, ptr @c, align 2 33*706e7107SElvina Yakubova %conv1 = zext i16 %1 to i32 34*706e7107SElvina Yakubova %or.16 = or i32 %conv, 1 35*706e7107SElvina Yakubova %add.16 = add nsw i32 %or.16, %conv1 36*706e7107SElvina Yakubova %or.18 = or i32 %conv, 1 37*706e7107SElvina Yakubova %add.18 = add nsw i32 %or.18, %conv1 38*706e7107SElvina Yakubova %conv4.181 = or i32 %add.16, %add.18 39*706e7107SElvina Yakubova %or.20 = or i32 %conv, 1 40*706e7107SElvina Yakubova %add.20 = add nsw i32 %or.20, %conv1 41*706e7107SElvina Yakubova %conv4.202 = or i32 %conv4.181, %add.20 42*706e7107SElvina Yakubova %or.22 = or i32 %conv, 1 43*706e7107SElvina Yakubova %add.22 = add nsw i32 %or.22, %conv1 44*706e7107SElvina Yakubova %conv4.223 = or i32 %conv4.202, %add.22 45*706e7107SElvina Yakubova %or.24 = or i32 %conv, 1 46*706e7107SElvina Yakubova %add.24 = add nsw i32 %or.24, %conv1 47*706e7107SElvina Yakubova %conv4.244 = or i32 %conv4.223, %add.24 48*706e7107SElvina Yakubova %or.26 = or i32 %conv, 1 49*706e7107SElvina Yakubova %add.26 = add nsw i32 %or.26, %conv1 50*706e7107SElvina Yakubova %conv4.265 = or i32 %conv4.244, %add.26 51*706e7107SElvina Yakubova %or.28 = or i32 %conv, 1 52*706e7107SElvina Yakubova %add.28 = add nsw i32 %or.28, %conv1 53*706e7107SElvina Yakubova %conv4.286 = or i32 %conv4.265, %add.28 54*706e7107SElvina Yakubova %or.30 = or i32 %conv, 32769 55*706e7107SElvina Yakubova %add.30 = add nsw i32 %or.30, %conv1 56*706e7107SElvina Yakubova %conv4.307 = or i32 %conv4.286, %add.30 57*706e7107SElvina Yakubova %conv4.30 = trunc i32 %conv4.307 to i8 58*706e7107SElvina Yakubova %xor.31 = and i32 %or.30, -2 59*706e7107SElvina Yakubova store i32 %xor.31, ptr @d, align 4 60*706e7107SElvina Yakubova ret i8 %conv4.30 61*706e7107SElvina Yakubova} 62