14652ec0eSPatrick O'Neill; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 24652ec0eSPatrick O'Neill; RUN: opt < %s -passes=slp-vectorizer -S | FileCheck %s 34652ec0eSPatrick O'Neill 44652ec0eSPatrick O'Neilltarget triple = "riscv64-unknown-linux-gnu" 54652ec0eSPatrick O'Neill 64652ec0eSPatrick O'Neilldefine void @partial_vec_invalid_cost() #0 { 74652ec0eSPatrick O'Neill; CHECK-LABEL: define void @partial_vec_invalid_cost( 84652ec0eSPatrick O'Neill; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { 94652ec0eSPatrick O'Neill; CHECK-NEXT: entry: 10*947d8ebbSAlexey Bataev; CHECK-NEXT: [[LSHR_1:%.*]] = lshr i96 0, 0 11*947d8ebbSAlexey Bataev; CHECK-NEXT: [[LSHR_2:%.*]] = lshr i96 0, 0 12*947d8ebbSAlexey Bataev; CHECK-NEXT: [[TRUNC_I96_1:%.*]] = trunc i96 [[LSHR_1]] to i32 13*947d8ebbSAlexey Bataev; CHECK-NEXT: [[TRUNC_I96_2:%.*]] = trunc i96 [[LSHR_2]] to i32 14*947d8ebbSAlexey Bataev; CHECK-NEXT: [[TRUNC_I96_3:%.*]] = trunc i96 0 to i32 15*947d8ebbSAlexey Bataev; CHECK-NEXT: [[TRUNC_I96_4:%.*]] = trunc i96 0 to i32 1654ca1e2cSAlexey Bataev; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> zeroinitializer) 17*947d8ebbSAlexey Bataev; CHECK-NEXT: [[OP_RDX:%.*]] = or i32 [[TMP1]], [[TRUNC_I96_1]] 18*947d8ebbSAlexey Bataev; CHECK-NEXT: [[OP_RDX1:%.*]] = or i32 [[TRUNC_I96_2]], [[TRUNC_I96_3]] 19*947d8ebbSAlexey Bataev; CHECK-NEXT: [[OP_RDX2:%.*]] = or i32 [[OP_RDX]], [[OP_RDX1]] 20*947d8ebbSAlexey Bataev; CHECK-NEXT: [[OP_RDX3:%.*]] = or i32 [[OP_RDX2]], [[TRUNC_I96_4]] 214652ec0eSPatrick O'Neill; CHECK-NEXT: [[STORE_THIS:%.*]] = zext i32 [[OP_RDX3]] to i96 224652ec0eSPatrick O'Neill; CHECK-NEXT: store i96 [[STORE_THIS]], ptr null, align 16 234652ec0eSPatrick O'Neill; CHECK-NEXT: ret void 244652ec0eSPatrick O'Neill; 254652ec0eSPatrick O'Neillentry: 264652ec0eSPatrick O'Neill 274652ec0eSPatrick O'Neill %lshr.1 = lshr i96 0, 0 ; These ops 284652ec0eSPatrick O'Neill %lshr.2 = lshr i96 0, 0 ; return an 294652ec0eSPatrick O'Neill %add.0 = add i96 0, 0 ; invalid 304652ec0eSPatrick O'Neill %add.1 = add i96 0, 0 ; vector cost. 314652ec0eSPatrick O'Neill 324652ec0eSPatrick O'Neill %trunc.i96.1 = trunc i96 %lshr.1 to i32 ; These ops 334652ec0eSPatrick O'Neill %trunc.i96.2 = trunc i96 %lshr.2 to i32 ; return an 344652ec0eSPatrick O'Neill %trunc.i96.3 = trunc i96 %add.0 to i32 ; invalid 354652ec0eSPatrick O'Neill %trunc.i96.4 = trunc i96 %add.1 to i32 ; vector cost. 364652ec0eSPatrick O'Neill 374652ec0eSPatrick O'Neill %or.0 = or i32 %trunc.i96.1, %trunc.i96.2 384652ec0eSPatrick O'Neill %or.1 = or i32 %or.0, %trunc.i96.3 394652ec0eSPatrick O'Neill %or.2 = or i32 %or.1, %trunc.i96.4 404652ec0eSPatrick O'Neill 414652ec0eSPatrick O'Neill %zext.0 = zext i1 0 to i32 ; These 424652ec0eSPatrick O'Neill %zext.1 = zext i1 0 to i32 ; ops 434652ec0eSPatrick O'Neill %zext.2 = zext i1 0 to i32 ; are 444652ec0eSPatrick O'Neill %zext.3 = zext i1 0 to i32 ; vectorized 454652ec0eSPatrick O'Neill 464652ec0eSPatrick O'Neill %or.3 = or i32 %or.2, %zext.0 ; users 474652ec0eSPatrick O'Neill %or.4 = or i32 %or.3, %zext.1 ; of 484652ec0eSPatrick O'Neill %or.5 = or i32 %or.4, %zext.2 ; vectorized 494652ec0eSPatrick O'Neill %or.6 = or i32 %or.5, %zext.3 ; ops 504652ec0eSPatrick O'Neill 514652ec0eSPatrick O'Neill %store.this = zext i32 %or.6 to i96 524652ec0eSPatrick O'Neill 534652ec0eSPatrick O'Neill store i96 %store.this, ptr null, align 16 544652ec0eSPatrick O'Neill ret void 554652ec0eSPatrick O'Neill} 564652ec0eSPatrick O'Neill 574652ec0eSPatrick O'Neillattributes #0 = { "target-features"="+v" } 58