1e83c6ddfSAlexey Bataev; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2e83c6ddfSAlexey Bataev; RUN: opt -S --passes=slp-vectorizer -mtriple=riscv64-unknown-linux -mattr=+v < %s | FileCheck %s 3e83c6ddfSAlexey Bataev 4e83c6ddfSAlexey Bataevdefine void @test(ptr noalias %p, ptr %p1) { 5e83c6ddfSAlexey Bataev; CHECK-LABEL: define void @test( 6e83c6ddfSAlexey Bataev; CHECK-SAME: ptr noalias [[P:%.*]], ptr [[P1:%.*]]) #[[ATTR0:[0-9]+]] { 796b31666SVitaly Buka; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 16 8*f3d2609aSAlexey Bataev; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[P]], align 2 9fc382db2SAlexey Bataev; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i16>, ptr [[GEP2]], align 2 10*f3d2609aSAlexey Bataev; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.vector.insert.v4i16.v2i16(<4 x i16> poison, <2 x i16> [[TMP1]], i64 0) 11*f3d2609aSAlexey Bataev; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i16> @llvm.vector.insert.v4i16.v2i16(<4 x i16> [[TMP3]], <2 x i16> [[TMP2]], i64 2) 12fc382db2SAlexey Bataev; CHECK-NEXT: store <4 x i16> [[TMP5]], ptr [[P1]], align 2 13e83c6ddfSAlexey Bataev; CHECK-NEXT: ret void 14e83c6ddfSAlexey Bataev; 15e83c6ddfSAlexey Bataev %l1 = load i16, ptr %p, align 2 16e83c6ddfSAlexey Bataev %gep1 = getelementptr inbounds i8, ptr %p, i64 2 17e83c6ddfSAlexey Bataev %l2 = load i16, ptr %gep1, align 2 18e83c6ddfSAlexey Bataev %gep2 = getelementptr inbounds i8, ptr %p, i64 16 19e83c6ddfSAlexey Bataev %l3 = load i16, ptr %gep2, align 2 20e83c6ddfSAlexey Bataev %gep3 = getelementptr inbounds i8, ptr %p, i64 18 21e83c6ddfSAlexey Bataev %l4 = load i16, ptr %gep3, align 2 22e83c6ddfSAlexey Bataev store i16 %l1, ptr %p1, align 2 23e83c6ddfSAlexey Bataev %geps1 = getelementptr inbounds i8, ptr %p1, i64 2 24e83c6ddfSAlexey Bataev store i16 %l2, ptr %geps1, align 2 25e83c6ddfSAlexey Bataev %geps2 = getelementptr inbounds i8, ptr %p1, i64 4 26e83c6ddfSAlexey Bataev store i16 %l3, ptr %geps2, align 2 27e83c6ddfSAlexey Bataev %geps3 = getelementptr inbounds i8, ptr %p1, i64 6 28e83c6ddfSAlexey Bataev store i16 %l4, ptr %geps3, align 2 29e83c6ddfSAlexey Bataev ret void 30e83c6ddfSAlexey Bataev} 31e83c6ddfSAlexey Bataev 32