1*f7f7574aSYingwei Zheng; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2*f7f7574aSYingwei Zheng; RUN: opt < %s -passes=instcombine -S | FileCheck %s 3*f7f7574aSYingwei Zheng 4*f7f7574aSYingwei Zhengdefine i1 @test_switch_with_neg(i32 %a) { 5*f7f7574aSYingwei Zheng; CHECK-LABEL: define i1 @test_switch_with_neg( 6*f7f7574aSYingwei Zheng; CHECK-SAME: i32 [[A:%.*]]) { 7*f7f7574aSYingwei Zheng; CHECK-NEXT: entry: 8*f7f7574aSYingwei Zheng; CHECK-NEXT: switch i32 [[A]], label [[SW_DEFAULT:%.*]] [ 9*f7f7574aSYingwei Zheng; CHECK-NEXT: i32 -37, label [[SW_BB:%.*]] 10*f7f7574aSYingwei Zheng; CHECK-NEXT: i32 -38, label [[SW_BB]] 11*f7f7574aSYingwei Zheng; CHECK-NEXT: i32 -39, label [[SW_BB]] 12*f7f7574aSYingwei Zheng; CHECK-NEXT: ] 13*f7f7574aSYingwei Zheng; CHECK: sw.bb: 14*f7f7574aSYingwei Zheng; CHECK-NEXT: ret i1 true 15*f7f7574aSYingwei Zheng; CHECK: sw.default: 16*f7f7574aSYingwei Zheng; CHECK-NEXT: ret i1 false 17*f7f7574aSYingwei Zheng; 18*f7f7574aSYingwei Zhengentry: 19*f7f7574aSYingwei Zheng %a.neg = sub i32 0, %a 20*f7f7574aSYingwei Zheng switch i32 %a.neg, label %sw.default [ 21*f7f7574aSYingwei Zheng i32 37, label %sw.bb 22*f7f7574aSYingwei Zheng i32 38, label %sw.bb 23*f7f7574aSYingwei Zheng i32 39, label %sw.bb 24*f7f7574aSYingwei Zheng ] 25*f7f7574aSYingwei Zheng 26*f7f7574aSYingwei Zhengsw.bb: 27*f7f7574aSYingwei Zheng ret i1 true 28*f7f7574aSYingwei Zhengsw.default: 29*f7f7574aSYingwei Zheng ret i1 false 30*f7f7574aSYingwei Zheng} 31*f7f7574aSYingwei Zheng 32*f7f7574aSYingwei Zhengdefine i1 @test_switch_with_sub(i32 %a) { 33*f7f7574aSYingwei Zheng; CHECK-LABEL: define i1 @test_switch_with_sub( 34*f7f7574aSYingwei Zheng; CHECK-SAME: i32 [[A:%.*]]) { 35*f7f7574aSYingwei Zheng; CHECK-NEXT: entry: 36*f7f7574aSYingwei Zheng; CHECK-NEXT: switch i32 [[A]], label [[SW_DEFAULT:%.*]] [ 37*f7f7574aSYingwei Zheng; CHECK-NEXT: i32 0, label [[SW_BB:%.*]] 38*f7f7574aSYingwei Zheng; CHECK-NEXT: i32 -1, label [[SW_BB]] 39*f7f7574aSYingwei Zheng; CHECK-NEXT: i32 -2, label [[SW_BB]] 40*f7f7574aSYingwei Zheng; CHECK-NEXT: ] 41*f7f7574aSYingwei Zheng; CHECK: sw.bb: 42*f7f7574aSYingwei Zheng; CHECK-NEXT: ret i1 true 43*f7f7574aSYingwei Zheng; CHECK: sw.default: 44*f7f7574aSYingwei Zheng; CHECK-NEXT: ret i1 false 45*f7f7574aSYingwei Zheng; 46*f7f7574aSYingwei Zhengentry: 47*f7f7574aSYingwei Zheng %a.neg = sub i32 37, %a 48*f7f7574aSYingwei Zheng switch i32 %a.neg, label %sw.default [ 49*f7f7574aSYingwei Zheng i32 37, label %sw.bb 50*f7f7574aSYingwei Zheng i32 38, label %sw.bb 51*f7f7574aSYingwei Zheng i32 39, label %sw.bb 52*f7f7574aSYingwei Zheng ] 53*f7f7574aSYingwei Zheng 54*f7f7574aSYingwei Zhengsw.bb: 55*f7f7574aSYingwei Zheng ret i1 true 56*f7f7574aSYingwei Zhengsw.default: 57*f7f7574aSYingwei Zheng ret i1 false 58*f7f7574aSYingwei Zheng} 59*f7f7574aSYingwei Zheng 60*f7f7574aSYingwei Zheng; Negative tests 61*f7f7574aSYingwei Zheng 62*f7f7574aSYingwei Zhengdefine i1 @test_switch_with_sub_nonconst(i32 %a, i32 %b) { 63*f7f7574aSYingwei Zheng; CHECK-LABEL: define i1 @test_switch_with_sub_nonconst( 64*f7f7574aSYingwei Zheng; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { 65*f7f7574aSYingwei Zheng; CHECK-NEXT: entry: 66*f7f7574aSYingwei Zheng; CHECK-NEXT: [[A_NEG:%.*]] = sub i32 [[B]], [[A]] 67*f7f7574aSYingwei Zheng; CHECK-NEXT: switch i32 [[A_NEG]], label [[SW_DEFAULT:%.*]] [ 68*f7f7574aSYingwei Zheng; CHECK-NEXT: i32 37, label [[SW_BB:%.*]] 69*f7f7574aSYingwei Zheng; CHECK-NEXT: i32 38, label [[SW_BB]] 70*f7f7574aSYingwei Zheng; CHECK-NEXT: i32 39, label [[SW_BB]] 71*f7f7574aSYingwei Zheng; CHECK-NEXT: ] 72*f7f7574aSYingwei Zheng; CHECK: sw.bb: 73*f7f7574aSYingwei Zheng; CHECK-NEXT: ret i1 true 74*f7f7574aSYingwei Zheng; CHECK: sw.default: 75*f7f7574aSYingwei Zheng; CHECK-NEXT: ret i1 false 76*f7f7574aSYingwei Zheng; 77*f7f7574aSYingwei Zhengentry: 78*f7f7574aSYingwei Zheng %a.neg = sub i32 %b, %a 79*f7f7574aSYingwei Zheng switch i32 %a.neg, label %sw.default [ 80*f7f7574aSYingwei Zheng i32 37, label %sw.bb 81*f7f7574aSYingwei Zheng i32 38, label %sw.bb 82*f7f7574aSYingwei Zheng i32 39, label %sw.bb 83*f7f7574aSYingwei Zheng ] 84*f7f7574aSYingwei Zheng 85*f7f7574aSYingwei Zhengsw.bb: 86*f7f7574aSYingwei Zheng ret i1 true 87*f7f7574aSYingwei Zhengsw.default: 88*f7f7574aSYingwei Zheng ret i1 false 89*f7f7574aSYingwei Zheng} 90