1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -instcombine -S | FileCheck %s 3 4declare { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32>, <2 x i32>) 5 6declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) 7 8declare { i8, i1 } @llvm.sadd.with.overflow.i8(i8, i8) 9 10define { i32, i1 } @simple_fold(i32) { 11; CHECK-LABEL: @simple_fold( 12; CHECK-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP0:%.*]], 7 13; CHECK-NEXT: [[TMP3:%.*]] = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[TMP2]], i32 13) 14; CHECK-NEXT: ret { i32, i1 } [[TMP3]] 15; 16 %2 = add nsw i32 %0, 7 17 %3 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %2, i32 13) 18 ret { i32, i1 } %3 19} 20 21define { i32, i1 } @fold_mixed_signs(i32) { 22; CHECK-LABEL: @fold_mixed_signs( 23; CHECK-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP0:%.*]], 13 24; CHECK-NEXT: [[TMP3:%.*]] = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[TMP2]], i32 -7) 25; CHECK-NEXT: ret { i32, i1 } [[TMP3]] 26; 27 %2 = add nsw i32 %0, 13 28 %3 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %2, i32 -7) 29 ret { i32, i1 } %3 30} 31 32define { i8, i1 } @no_fold_on_constant_add_overflow(i8) { 33; CHECK-LABEL: @no_fold_on_constant_add_overflow( 34; CHECK-NEXT: [[TMP2:%.*]] = add nsw i8 [[TMP0:%.*]], 127 35; CHECK-NEXT: [[TMP3:%.*]] = tail call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[TMP2]], i8 127) 36; CHECK-NEXT: ret { i8, i1 } [[TMP3]] 37; 38 %2 = add nsw i8 %0, 127 39 %3 = tail call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 %2, i8 127) 40 ret { i8, i1 } %3 41} 42 43define { <2 x i32>, <2 x i1> } @fold_simple_splat_constant(<2 x i32>) { 44; CHECK-LABEL: @fold_simple_splat_constant( 45; CHECK-NEXT: [[TMP2:%.*]] = add nsw <2 x i32> [[TMP0:%.*]], <i32 12, i32 12> 46; CHECK-NEXT: [[TMP3:%.*]] = tail call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[TMP2]], <2 x i32> <i32 30, i32 30>) 47; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[TMP3]] 48; 49 %2 = add nsw <2 x i32> %0, <i32 12, i32 12> 50 %3 = tail call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> %2, <2 x i32> <i32 30, i32 30>) 51 ret { <2 x i32>, <2 x i1> } %3 52} 53 54define { <2 x i32>, <2 x i1> } @no_fold_splat_undef_constant(<2 x i32>) { 55; CHECK-LABEL: @no_fold_splat_undef_constant( 56; CHECK-NEXT: [[TMP2:%.*]] = add nsw <2 x i32> [[TMP0:%.*]], <i32 12, i32 undef> 57; CHECK-NEXT: [[TMP3:%.*]] = tail call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[TMP2]], <2 x i32> <i32 30, i32 30>) 58; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[TMP3]] 59; 60 %2 = add nsw <2 x i32> %0, <i32 12, i32 undef> 61 %3 = tail call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> %2, <2 x i32> <i32 30, i32 30>) 62 ret { <2 x i32>, <2 x i1> } %3 63} 64 65define { <2 x i32>, <2 x i1> } @no_fold_splat_not_constant(<2 x i32>, <2 x i32>) { 66; CHECK-LABEL: @no_fold_splat_not_constant( 67; CHECK-NEXT: [[TMP3:%.*]] = add nsw <2 x i32> [[TMP0:%.*]], [[TMP1:%.*]] 68; CHECK-NEXT: [[TMP4:%.*]] = tail call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[TMP3]], <2 x i32> <i32 30, i32 30>) 69; CHECK-NEXT: ret { <2 x i32>, <2 x i1> } [[TMP4]] 70; 71 %3 = add nsw <2 x i32> %0, %1 72 %4 = tail call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> %3, <2 x i32> <i32 30, i32 30>) 73 ret { <2 x i32>, <2 x i1> } %4 74} 75 76define { i32, i1 } @fold_nuwnsw(i32) { 77; CHECK-LABEL: @fold_nuwnsw( 78; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i32 [[TMP0:%.*]], 12 79; CHECK-NEXT: [[TMP3:%.*]] = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[TMP2]], i32 30) 80; CHECK-NEXT: ret { i32, i1 } [[TMP3]] 81; 82 %2 = add nuw nsw i32 %0, 12 83 %3 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %2, i32 30) 84 ret { i32, i1 } %3 85} 86 87define { i32, i1 } @no_fold_nuw(i32) { 88; CHECK-LABEL: @no_fold_nuw( 89; CHECK-NEXT: [[TMP2:%.*]] = add nuw i32 [[TMP0:%.*]], 12 90; CHECK-NEXT: [[TMP3:%.*]] = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[TMP2]], i32 30) 91; CHECK-NEXT: ret { i32, i1 } [[TMP3]] 92; 93 %2 = add nuw i32 %0, 12 94 %3 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %2, i32 30) 95 ret { i32, i1 } %3 96} 97