1cb8d83a7SYingwei Zheng; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2cb8d83a7SYingwei Zheng; RUN: opt -S -passes=instcombine < %s | FileCheck %s 3cb8d83a7SYingwei Zheng 4cb8d83a7SYingwei Zhengdefine i64 @pr80597(i1 %cond) { 5cb8d83a7SYingwei Zheng; CHECK-LABEL: define i64 @pr80597( 6cb8d83a7SYingwei Zheng; CHECK-SAME: i1 [[COND:%.*]]) { 7cb8d83a7SYingwei Zheng; CHECK-NEXT: entry: 8cb8d83a7SYingwei Zheng; CHECK-NEXT: [[ADD:%.*]] = select i1 [[COND]], i64 0, i64 -12884901888 9cb8d83a7SYingwei Zheng; CHECK-NEXT: [[SEXT1:%.*]] = add nsw i64 [[ADD]], 8836839514384105472 10cb8d83a7SYingwei Zheng; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[SEXT1]], -34359738368 11cb8d83a7SYingwei Zheng; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] 12cb8d83a7SYingwei Zheng; CHECK: if.else: 13cb8d83a7SYingwei Zheng; CHECK-NEXT: [[SEXT2:%.*]] = ashr exact i64 [[ADD]], 1 14*154c8a02SNikita Popov; CHECK-NEXT: [[ASHR:%.*]] = or disjoint i64 [[SEXT2]], 4418419761487020032 15cb8d83a7SYingwei Zheng; CHECK-NEXT: ret i64 [[ASHR]] 16cb8d83a7SYingwei Zheng; CHECK: if.then: 17cb8d83a7SYingwei Zheng; CHECK-NEXT: ret i64 0 18cb8d83a7SYingwei Zheng; 19cb8d83a7SYingwei Zhengentry: 20cb8d83a7SYingwei Zheng %add = select i1 %cond, i64 0, i64 4294967293 21cb8d83a7SYingwei Zheng %add8 = shl i64 %add, 32 22cb8d83a7SYingwei Zheng %sext1 = add i64 %add8, 8836839514384105472 23cb8d83a7SYingwei Zheng %cmp = icmp ult i64 %sext1, -34359738368 24cb8d83a7SYingwei Zheng br i1 %cmp, label %if.then, label %if.else 25cb8d83a7SYingwei Zheng 26cb8d83a7SYingwei Zhengif.else: 27cb8d83a7SYingwei Zheng %sext2 = or i64 %add8, 8836839522974040064 28cb8d83a7SYingwei Zheng %ashr = ashr i64 %sext2, 1 29cb8d83a7SYingwei Zheng ret i64 %ashr 30cb8d83a7SYingwei Zheng 31cb8d83a7SYingwei Zhengif.then: 32cb8d83a7SYingwei Zheng ret i64 0 33cb8d83a7SYingwei Zheng} 34