13978f37cSDhruv Chawla; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 2*0f152a55SDhruv Chawla; RUN: opt < %s -passes=infer-alignment -S | FileCheck %s 33978f37cSDhruv Chawla 43978f37cSDhruv Chawla; InferAlignment should be able to prove vector alignment in the 53978f37cSDhruv Chawla; presence of a few mild address computation tricks. 63978f37cSDhruv Chawla 73978f37cSDhruv Chawla; ------------------------------------------------------------------------------ 83978f37cSDhruv Chawla; alloca 93978f37cSDhruv Chawla; ------------------------------------------------------------------------------ 103978f37cSDhruv Chawla 113978f37cSDhruv Chawladefine void @alloca(<2 x i64> %y) { 123978f37cSDhruv Chawla; CHECK-LABEL: define void @alloca 133978f37cSDhruv Chawla; CHECK-SAME: (<2 x i64> [[Y:%.*]]) { 143978f37cSDhruv Chawla; CHECK-NEXT: [[ALLOCA:%.*]] = alloca <2 x i64>, align 16 15*0f152a55SDhruv Chawla; CHECK-NEXT: [[LOAD:%.*]] = load <2 x i64>, ptr [[ALLOCA]], align 16 16*0f152a55SDhruv Chawla; CHECK-NEXT: store <2 x i64> [[Y]], ptr [[ALLOCA]], align 16 173978f37cSDhruv Chawla; CHECK-NEXT: ret void 183978f37cSDhruv Chawla; 193978f37cSDhruv Chawla %alloca = alloca <2 x i64> 203978f37cSDhruv Chawla %load = load <2 x i64>, ptr %alloca, align 1 213978f37cSDhruv Chawla store <2 x i64> %y, ptr %alloca, align 1 223978f37cSDhruv Chawla ret void 233978f37cSDhruv Chawla} 243978f37cSDhruv Chawla 253978f37cSDhruv Chawla; ------------------------------------------------------------------------------ 263978f37cSDhruv Chawla; global 273978f37cSDhruv Chawla; ------------------------------------------------------------------------------ 283978f37cSDhruv Chawla 293978f37cSDhruv Chawla@x.vector = external global <2 x i64>, align 16 303978f37cSDhruv Chawla 313978f37cSDhruv Chawladefine void @global(<2 x i64> %y) { 323978f37cSDhruv Chawla; CHECK-LABEL: define void @global 333978f37cSDhruv Chawla; CHECK-SAME: (<2 x i64> [[Y:%.*]]) { 34*0f152a55SDhruv Chawla; CHECK-NEXT: [[LOAD:%.*]] = load <2 x i64>, ptr @x.vector, align 16 35*0f152a55SDhruv Chawla; CHECK-NEXT: store <2 x i64> [[Y]], ptr @x.vector, align 16 363978f37cSDhruv Chawla; CHECK-NEXT: ret void 373978f37cSDhruv Chawla; 383978f37cSDhruv Chawla %load = load <2 x i64>, ptr @x.vector, align 1 393978f37cSDhruv Chawla store <2 x i64> %y, ptr @x.vector, align 1 403978f37cSDhruv Chawla ret void 413978f37cSDhruv Chawla} 423978f37cSDhruv Chawla 433978f37cSDhruv Chawla; ------------------------------------------------------------------------------ 443978f37cSDhruv Chawla; getelementptr 453978f37cSDhruv Chawla; ------------------------------------------------------------------------------ 463978f37cSDhruv Chawla 473978f37cSDhruv Chawla@vector = external global <2 x i64>, align 16 483978f37cSDhruv Chawla@vector.arr = external global [13 x <2 x i64>], align 16 493978f37cSDhruv Chawla 503978f37cSDhruv Chawla; ------------------------------------------------------------------------------ 513978f37cSDhruv Chawla; 1d access 523978f37cSDhruv Chawla; ------------------------------------------------------------------------------ 533978f37cSDhruv Chawla 543978f37cSDhruv Chawladefine void @vector_singular(i32 %i, <2 x i64> %y) { 553978f37cSDhruv Chawla; CHECK-LABEL: define void @vector_singular 563978f37cSDhruv Chawla; CHECK-SAME: (i32 [[I:%.*]], <2 x i64> [[Y:%.*]]) { 573978f37cSDhruv Chawla; CHECK-NEXT: [[GEP:%.*]] = getelementptr <2 x i64>, ptr @vector, i32 [[I]] 58*0f152a55SDhruv Chawla; CHECK-NEXT: [[LOAD:%.*]] = load <2 x i64>, ptr [[GEP]], align 16 59*0f152a55SDhruv Chawla; CHECK-NEXT: store <2 x i64> [[Y]], ptr [[GEP]], align 16 603978f37cSDhruv Chawla; CHECK-NEXT: ret void 613978f37cSDhruv Chawla; 623978f37cSDhruv Chawla %gep = getelementptr <2 x i64>, ptr @vector, i32 %i 633978f37cSDhruv Chawla %load = load <2 x i64>, ptr %gep, align 1 643978f37cSDhruv Chawla store <2 x i64> %y, ptr %gep, align 1 653978f37cSDhruv Chawla ret void 663978f37cSDhruv Chawla} 673978f37cSDhruv Chawla 683978f37cSDhruv Chawla; ------------------------------------------------------------------------------ 693978f37cSDhruv Chawla; 2d access 703978f37cSDhruv Chawla; ------------------------------------------------------------------------------ 713978f37cSDhruv Chawla 723978f37cSDhruv Chawladefine void @vector_array(i32 %i, i32 %j, <2 x i64> %y) { 733978f37cSDhruv Chawla; CHECK-LABEL: define void @vector_array 743978f37cSDhruv Chawla; CHECK-SAME: (i32 [[I:%.*]], i32 [[J:%.*]], <2 x i64> [[Y:%.*]]) { 753978f37cSDhruv Chawla; CHECK-NEXT: [[GEP:%.*]] = getelementptr [13 x <2 x i64>], ptr @vector.arr, i32 [[I]], i32 [[J]] 76*0f152a55SDhruv Chawla; CHECK-NEXT: [[LOAD:%.*]] = load <2 x i64>, ptr [[GEP]], align 16 77*0f152a55SDhruv Chawla; CHECK-NEXT: store <2 x i64> [[Y]], ptr [[GEP]], align 16 783978f37cSDhruv Chawla; CHECK-NEXT: ret void 793978f37cSDhruv Chawla; 803978f37cSDhruv Chawla %gep = getelementptr [13 x <2 x i64>], ptr @vector.arr, i32 %i, i32 %j 813978f37cSDhruv Chawla %load = load <2 x i64>, ptr %gep, align 1 823978f37cSDhruv Chawla store <2 x i64> %y, ptr %gep, align 1 833978f37cSDhruv Chawla ret void 843978f37cSDhruv Chawla} 853978f37cSDhruv Chawla 863978f37cSDhruv Chawla; ------------------------------------------------------------------------------ 873978f37cSDhruv Chawla; non-vector array type 883978f37cSDhruv Chawla; ------------------------------------------------------------------------------ 893978f37cSDhruv Chawla 903978f37cSDhruv Chawla; When we see a unaligned load or store from an insufficiently aligned global or 913978f37cSDhruv Chawla; alloca, increase the alignment, turning it into an aligned load or store. 923978f37cSDhruv Chawla@x.array = internal global [4 x i32] zeroinitializer 933978f37cSDhruv Chawla 943978f37cSDhruv Chawladefine void @nonvector_array() { 953978f37cSDhruv Chawla; CHECK-LABEL: define void @nonvector_array() { 96*0f152a55SDhruv Chawla; CHECK-NEXT: [[LOAD_0:%.*]] = load <16 x i8>, ptr @x.array, align 16 97*0f152a55SDhruv Chawla; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr @x.array, align 16 983978f37cSDhruv Chawla; CHECK-NEXT: [[GEP:%.*]] = getelementptr [4 x i32], ptr @x.array, i16 0, i16 2 99*0f152a55SDhruv Chawla; CHECK-NEXT: [[LOAD_1:%.*]] = load <16 x i8>, ptr [[GEP]], align 8 100*0f152a55SDhruv Chawla; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr [[GEP]], align 8 1013978f37cSDhruv Chawla; CHECK-NEXT: ret void 1023978f37cSDhruv Chawla; 1033978f37cSDhruv Chawla %load.0 = load <16 x i8>, ptr @x.array, align 1 1043978f37cSDhruv Chawla store <16 x i8> zeroinitializer, ptr @x.array, align 1 1053978f37cSDhruv Chawla 1063978f37cSDhruv Chawla %gep = getelementptr [4 x i32], ptr @x.array, i16 0, i16 2 1073978f37cSDhruv Chawla %load.1 = load <16 x i8>, ptr %gep, align 1 1083978f37cSDhruv Chawla store <16 x i8> zeroinitializer, ptr %gep, align 1 1093978f37cSDhruv Chawla 1103978f37cSDhruv Chawla ret void 1113978f37cSDhruv Chawla} 112