xref: /llvm-project/llvm/test/MC/ARM/thumb-add-sub-width.s (revision d771f6cb16043afb97e2c4b3a6a02ff5aa963923)
1*d771f6cbSOliver Stannard// RUN: llvm-mc -triple thumbv6m -show-encoding < %s | FileCheck %s
2*d771f6cbSOliver Stannard
3*d771f6cbSOliver Stannard  .text
4*d771f6cbSOliver Stannard  .thumb
5*d771f6cbSOliver Stannard
6*d771f6cbSOliver Stannard  // Check that the correct encoding of the add and sub instructions is
7*d771f6cbSOliver Stannard  // selected, for all combinations of flag-setting, condition and 2- or
8*d771f6cbSOliver Stannard  // 3-operand syntax.
9*d771f6cbSOliver Stannard
10*d771f6cbSOliver Stannard  .arch armv6-m
11*d771f6cbSOliver Stannard  add r0, r0, r1     // T2
12*d771f6cbSOliver Stannard  add r0, r1         // T2
13*d771f6cbSOliver Stannard  adds r0, r0, r1    // T1
14*d771f6cbSOliver Stannard  adds r0, r1        // T1
15*d771f6cbSOliver Stannard// CHECK: add     r0, r1                  @ encoding: [0x08,0x44]
16*d771f6cbSOliver Stannard// CHECK: add     r0, r1                  @ encoding: [0x08,0x44]
17*d771f6cbSOliver Stannard// CHECK: adds    r0, r0, r1              @ encoding: [0x40,0x18]
18*d771f6cbSOliver Stannard// CHECK: adds    r0, r0, r1              @ encoding: [0x40,0x18]
19*d771f6cbSOliver Stannard
20*d771f6cbSOliver Stannard  .arch armv7-m
21*d771f6cbSOliver Stannard  add r0, r0, r1     // T2, T3
22*d771f6cbSOliver Stannard  add r0, r1         // T2, T3
23*d771f6cbSOliver Stannard  adds r0, r0, r1    // T1, T3
24*d771f6cbSOliver Stannard  adds r0, r1        // T1, T3
25*d771f6cbSOliver Stannard// CHECK: add     r0, r1                  @ encoding: [0x08,0x44]
26*d771f6cbSOliver Stannard// CHECK: add     r0, r1                  @ encoding: [0x08,0x44]
27*d771f6cbSOliver Stannard// CHECK: adds    r0, r0, r1              @ encoding: [0x40,0x18]
28*d771f6cbSOliver Stannard// CHECK: adds    r0, r0, r1              @ encoding: [0x40,0x18]
29*d771f6cbSOliver Stannard
30*d771f6cbSOliver Stannard  itttt eq
31*d771f6cbSOliver Stannard// CHECK: itttt   eq                      @ encoding: [0x01,0xbf]
32*d771f6cbSOliver Stannard  addeq r0, r0, r1   // T1, T2, T3
33*d771f6cbSOliver Stannard  addeq r0, r1       // T2, T1, T3
34*d771f6cbSOliver Stannard  addseq r0, r0, r1  // T3
35*d771f6cbSOliver Stannard  addseq r0, r1      // T3
36*d771f6cbSOliver Stannard  // NOTE: Both T1 and T2 are valid for these two instructions, which one is
37*d771f6cbSOliver Stannard  // the preferred varies depending on whether the 2- or 3-operand syntax was
38*d771f6cbSOliver Stannard  // used.
39*d771f6cbSOliver Stannard// CHECK: addeq   r0, r0, r1              @ encoding: [0x40,0x18]
40*d771f6cbSOliver Stannard// CHECK: addeq   r0, r1                  @ encoding: [0x08,0x44]
41*d771f6cbSOliver Stannard// CHECK: addseq.w        r0, r0, r1      @ encoding: [0x10,0xeb,0x01,0x00]
42*d771f6cbSOliver Stannard// CHECK: addseq.w        r0, r0, r1      @ encoding: [0x10,0xeb,0x01,0x00]
43*d771f6cbSOliver Stannard
44*d771f6cbSOliver Stannard  .arch armv6-m
45*d771f6cbSOliver Stannard  // NOTE: There is no non-flag-setting sub instruction for v6-M
46*d771f6cbSOliver Stannard  subs r0, r0, r1    // T1, T2
47*d771f6cbSOliver Stannard  subs r0, r1        // T1, T2
48*d771f6cbSOliver Stannard// CHECK: subs    r0, r0, r1              @ encoding: [0x40,0x1a]
49*d771f6cbSOliver Stannard// CHECK: subs    r0, r0, r1              @ encoding: [0x40,0x1a]
50*d771f6cbSOliver Stannard
51*d771f6cbSOliver Stannard  .arch armv7-m
52*d771f6cbSOliver Stannard  sub r0, r0, r1     // T2
53*d771f6cbSOliver Stannard  sub r0, r1         // T2
54*d771f6cbSOliver Stannard  subs r0, r0, r1    // T1, T2
55*d771f6cbSOliver Stannard  subs r0, r1        // T1, T2
56*d771f6cbSOliver Stannard// CHECK: sub.w   r0, r0, r1              @ encoding: [0xa0,0xeb,0x01,0x00]
57*d771f6cbSOliver Stannard// CHECK: sub.w   r0, r0, r1              @ encoding: [0xa0,0xeb,0x01,0x00]
58*d771f6cbSOliver Stannard// CHECK: subs    r0, r0, r1              @ encoding: [0x40,0x1a]
59*d771f6cbSOliver Stannard// CHECK: subs    r0, r0, r1              @ encoding: [0x40,0x1a]
60*d771f6cbSOliver Stannard
61*d771f6cbSOliver Stannard  itttt eq
62*d771f6cbSOliver Stannard// CHECK: itttt   eq                      @ encoding: [0x01,0xbf]
63*d771f6cbSOliver Stannard  subeq r0, r0, r1   // T1, T2
64*d771f6cbSOliver Stannard  subeq r0, r1       // T1, T2
65*d771f6cbSOliver Stannard  subseq r0, r0, r1  // T2
66*d771f6cbSOliver Stannard  subseq r0, r1      // T2
67*d771f6cbSOliver Stannard// CHECK: subeq   r0, r0, r1              @ encoding: [0x40,0x1a]
68*d771f6cbSOliver Stannard// CHECK: subeq   r0, r0, r1              @ encoding: [0x40,0x1a]
69*d771f6cbSOliver Stannard// CHECK: subseq.w        r0, r0, r1      @ encoding: [0xb0,0xeb,0x01,0x00]
70*d771f6cbSOliver Stannard// CHECK: subseq.w        r0, r0, r1      @ encoding: [0xb0,0xeb,0x01,0x00]
71