xref: /llvm-project/llvm/test/MC/ARM/armv8.6a-matmul-error.s (revision 659ca502453cb6f544f358bdf2a95df89cf7840b) 
1*659ca502SLuke Geeson// RUN: not llvm-mc -triple armv8a   -show-encoding -mattr=+i8mm < %s 2>&1 | FileCheck %s
2*659ca502SLuke Geeson// RUN: not llvm-mc -triple thumbv8a -show-encoding -mattr=+i8mm < %s 2>&1 | FileCheck %s
3*659ca502SLuke Geeson
4*659ca502SLuke Geeson
5*659ca502SLuke Geeson// VSMMLA, VUMMLA, VUSMMLA
6*659ca502SLuke Geeson
7*659ca502SLuke Geeson// Data type specifier must match instruction
8*659ca502SLuke Geeson
9*659ca502SLuke Geesonvsmmla.u8 q0, q1, q2
10*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
11*659ca502SLuke Geeson// CHECK-NEXT:    vsmmla.u8 q0, q1, q2
12*659ca502SLuke Geeson// CHECK-NEXT: {{^      \^}}
13*659ca502SLuke Geeson
14*659ca502SLuke Geesonvummla.s8 q0, q1, q2
15*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
16*659ca502SLuke Geeson// CHECK-NEXT:    vummla.s8 q0, q1, q2
17*659ca502SLuke Geeson// CHECK-NEXT: {{^      \^}}
18*659ca502SLuke Geeson
19*659ca502SLuke Geesonvusmmla.u8 q0, q1, q2
20*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
21*659ca502SLuke Geeson// CHECK-NEXT:    vusmmla.u8 q0, q1, q2
22*659ca502SLuke Geeson// CHECK-NEXT: {{^       \^}}
23*659ca502SLuke Geeson
24*659ca502SLuke Geeson
25*659ca502SLuke Geeson// Incorrect register type
26*659ca502SLuke Geeson
27*659ca502SLuke Geesonvsmmla.s8 d0, q1, q2
28*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [q0, q15]
29*659ca502SLuke Geeson// CHECK-NEXT:    vsmmla.s8 d0, q1, q2
30*659ca502SLuke Geeson// CHECK-NEXT: {{^          \^}}
31*659ca502SLuke Geeson
32*659ca502SLuke Geesonvummla.u8 q0, d1, q2
33*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [q0, q15]
34*659ca502SLuke Geeson// CHECK-NEXT:    vummla.u8 q0, d1, q2
35*659ca502SLuke Geeson// CHECK-NEXT: {{^              \^}}
36*659ca502SLuke Geeson
37*659ca502SLuke Geesonvusmmla.s8 q0, q1, d2
38*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [q0, q15]
39*659ca502SLuke Geeson// CHECK-NEXT:    vusmmla.s8 q0, q1, d2
40*659ca502SLuke Geeson// CHECK-NEXT: {{^                   \^}}
41*659ca502SLuke Geeson
42*659ca502SLuke Geeson
43*659ca502SLuke Geeson// VUSDOT (vector)
44*659ca502SLuke Geeson
45*659ca502SLuke Geeson// Data type specifier must match instruction
46*659ca502SLuke Geeson
47*659ca502SLuke Geesonvusdot.u8 q0, q1, q2
48*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
49*659ca502SLuke Geeson// CHECK-NEXT:    vusdot.u8 q0, q1, q2
50*659ca502SLuke Geeson// CHECK-NEXT: {{^      \^}}
51*659ca502SLuke Geeson
52*659ca502SLuke Geeson// Mis-matched register types
53*659ca502SLuke Geeson
54*659ca502SLuke Geesonvusdot.s8 q0, d1, d2
55*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [d0, d31]
56*659ca502SLuke Geesonvusdot.s8 d0, q1, d2
57*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [d0, d31]
58*659ca502SLuke Geesonvusdot.s8 d0, d1, q2
59*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [d0, d31]
60*659ca502SLuke Geeson
61*659ca502SLuke Geeson
62*659ca502SLuke Geeson// VUSDOT, VSUDOT (by scalar)
63*659ca502SLuke Geeson
64*659ca502SLuke Geeson// Data type specifier must match instruction
65*659ca502SLuke Geeson
66*659ca502SLuke Geesonvusdot.u8 d0, d1, d2[0]
67*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
68*659ca502SLuke Geeson// CHECK-NEXT:    vusdot.u8 d0, d1, d2[0]
69*659ca502SLuke Geeson// CHECK-NEXT: {{^      \^}}
70*659ca502SLuke Geeson
71*659ca502SLuke Geesonvsudot.s8 d0, d1, d2[0]
72*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
73*659ca502SLuke Geeson// CHECK-NEXT:    vsudot.s8 d0, d1, d2[0]
74*659ca502SLuke Geeson// CHECK-NEXT: {{^      \^}}
75*659ca502SLuke Geeson
76*659ca502SLuke Geeson// Incorrect register types
77*659ca502SLuke Geeson
78*659ca502SLuke Geesonvusdot.s8 q0, d1, d2[0]
79*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid instruction, any one of the following would fix this:
80*659ca502SLuke Geeson// CHECK-NEXT: vusdot.s8 q0, d1, d2[0]
81*659ca502SLuke Geeson// CHECK: [[@LINE-3]]:{{[0-9]+}}: note: operand must be a register in range [d0, d31]
82*659ca502SLuke Geeson// CHECK-NEXT: vusdot.s8 q0, d1, d2[0]
83*659ca502SLuke Geeson// CHECK-NEXT: {{^       \^}}
84*659ca502SLuke Geeson// CHECK: [[@LINE-6]]:{{[0-9]+}}: note: operand must be a register in range [q0, q15]
85*659ca502SLuke Geeson// CHECK-NEXT: vusdot.s8 q0, d1, d2[0]
86*659ca502SLuke Geeson// CHECK-NEXT: {{^           \^}}
87*659ca502SLuke Geeson
88*659ca502SLuke Geesonvusdot.s8 d0, q1, d2[0]
89*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid instruction, any one of the following would fix this:
90*659ca502SLuke Geeson// CHECK-NEXT: vusdot.s8 d0, q1, d2[0]
91*659ca502SLuke Geeson// CHECK: [[@LINE-3]]:{{[0-9]+}}: note: operand must be a register in range [d0, d31]
92*659ca502SLuke Geeson// CHECK-NEXT: vusdot.s8 d0, q1, d2[0]
93*659ca502SLuke Geeson// CHECK-NEXT: {{^           \^}}
94*659ca502SLuke Geeson// CHECK: [[@LINE-6]]:{{[0-9]+}}: note: operand must be a register in range [q0, q15]
95*659ca502SLuke Geeson// CHECK-NEXT: vusdot.s8 d0, q1, d2[0]
96*659ca502SLuke Geeson// CHECK-NEXT: {{^       \^}}
97*659ca502SLuke Geeson
98*659ca502SLuke Geesonvusdot.s8 q0, q1, q2[0]
99*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid instruction, any one of the following would fix this:
100*659ca502SLuke Geeson// CHECK-NEXT: vusdot.s8 q0, q1, q2[0]
101*659ca502SLuke Geeson// CHECK: [[@LINE-3]]:{{[0-9]+}}: note: operand must be a register in range [d0, d15]
102*659ca502SLuke Geeson// CHECK-NEXT: vusdot.s8 q0, q1, q2[0]
103*659ca502SLuke Geeson// CHECK-NEXT: {{^               \^}}
104*659ca502SLuke Geeson// CHECK: [[@LINE-6]]:{{[0-9]+}}: note: too many operands for instruction
105*659ca502SLuke Geeson// CHECK-NEXT: vusdot.s8 q0, q1, q2[0]
106*659ca502SLuke Geeson// CHECK-NEXT: {{^                 \^}}
107*659ca502SLuke Geeson
108*659ca502SLuke Geeson// Out of range lane index
109*659ca502SLuke Geeson
110*659ca502SLuke Geesonvusdot.s8 d0, d1, d2[2]
111*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
112*659ca502SLuke Geesonvsudot.u8 q0, q1, d2[2]
113*659ca502SLuke Geeson// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
114