1*7258735fSSaleem Abdulrasool// RUN: not llvm-mc -triple arm-eabi -mattr=+v5te %s -o /dev/null 2>&1 | FileCheck %s 20e1dd8c1STilmann Scheller// 31aebfa0aSTilmann Scheller// rdar://14479793 41aebfa0aSTilmann Scheller 51aebfa0aSTilmann Schellerldrd r1, r2, [pc, #0] 61aebfa0aSTilmann Schellerldrd r1, r2, [r3, #4] 71aebfa0aSTilmann Schellerldrd r1, r2, [r3], #4 81aebfa0aSTilmann Schellerldrd r1, r2, [r3, #4]! 91aebfa0aSTilmann Schellerldrd r1, r2, [r3, -r4]! 101aebfa0aSTilmann Schellerldrd r1, r2, [r3, r4] 111aebfa0aSTilmann Schellerldrd r1, r2, [r3], r4 120e1dd8c1STilmann Scheller// CHECK: error: Rt must be even-numbered 130e1dd8c1STilmann Scheller// CHECK: error: Rt must be even-numbered 140e1dd8c1STilmann Scheller// CHECK: error: Rt must be even-numbered 150e1dd8c1STilmann Scheller// CHECK: error: Rt must be even-numbered 160e1dd8c1STilmann Scheller// CHECK: error: Rt must be even-numbered 170e1dd8c1STilmann Scheller// CHECK: error: Rt must be even-numbered 180e1dd8c1STilmann Scheller// CHECK: error: Rt must be even-numbered 190e1dd8c1STilmann Scheller 200e1dd8c1STilmann Schellerldrd r0, r3, [pc, #0] 210e1dd8c1STilmann Schellerldrd r0, r3, [r4, #4] 220e1dd8c1STilmann Schellerldrd r0, r3, [r4], #4 230e1dd8c1STilmann Schellerldrd r0, r3, [r4, #4]! 240e1dd8c1STilmann Schellerldrd r0, r3, [r4, -r5]! 250e1dd8c1STilmann Schellerldrd r0, r3, [r4, r5] 2638c4ef68STilmann Schellerldrd r0, r3, [r4], r5 270e1dd8c1STilmann Scheller// CHECK: error: destination operands must be sequential 280e1dd8c1STilmann Scheller// CHECK: error: destination operands must be sequential 290e1dd8c1STilmann Scheller// CHECK: error: destination operands must be sequential 300e1dd8c1STilmann Scheller// CHECK: error: destination operands must be sequential 310e1dd8c1STilmann Scheller// CHECK: error: destination operands must be sequential 320e1dd8c1STilmann Scheller// CHECK: error: destination operands must be sequential 330e1dd8c1STilmann Scheller// CHECK: error: destination operands must be sequential 340e1dd8c1STilmann Scheller 350e1dd8c1STilmann Schellerldrd lr, pc, [pc, #0] 360e1dd8c1STilmann Schellerldrd lr, pc, [r3, #4] 370e1dd8c1STilmann Schellerldrd lr, pc, [r3], #4 380e1dd8c1STilmann Schellerldrd lr, pc, [r3, #4]! 390e1dd8c1STilmann Schellerldrd lr, pc, [r3, -r4]! 400e1dd8c1STilmann Schellerldrd lr, pc, [r3, r4] 410e1dd8c1STilmann Schellerldrd lr, pc, [r3], r4 420e1dd8c1STilmann Scheller// CHECK: error: Rt can't be R14 430e1dd8c1STilmann Scheller// CHECK: error: Rt can't be R14 440e1dd8c1STilmann Scheller// CHECK: error: Rt can't be R14 450e1dd8c1STilmann Scheller// CHECK: error: Rt can't be R14 460e1dd8c1STilmann Scheller// CHECK: error: Rt can't be R14 470e1dd8c1STilmann Scheller// CHECK: error: Rt can't be R14 480e1dd8c1STilmann Scheller// CHECK: error: Rt can't be R14 49255722beSTilmann Scheller 50255722beSTilmann Schellerldrd r0, r1, [r0], #4 51255722beSTilmann Schellerldrd r0, r1, [r1], #4 52255722beSTilmann Schellerldrd r0, r1, [r0, #4]! 53255722beSTilmann Schellerldrd r0, r1, [r1, #4]! 540e1dd8c1STilmann Scheller// CHECK: error: base register needs to be different from destination registers 550e1dd8c1STilmann Scheller// CHECK: error: base register needs to be different from destination registers 560e1dd8c1STilmann Scheller// CHECK: error: base register needs to be different from destination registers 570e1dd8c1STilmann Scheller// CHECK: error: base register needs to be different from destination registers 58