1f1cc7913SSimon Pilgrim; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2f1cc7913SSimon Pilgrim; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefixes=X86 3f1cc7913SSimon Pilgrim; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefixes=X64 4f1cc7913SSimon Pilgrim 5f1cc7913SSimon Pilgrim; Fold and(sextinreg(v0,i5),sextinreg(v1,i5)) -> sextinreg(and(v0,v1),i5) 6f1cc7913SSimon Pilgrimdefine i32 @sextinreg_i32(ptr %p0, ptr %p1) { 7f1cc7913SSimon Pilgrim; X86-LABEL: sextinreg_i32: 8f1cc7913SSimon Pilgrim; X86: # %bb.0: 9f1cc7913SSimon Pilgrim; X86-NEXT: movl {{[0-9]+}}(%esp), %eax 10f1cc7913SSimon Pilgrim; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx 11f1cc7913SSimon Pilgrim; X86-NEXT: movzbl (%ecx), %ecx 12f1cc7913SSimon Pilgrim; X86-NEXT: movzbl (%eax), %eax 13f1cc7913SSimon Pilgrim; X86-NEXT: andl %ecx, %eax 14f1cc7913SSimon Pilgrim; X86-NEXT: shll $27, %eax 15f1cc7913SSimon Pilgrim; X86-NEXT: sarl $27, %eax 16f1cc7913SSimon Pilgrim; X86-NEXT: retl 17f1cc7913SSimon Pilgrim; 18f1cc7913SSimon Pilgrim; X64-LABEL: sextinreg_i32: 19f1cc7913SSimon Pilgrim; X64: # %bb.0: 20f1cc7913SSimon Pilgrim; X64-NEXT: movzbl (%rdi), %ecx 21f1cc7913SSimon Pilgrim; X64-NEXT: movzbl (%rsi), %eax 22f1cc7913SSimon Pilgrim; X64-NEXT: andl %ecx, %eax 23f1cc7913SSimon Pilgrim; X64-NEXT: shll $27, %eax 24f1cc7913SSimon Pilgrim; X64-NEXT: sarl $27, %eax 25f1cc7913SSimon Pilgrim; X64-NEXT: retq 26f1cc7913SSimon Pilgrim %v0 = load i8, ptr %p0, align 1 27f1cc7913SSimon Pilgrim %v1 = load i8, ptr %p1, align 1 28f1cc7913SSimon Pilgrim %x0 = zext i8 %v0 to i32 29f1cc7913SSimon Pilgrim %x1 = zext i8 %v1 to i32 30f1cc7913SSimon Pilgrim %l0 = shl i32 %x0, 27 31f1cc7913SSimon Pilgrim %l1 = shl i32 %x1, 27 32f1cc7913SSimon Pilgrim %a0 = ashr exact i32 %l0, 27 33f1cc7913SSimon Pilgrim %a1 = ashr exact i32 %l1, 27 34f1cc7913SSimon Pilgrim %and = and i32 %a0, %a1 35f1cc7913SSimon Pilgrim ret i32 %and 36f1cc7913SSimon Pilgrim} 37f1cc7913SSimon Pilgrim 38*697f6059SSimon Pilgrim; MISMATCH and(sextinreg(v0,i2),sextinreg(v1,i5)) != sextinreg(and(v0,v1),i2) 39f1cc7913SSimon Pilgrimdefine i32 @sextinreg_i32_mismatch(ptr %p0, ptr %p1) { 40f1cc7913SSimon Pilgrim; X86-LABEL: sextinreg_i32_mismatch: 41f1cc7913SSimon Pilgrim; X86: # %bb.0: 42f1cc7913SSimon Pilgrim; X86-NEXT: movl {{[0-9]+}}(%esp), %eax 43f1cc7913SSimon Pilgrim; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx 44f1cc7913SSimon Pilgrim; X86-NEXT: movzbl (%ecx), %ecx 45f1cc7913SSimon Pilgrim; X86-NEXT: movzbl (%eax), %eax 46*697f6059SSimon Pilgrim; X86-NEXT: shll $30, %ecx 47*697f6059SSimon Pilgrim; X86-NEXT: sarl $30, %ecx 48*697f6059SSimon Pilgrim; X86-NEXT: shll $27, %eax 49*697f6059SSimon Pilgrim; X86-NEXT: sarl $27, %eax 50f1cc7913SSimon Pilgrim; X86-NEXT: andl %ecx, %eax 51f1cc7913SSimon Pilgrim; X86-NEXT: retl 52f1cc7913SSimon Pilgrim; 53f1cc7913SSimon Pilgrim; X64-LABEL: sextinreg_i32_mismatch: 54f1cc7913SSimon Pilgrim; X64: # %bb.0: 55f1cc7913SSimon Pilgrim; X64-NEXT: movzbl (%rdi), %ecx 56f1cc7913SSimon Pilgrim; X64-NEXT: movzbl (%rsi), %eax 57*697f6059SSimon Pilgrim; X64-NEXT: shll $30, %ecx 58*697f6059SSimon Pilgrim; X64-NEXT: sarl $30, %ecx 59*697f6059SSimon Pilgrim; X64-NEXT: shll $27, %eax 60*697f6059SSimon Pilgrim; X64-NEXT: sarl $27, %eax 61f1cc7913SSimon Pilgrim; X64-NEXT: andl %ecx, %eax 62f1cc7913SSimon Pilgrim; X64-NEXT: retq 63f1cc7913SSimon Pilgrim %v0 = load i8, ptr %p0, align 1 64f1cc7913SSimon Pilgrim %v1 = load i8, ptr %p1, align 1 65f1cc7913SSimon Pilgrim %x0 = zext i8 %v0 to i32 66f1cc7913SSimon Pilgrim %x1 = zext i8 %v1 to i32 67f1cc7913SSimon Pilgrim %l0 = shl i32 %x0, 30 68f1cc7913SSimon Pilgrim %l1 = shl i32 %x1, 27 69f1cc7913SSimon Pilgrim %a0 = ashr exact i32 %l0, 30 70f1cc7913SSimon Pilgrim %a1 = ashr exact i32 %l1, 27 71f1cc7913SSimon Pilgrim %and = and i32 %a0, %a1 72f1cc7913SSimon Pilgrim ret i32 %and 73f1cc7913SSimon Pilgrim} 74