17f827ebdSSanjay Patel; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 27f827ebdSSanjay Patel; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s 37f827ebdSSanjay Patel 47f827ebdSSanjay Pateldefine i64 @muladd_demand(i64 %x, i64 %y) { 57f827ebdSSanjay Patel; CHECK-LABEL: muladd_demand: 67f827ebdSSanjay Patel; CHECK: # %bb.0: 7*21d7c3bcSSanjay Patel; CHECK-NEXT: movq %rsi, %rax 8*21d7c3bcSSanjay Patel; CHECK-NEXT: shll $6, %edi 9*21d7c3bcSSanjay Patel; CHECK-NEXT: subl %edi, %eax 107f827ebdSSanjay Patel; CHECK-NEXT: shlq $47, %rax 117f827ebdSSanjay Patel; CHECK-NEXT: retq 127f827ebdSSanjay Patel %m = mul i64 %x, 131008 ; 0x0001ffc0 137f827ebdSSanjay Patel %a = add i64 %m, %y 147f827ebdSSanjay Patel %r = shl i64 %a, 47 157f827ebdSSanjay Patel ret i64 %r 167f827ebdSSanjay Patel} 177f827ebdSSanjay Patel 187f827ebdSSanjay Pateldefine <2 x i64> @muladd_demand_commute(<2 x i64> %x, <2 x i64> %y) { 197f827ebdSSanjay Patel; CHECK-LABEL: muladd_demand_commute: 207f827ebdSSanjay Patel; CHECK: # %bb.0: 21*21d7c3bcSSanjay Patel; CHECK-NEXT: psllq $6, %xmm0 22*21d7c3bcSSanjay Patel; CHECK-NEXT: psubq %xmm0, %xmm1 23*21d7c3bcSSanjay Patel; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 24*21d7c3bcSSanjay Patel; CHECK-NEXT: movdqa %xmm1, %xmm0 257f827ebdSSanjay Patel; CHECK-NEXT: retq 267f827ebdSSanjay Patel %m = mul <2 x i64> %x, <i64 131008, i64 131008> 277f827ebdSSanjay Patel %a = add <2 x i64> %y, %m 287f827ebdSSanjay Patel %r = and <2 x i64> %a, <i64 131071, i64 131071> 297f827ebdSSanjay Patel ret <2 x i64> %r 307f827ebdSSanjay Patel} 31