1f318d1e2SSimon Moll; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2*5240e0b8SFangrui Song; RUN: llc < %s -O0 --mtriple=ve -mattr=+vpu | FileCheck %s 3f318d1e2SSimon Moll 4f318d1e2SSimon Molldeclare i64 @llvm.vector.reduce.and.v256i64(<256 x i64>) 5f318d1e2SSimon Moll 6f318d1e2SSimon Molldefine fastcc i64 @vec_reduce_and_v256i64(<256 x i64> %v) { 7f318d1e2SSimon Moll; CHECK-LABEL: vec_reduce_and_v256i64: 8f318d1e2SSimon Moll; CHECK: # %bb.0: 9f318d1e2SSimon Moll; CHECK-NEXT: lea %s0, 256 10f318d1e2SSimon Moll; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 11f318d1e2SSimon Moll; CHECK-NEXT: lvl %s0 12f318d1e2SSimon Moll; CHECK-NEXT: vrand %v0, %v0 13f318d1e2SSimon Moll; CHECK-NEXT: lvs %s0, %v0(0) 14f318d1e2SSimon Moll; CHECK-NEXT: b.l.t (, %s10) 15f318d1e2SSimon Moll %r = call i64 @llvm.vector.reduce.and.v256i64( <256 x i64> %v) 16f318d1e2SSimon Moll ret i64 %r 17f318d1e2SSimon Moll} 18f318d1e2SSimon Moll 19f318d1e2SSimon Molldeclare i32 @llvm.vector.reduce.and.v256i32(<256 x i32>) 20f318d1e2SSimon Moll 21f318d1e2SSimon Molldefine fastcc i32 @vec_reduce_and_v256i32(<256 x i32> %v) { 22f318d1e2SSimon Moll; CHECK-LABEL: vec_reduce_and_v256i32: 23f318d1e2SSimon Moll; CHECK: # %bb.0: 24f318d1e2SSimon Moll; CHECK-NEXT: lea %s0, 256 25f318d1e2SSimon Moll; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 26f318d1e2SSimon Moll; CHECK-NEXT: lvl %s0 27f318d1e2SSimon Moll; CHECK-NEXT: vrand %v0, %v0 28f318d1e2SSimon Moll; CHECK-NEXT: lvs %s0, %v0(0) 29f318d1e2SSimon Moll; CHECK-NEXT: or %s1, 0, %s0 30f318d1e2SSimon Moll; CHECK-NEXT: # implicit-def: $sx0 31f318d1e2SSimon Moll; CHECK-NEXT: or %s0, 0, %s1 32f318d1e2SSimon Moll; CHECK-NEXT: b.l.t (, %s10) 33f318d1e2SSimon Moll %r = call i32 @llvm.vector.reduce.and.v256i32( <256 x i32> %v) 34f318d1e2SSimon Moll ret i32 %r 35f318d1e2SSimon Moll} 36