xref: /llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/wls-search-pred.mir (revision 60442f0d442723a487528bdd8b48b24657a025e8)

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve %s -run-pass=arm-mve-vpt-opts --verify-machineinstrs -o - | FileCheck %s

--- |
  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
  target triple = "thumbv8.1m.main-none-unknown-eabihf"

  define void @test_memset_preheader(ptr %x, ptr %y, i32 %n) {
  entry:
    %cmp6 = icmp ne i32 %n, 0
    %0 = call { i32, i1 } @llvm.test.start.loop.iterations.i32(i32 %n)
    %1 = extractvalue { i32, i1 } %0, 1
    %2 = extractvalue { i32, i1 } %0, 0
    br i1 %1, label %prehead, label %for.cond.cleanup

  prehead:                                          ; preds = %entry
    call void @llvm.memset.p0.i32(ptr align 1 %x, i8 0, i32 %n, i1 false)
    br label %for.body

  for.body:                                         ; preds = %for.body, %prehead
    %x.addr.08 = phi ptr [ %add.ptr, %for.body ], [ %x, %prehead ]
    %y.addr.07 = phi ptr [ %add.ptr1, %for.body ], [ %y, %prehead ]
    %3 = phi i32 [ %2, %prehead ], [ %4, %for.body ]
    %add.ptr = getelementptr inbounds i8, ptr %x.addr.08, i32 1
    %add.ptr1 = getelementptr inbounds i8, ptr %y.addr.07, i32 1
    %l = load i8, ptr %x.addr.08, align 1
    store i8 %l, ptr %y.addr.07, align 1
    %4 = call i32 @llvm.loop.decrement.reg.i32(i32 %3, i32 1)
    %5 = icmp ne i32 %4, 0
    br i1 %5, label %for.body, label %for.cond.cleanup

  for.cond.cleanup:                                 ; preds = %for.body, %entry
    ret void
  }

  declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg)
  declare { i32, i1 } @llvm.test.start.loop.iterations.i32(i32)
  declare i32 @llvm.loop.decrement.reg.i32(i32, i32)

...
---
name:            test_memset_preheader
tracksRegLiveness: true
liveins:
  - { reg: '$r0', virtual-reg: '%7' }
  - { reg: '$r1', virtual-reg: '%8' }
  - { reg: '$r2', virtual-reg: '%9' }
body:             |
  ; CHECK-LABEL: name: test_memset_preheader
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.1(0x40000000), %bb.5(0x40000000)
  ; CHECK:   liveins: $r0, $r1, $r2
  ; CHECK:   [[COPY:%[0-9]+]]:rgpr = COPY $r2
  ; CHECK:   [[COPY1:%[0-9]+]]:gpr = COPY $r1
  ; CHECK:   [[COPY2:%[0-9]+]]:rgpr = COPY $r0
  ; CHECK:   t2CMPri [[COPY]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   t2Bcc %bb.5, 0 /* CC::eq */, $cpsr
  ; CHECK:   t2B %bb.1, 14 /* CC::al */, $noreg
  ; CHECK: bb.1.prehead:
  ; CHECK:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK:   [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF
  ; CHECK:   [[MVE_VMOVimmi32_:%[0-9]+]]:mqpr = MVE_VMOVimmi32 0, 0, $noreg, $noreg, [[DEF]]
  ; CHECK:   [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   [[t2BICri:%[0-9]+]]:rgpr = t2BICri killed [[t2ADDri]], 16, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   [[t2LSRri:%[0-9]+]]:gprlr = t2LSRri killed [[t2BICri]], 4, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   [[t2WhileLoopStartTP:%[0-9]+]]:gprlr = t2WhileLoopStartTP killed [[t2LSRri]], [[COPY]], %bb.3, implicit-def $cpsr
  ; CHECK: bb.2:
  ; CHECK:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
  ; CHECK:   [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.1, %11, %bb.2
  ; CHECK:   [[PHI1:%[0-9]+]]:gprlr = PHI [[t2WhileLoopStartTP]], %bb.1, %13, %bb.2
  ; CHECK:   [[PHI2:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.1, %15, %bb.2
  ; CHECK:   [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI2]], 0, $noreg, $noreg
  ; CHECK:   [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 16, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[MVE_VMOVimmi32_]], [[PHI]], 16, 1, [[MVE_VCTP8_]], [[PHI1]]
  ; CHECK:   [[t2LoopEndDec:%[0-9]+]]:gprlr = t2LoopEndDec [[PHI1]], %bb.2, implicit-def $cpsr
  ; CHECK:   t2B %bb.3, 14 /* CC::al */, $noreg
  ; CHECK: bb.3.prehead:
  ; CHECK:   successors: %bb.4(0x80000000)
  ; CHECK:   [[t2DoLoopStart:%[0-9]+]]:gprlr = t2DoLoopStart [[COPY]]
  ; CHECK:   t2B %bb.4, 14 /* CC::al */, $noreg
  ; CHECK: bb.4.for.body:
  ; CHECK:   successors: %bb.4(0x7c000000), %bb.5(0x04000000)
  ; CHECK:   [[PHI3:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.3, %19, %bb.4
  ; CHECK:   [[PHI4:%[0-9]+]]:gpr = PHI [[COPY1]], %bb.3, %21, %bb.4
  ; CHECK:   [[PHI5:%[0-9]+]]:gprlr = PHI [[t2DoLoopStart]], %bb.3, %26, %bb.4
  ; CHECK:   [[t2LDRB_POST:%[0-9]+]]:rgpr, [[t2LDRB_POST1:%[0-9]+]]:gpr = t2LDRB_POST [[PHI3]], 1, 14 /* CC::al */, $noreg :: (load (s8) from %ir.x.addr.08)
  ; CHECK:   early-clobber %25:gprnopc = t2STRB_POST killed [[t2LDRB_POST]], [[PHI4]], 1, 14 /* CC::al */, $noreg :: (store (s8) into %ir.y.addr.07)
  ; CHECK:   [[COPY3:%[0-9]+]]:gpr = COPY %25
  ; CHECK:   [[t2LoopEndDec1:%[0-9]+]]:gprlr = t2LoopEndDec [[PHI5]], %bb.4, implicit-def $cpsr
  ; CHECK:   t2B %bb.5, 14 /* CC::al */, $noreg
  ; CHECK: bb.5.for.cond.cleanup:
  ; CHECK:   tBX_RET 14 /* CC::al */, $noreg
  bb.0.entry:
    successors: %bb.1(0x40000000), %bb.3(0x40000000)
    liveins: $r0, $r1, $r2

    %9:rgpr = COPY $r2
    %8:gpr = COPY $r1
    %7:rgpr = COPY $r0
    %10:gprlr = t2WhileLoopSetup %9
    t2WhileLoopStart %10, %bb.3, implicit-def dead $cpsr
    t2B %bb.1, 14 /* CC::al */, $noreg

  bb.1.prehead:
    successors: %bb.5(0x40000000), %bb.4(0x40000000)

    %12:mqpr = IMPLICIT_DEF
    %11:mqpr = MVE_VMOVimmi32 0, 0, $noreg, $noreg, %12
    %17:rgpr = t2ADDri %9, 15, 14 /* CC::al */, $noreg, $noreg
    %18:rgpr = t2BICri killed %17, 16, 14 /* CC::al */, $noreg, $noreg
    %19:gprlr = t2LSRri killed %18, 4, 14 /* CC::al */, $noreg, $noreg
    %20:gprlr = t2WhileLoopSetup killed %19
    t2WhileLoopStart %20, %bb.5, implicit-def $cpsr

  bb.4:
    successors: %bb.4(0x40000000), %bb.5(0x40000000)

    %21:rgpr = PHI %7, %bb.1, %22, %bb.4
    %23:gprlr = PHI %20, %bb.1, %24, %bb.4
    %25:rgpr = PHI %9, %bb.1, %26, %bb.4
    %27:vccr = MVE_VCTP8 %25, 0, $noreg, $noreg
    %26:rgpr = t2SUBri %25, 16, 14 /* CC::al */, $noreg, $noreg
    %22:rgpr = MVE_VSTRBU8_post %11, %21, 16, 1, %27, $noreg
    %24:gprlr = t2LoopDec %23, 1
    t2LoopEnd %24, %bb.4, implicit-def $cpsr
    t2B %bb.5, 14 /* CC::al */, $noreg

  bb.5.prehead:
    successors: %bb.2(0x80000000)

    %0:gpr = COPY %10
    t2B %bb.2, 14 /* CC::al */, $noreg

  bb.2.for.body:
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)

    %1:gpr = PHI %7, %bb.5, %4, %bb.2
    %2:gpr = PHI %8, %bb.5, %5, %bb.2
    %3:gprlr = PHI %0, %bb.5, %6, %bb.2
    %13:rgpr, %4:gpr = t2LDRB_POST %1, 1, 14 /* CC::al */, $noreg :: (load (s8) from %ir.x.addr.08)
    early-clobber %14:gprnopc = t2STRB_POST killed %13, %2, 1, 14 /* CC::al */, $noreg :: (store (s8) into %ir.y.addr.07)
    %15:gprlr = t2LoopDec %3, 1
    %5:gpr = COPY %14
    %6:gpr = COPY %15
    t2LoopEnd %15, %bb.2, implicit-def dead $cpsr
    t2B %bb.3, 14 /* CC::al */, $noreg

  bb.3.for.cond.cleanup:
    tBX_RET 14 /* CC::al */, $noreg

...