1*ce4c1095SUlrich Weigand; Test vector logical shift right with vector shift amount. 2*ce4c1095SUlrich Weigand; 3*ce4c1095SUlrich Weigand; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 4*ce4c1095SUlrich Weigand 5*ce4c1095SUlrich Weigand; Test a v16i8 shift. 6*ce4c1095SUlrich Weiganddefine <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { 7*ce4c1095SUlrich Weigand; CHECK-LABEL: f1: 8*ce4c1095SUlrich Weigand; CHECK: vesrlvb %v24, %v26, %v28 9*ce4c1095SUlrich Weigand; CHECK: br %r14 10*ce4c1095SUlrich Weigand %ret = lshr <16 x i8> %val1, %val2 11*ce4c1095SUlrich Weigand ret <16 x i8> %ret 12*ce4c1095SUlrich Weigand} 13*ce4c1095SUlrich Weigand 14*ce4c1095SUlrich Weigand; Test a v8i16 shift. 15*ce4c1095SUlrich Weiganddefine <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { 16*ce4c1095SUlrich Weigand; CHECK-LABEL: f2: 17*ce4c1095SUlrich Weigand; CHECK: vesrlvh %v24, %v26, %v28 18*ce4c1095SUlrich Weigand; CHECK: br %r14 19*ce4c1095SUlrich Weigand %ret = lshr <8 x i16> %val1, %val2 20*ce4c1095SUlrich Weigand ret <8 x i16> %ret 21*ce4c1095SUlrich Weigand} 22*ce4c1095SUlrich Weigand 23*ce4c1095SUlrich Weigand; Test a v4i32 shift. 24*ce4c1095SUlrich Weiganddefine <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { 25*ce4c1095SUlrich Weigand; CHECK-LABEL: f3: 26*ce4c1095SUlrich Weigand; CHECK: vesrlvf %v24, %v26, %v28 27*ce4c1095SUlrich Weigand; CHECK: br %r14 28*ce4c1095SUlrich Weigand %ret = lshr <4 x i32> %val1, %val2 29*ce4c1095SUlrich Weigand ret <4 x i32> %ret 30*ce4c1095SUlrich Weigand} 31*ce4c1095SUlrich Weigand 32*ce4c1095SUlrich Weigand; Test a v2i64 shift. 33*ce4c1095SUlrich Weiganddefine <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { 34*ce4c1095SUlrich Weigand; CHECK-LABEL: f4: 35*ce4c1095SUlrich Weigand; CHECK: vesrlvg %v24, %v26, %v28 36*ce4c1095SUlrich Weigand; CHECK: br %r14 37*ce4c1095SUlrich Weigand %ret = lshr <2 x i64> %val1, %val2 38*ce4c1095SUlrich Weigand ret <2 x i64> %ret 39*ce4c1095SUlrich Weigand} 40