1ce4c1095SUlrich Weigand; Test vector multiplication. 2ce4c1095SUlrich Weigand; 3ce4c1095SUlrich Weigand; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 4ce4c1095SUlrich Weigand 5ce4c1095SUlrich Weigand; Test a v16i8 multiplication. 6ce4c1095SUlrich Weiganddefine <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { 7ce4c1095SUlrich Weigand; CHECK-LABEL: f1: 8ce4c1095SUlrich Weigand; CHECK: vmlb %v24, %v26, %v28 9ce4c1095SUlrich Weigand; CHECK: br %r14 10ce4c1095SUlrich Weigand %ret = mul <16 x i8> %val1, %val2 11ce4c1095SUlrich Weigand ret <16 x i8> %ret 12ce4c1095SUlrich Weigand} 13ce4c1095SUlrich Weigand 14ce4c1095SUlrich Weigand; Test a v8i16 multiplication. 15ce4c1095SUlrich Weiganddefine <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { 16ce4c1095SUlrich Weigand; CHECK-LABEL: f2: 17ce4c1095SUlrich Weigand; CHECK: vmlhw %v24, %v26, %v28 18ce4c1095SUlrich Weigand; CHECK: br %r14 19ce4c1095SUlrich Weigand %ret = mul <8 x i16> %val1, %val2 20ce4c1095SUlrich Weigand ret <8 x i16> %ret 21ce4c1095SUlrich Weigand} 22ce4c1095SUlrich Weigand 23ce4c1095SUlrich Weigand; Test a v4i32 multiplication. 24ce4c1095SUlrich Weiganddefine <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { 25ce4c1095SUlrich Weigand; CHECK-LABEL: f3: 26ce4c1095SUlrich Weigand; CHECK: vmlf %v24, %v26, %v28 27ce4c1095SUlrich Weigand; CHECK: br %r14 28ce4c1095SUlrich Weigand %ret = mul <4 x i32> %val1, %val2 29ce4c1095SUlrich Weigand ret <4 x i32> %ret 30ce4c1095SUlrich Weigand} 31ce4c1095SUlrich Weigand 32ce4c1095SUlrich Weigand; Test a v2i64 multiplication. There's no vector equivalent. 33ce4c1095SUlrich Weiganddefine <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { 34ce4c1095SUlrich Weigand; CHECK-LABEL: f4: 35ce4c1095SUlrich Weigand; CHECK-NOT: vmlg 36ce4c1095SUlrich Weigand; CHECK: br %r14 37ce4c1095SUlrich Weigand %ret = mul <2 x i64> %val1, %val2 38ce4c1095SUlrich Weigand ret <2 x i64> %ret 39ce4c1095SUlrich Weigand} 40cd808237SUlrich Weigand 41cd808237SUlrich Weigand; Test a v2f64 multiplication. 42cd808237SUlrich Weiganddefine <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1, 43cd808237SUlrich Weigand <2 x double> %val2) { 44cd808237SUlrich Weigand; CHECK-LABEL: f5: 45cd808237SUlrich Weigand; CHECK: vfmdb %v24, %v26, %v28 46cd808237SUlrich Weigand; CHECK: br %r14 47cd808237SUlrich Weigand %ret = fmul <2 x double> %val1, %val2 48cd808237SUlrich Weigand ret <2 x double> %ret 49cd808237SUlrich Weigand} 50*49506d78SUlrich Weigand 51*49506d78SUlrich Weigand; Test an f64 multiplication that uses vector registers. 52*49506d78SUlrich Weiganddefine double @f6(<2 x double> %val1, <2 x double> %val2) { 53*49506d78SUlrich Weigand; CHECK-LABEL: f6: 54*49506d78SUlrich Weigand; CHECK: wfmdb %f0, %v24, %v26 55*49506d78SUlrich Weigand; CHECK: br %r14 56*49506d78SUlrich Weigand %scalar1 = extractelement <2 x double> %val1, i32 0 57*49506d78SUlrich Weigand %scalar2 = extractelement <2 x double> %val2, i32 0 58*49506d78SUlrich Weigand %ret = fmul double %scalar1, %scalar2 59*49506d78SUlrich Weigand ret double %ret 60*49506d78SUlrich Weigand} 61