1ce4c1095SUlrich Weigand; Test vector register moves. 2ce4c1095SUlrich Weigand; 3ce4c1095SUlrich Weigand; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 4ce4c1095SUlrich Weigand 5ce4c1095SUlrich Weigand; Test v16i8 moves. 6ce4c1095SUlrich Weiganddefine <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) { 7ce4c1095SUlrich Weigand; CHECK-LABEL: f1: 8ce4c1095SUlrich Weigand; CHECK: vlr %v24, %v26 9ce4c1095SUlrich Weigand; CHECK: br %r14 10ce4c1095SUlrich Weigand ret <16 x i8> %val2 11ce4c1095SUlrich Weigand} 12ce4c1095SUlrich Weigand 13ce4c1095SUlrich Weigand; Test v8i16 moves. 14ce4c1095SUlrich Weiganddefine <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) { 15ce4c1095SUlrich Weigand; CHECK-LABEL: f2: 16ce4c1095SUlrich Weigand; CHECK: vlr %v24, %v26 17ce4c1095SUlrich Weigand; CHECK: br %r14 18ce4c1095SUlrich Weigand ret <8 x i16> %val2 19ce4c1095SUlrich Weigand} 20ce4c1095SUlrich Weigand 21ce4c1095SUlrich Weigand; Test v4i32 moves. 22ce4c1095SUlrich Weiganddefine <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) { 23ce4c1095SUlrich Weigand; CHECK-LABEL: f3: 24ce4c1095SUlrich Weigand; CHECK: vlr %v24, %v26 25ce4c1095SUlrich Weigand; CHECK: br %r14 26ce4c1095SUlrich Weigand ret <4 x i32> %val2 27ce4c1095SUlrich Weigand} 28ce4c1095SUlrich Weigand 29ce4c1095SUlrich Weigand; Test v2i64 moves. 30ce4c1095SUlrich Weiganddefine <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) { 31ce4c1095SUlrich Weigand; CHECK-LABEL: f4: 32ce4c1095SUlrich Weigand; CHECK: vlr %v24, %v26 33ce4c1095SUlrich Weigand; CHECK: br %r14 34ce4c1095SUlrich Weigand ret <2 x i64> %val2 35ce4c1095SUlrich Weigand} 36cd808237SUlrich Weigand 3780b3af7aSUlrich Weigand; Test v4f32 moves. 3880b3af7aSUlrich Weiganddefine <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) { 3980b3af7aSUlrich Weigand; CHECK-LABEL: f5: 4080b3af7aSUlrich Weigand; CHECK: vlr %v24, %v26 4180b3af7aSUlrich Weigand; CHECK: br %r14 4280b3af7aSUlrich Weigand ret <4 x float> %val2 4380b3af7aSUlrich Weigand} 4480b3af7aSUlrich Weigand 45cd808237SUlrich Weigand; Test v2f64 moves. 46cd808237SUlrich Weiganddefine <2 x double> @f6(<2 x double> %val1, <2 x double> %val2) { 47cd808237SUlrich Weigand; CHECK-LABEL: f6: 48cd808237SUlrich Weigand; CHECK: vlr %v24, %v26 49cd808237SUlrich Weigand; CHECK: br %r14 50cd808237SUlrich Weigand ret <2 x double> %val2 51cd808237SUlrich Weigand} 52*cd2a1b53SUlrich Weigand 53*cd2a1b53SUlrich Weigand; Test v2i8 moves. 54*cd2a1b53SUlrich Weiganddefine <2 x i8> @f7(<2 x i8> %val1, <2 x i8> %val2) { 55*cd2a1b53SUlrich Weigand; CHECK-LABEL: f7: 56*cd2a1b53SUlrich Weigand; CHECK: vlr %v24, %v26 57*cd2a1b53SUlrich Weigand; CHECK: br %r14 58*cd2a1b53SUlrich Weigand ret <2 x i8> %val2 59*cd2a1b53SUlrich Weigand} 60*cd2a1b53SUlrich Weigand 61*cd2a1b53SUlrich Weigand; Test v4i8 moves. 62*cd2a1b53SUlrich Weiganddefine <4 x i8> @f8(<4 x i8> %val1, <4 x i8> %val2) { 63*cd2a1b53SUlrich Weigand; CHECK-LABEL: f8: 64*cd2a1b53SUlrich Weigand; CHECK: vlr %v24, %v26 65*cd2a1b53SUlrich Weigand; CHECK: br %r14 66*cd2a1b53SUlrich Weigand ret <4 x i8> %val2 67*cd2a1b53SUlrich Weigand} 68*cd2a1b53SUlrich Weigand 69*cd2a1b53SUlrich Weigand; Test v8i8 moves. 70*cd2a1b53SUlrich Weiganddefine <8 x i8> @f9(<8 x i8> %val1, <8 x i8> %val2) { 71*cd2a1b53SUlrich Weigand; CHECK-LABEL: f9: 72*cd2a1b53SUlrich Weigand; CHECK: vlr %v24, %v26 73*cd2a1b53SUlrich Weigand; CHECK: br %r14 74*cd2a1b53SUlrich Weigand ret <8 x i8> %val2 75*cd2a1b53SUlrich Weigand} 76*cd2a1b53SUlrich Weigand 77*cd2a1b53SUlrich Weigand; Test v2i16 moves. 78*cd2a1b53SUlrich Weiganddefine <2 x i16> @f10(<2 x i16> %val1, <2 x i16> %val2) { 79*cd2a1b53SUlrich Weigand; CHECK-LABEL: f10: 80*cd2a1b53SUlrich Weigand; CHECK: vlr %v24, %v26 81*cd2a1b53SUlrich Weigand; CHECK: br %r14 82*cd2a1b53SUlrich Weigand ret <2 x i16> %val2 83*cd2a1b53SUlrich Weigand} 84*cd2a1b53SUlrich Weigand 85*cd2a1b53SUlrich Weigand; Test v4i16 moves. 86*cd2a1b53SUlrich Weiganddefine <4 x i16> @f11(<4 x i16> %val1, <4 x i16> %val2) { 87*cd2a1b53SUlrich Weigand; CHECK-LABEL: f11: 88*cd2a1b53SUlrich Weigand; CHECK: vlr %v24, %v26 89*cd2a1b53SUlrich Weigand; CHECK: br %r14 90*cd2a1b53SUlrich Weigand ret <4 x i16> %val2 91*cd2a1b53SUlrich Weigand} 92*cd2a1b53SUlrich Weigand 93*cd2a1b53SUlrich Weigand; Test v2i32 moves. 94*cd2a1b53SUlrich Weiganddefine <2 x i32> @f12(<2 x i32> %val1, <2 x i32> %val2) { 95*cd2a1b53SUlrich Weigand; CHECK-LABEL: f12: 96*cd2a1b53SUlrich Weigand; CHECK: vlr %v24, %v26 97*cd2a1b53SUlrich Weigand; CHECK: br %r14 98*cd2a1b53SUlrich Weigand ret <2 x i32> %val2 99*cd2a1b53SUlrich Weigand} 100*cd2a1b53SUlrich Weigand 101*cd2a1b53SUlrich Weigand; Test v2f32 moves. 102*cd2a1b53SUlrich Weiganddefine <2 x float> @f13(<2 x float> %val1, <2 x float> %val2) { 103*cd2a1b53SUlrich Weigand; CHECK-LABEL: f13: 104*cd2a1b53SUlrich Weigand; CHECK: vlr %v24, %v26 105*cd2a1b53SUlrich Weigand; CHECK: br %r14 106*cd2a1b53SUlrich Weigand ret <2 x float> %val2 107*cd2a1b53SUlrich Weigand} 108