1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfh \ 3; RUN: -verify-machineinstrs -target-abi ilp32f -disable-strictnode-mutation \ 4; RUN: | FileCheck -check-prefix=RV32IZFH %s 5; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \ 6; RUN: -verify-machineinstrs -target-abi lp64f -disable-strictnode-mutation \ 7; RUN: | FileCheck -check-prefix=RV64IZFH %s 8; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \ 9; RUN: -mattr=+zfh -verify-machineinstrs -target-abi ilp32d \ 10; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32IZFH %s 11; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \ 12; RUN: -mattr=+zfh -verify-machineinstrs -target-abi lp64d \ 13; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64IZFH %s 14; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zhinx \ 15; RUN: -verify-machineinstrs -target-abi ilp32 -disable-strictnode-mutation \ 16; RUN: | FileCheck -check-prefix=RV32IZHINX %s 17; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zhinx \ 18; RUN: -verify-machineinstrs -target-abi lp64 -disable-strictnode-mutation \ 19; RUN: | FileCheck -check-prefix=RV64IZHINX %s 20; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \ 21; RUN: -mattr=+zhinx -verify-machineinstrs -target-abi ilp32 | \ 22; RUN: FileCheck -check-prefix=RV32IZDINXZHINX %s 23; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \ 24; RUN: -mattr=+zhinx -verify-machineinstrs -target-abi lp64 | \ 25; RUN: FileCheck -check-prefix=RV64IZDINXZHINX %s 26 27declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata) 28 29define half @sqrt_f16(half %a) nounwind strictfp { 30; RV32IZFH-LABEL: sqrt_f16: 31; RV32IZFH: # %bb.0: 32; RV32IZFH-NEXT: fsqrt.h fa0, fa0 33; RV32IZFH-NEXT: ret 34; 35; RV64IZFH-LABEL: sqrt_f16: 36; RV64IZFH: # %bb.0: 37; RV64IZFH-NEXT: fsqrt.h fa0, fa0 38; RV64IZFH-NEXT: ret 39; 40; RV32IZHINX-LABEL: sqrt_f16: 41; RV32IZHINX: # %bb.0: 42; RV32IZHINX-NEXT: fsqrt.h a0, a0 43; RV32IZHINX-NEXT: ret 44; 45; RV64IZHINX-LABEL: sqrt_f16: 46; RV64IZHINX: # %bb.0: 47; RV64IZHINX-NEXT: fsqrt.h a0, a0 48; RV64IZHINX-NEXT: ret 49; 50; RV32IZDINXZHINX-LABEL: sqrt_f16: 51; RV32IZDINXZHINX: # %bb.0: 52; RV32IZDINXZHINX-NEXT: fsqrt.h a0, a0 53; RV32IZDINXZHINX-NEXT: ret 54; 55; RV64IZDINXZHINX-LABEL: sqrt_f16: 56; RV64IZDINXZHINX: # %bb.0: 57; RV64IZDINXZHINX-NEXT: fsqrt.h a0, a0 58; RV64IZDINXZHINX-NEXT: ret 59 %1 = call half @llvm.experimental.constrained.sqrt.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp 60 ret half %1 61} 62 63declare half @llvm.experimental.constrained.floor.f16(half, metadata) 64 65define half @floor_f16(half %a) nounwind strictfp { 66; RV32IZFH-LABEL: floor_f16: 67; RV32IZFH: # %bb.0: 68; RV32IZFH-NEXT: addi sp, sp, -16 69; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 70; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 71; RV32IZFH-NEXT: call floorf 72; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 73; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 74; RV32IZFH-NEXT: addi sp, sp, 16 75; RV32IZFH-NEXT: ret 76; 77; RV64IZFH-LABEL: floor_f16: 78; RV64IZFH: # %bb.0: 79; RV64IZFH-NEXT: addi sp, sp, -16 80; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 81; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 82; RV64IZFH-NEXT: call floorf 83; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 84; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 85; RV64IZFH-NEXT: addi sp, sp, 16 86; RV64IZFH-NEXT: ret 87; 88; RV32IZHINX-LABEL: floor_f16: 89; RV32IZHINX: # %bb.0: 90; RV32IZHINX-NEXT: addi sp, sp, -16 91; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 92; RV32IZHINX-NEXT: fcvt.s.h a0, a0 93; RV32IZHINX-NEXT: call floorf 94; RV32IZHINX-NEXT: fcvt.h.s a0, a0 95; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 96; RV32IZHINX-NEXT: addi sp, sp, 16 97; RV32IZHINX-NEXT: ret 98; 99; RV64IZHINX-LABEL: floor_f16: 100; RV64IZHINX: # %bb.0: 101; RV64IZHINX-NEXT: addi sp, sp, -16 102; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 103; RV64IZHINX-NEXT: fcvt.s.h a0, a0 104; RV64IZHINX-NEXT: call floorf 105; RV64IZHINX-NEXT: fcvt.h.s a0, a0 106; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 107; RV64IZHINX-NEXT: addi sp, sp, 16 108; RV64IZHINX-NEXT: ret 109; 110; RV32IZDINXZHINX-LABEL: floor_f16: 111; RV32IZDINXZHINX: # %bb.0: 112; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 113; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 114; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 115; RV32IZDINXZHINX-NEXT: call floorf 116; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0 117; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 118; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 119; RV32IZDINXZHINX-NEXT: ret 120; 121; RV64IZDINXZHINX-LABEL: floor_f16: 122; RV64IZDINXZHINX: # %bb.0: 123; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 124; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 125; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 126; RV64IZDINXZHINX-NEXT: call floorf 127; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0 128; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 129; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 130; RV64IZDINXZHINX-NEXT: ret 131 %1 = call half @llvm.experimental.constrained.floor.f16(half %a, metadata !"fpexcept.strict") strictfp 132 ret half %1 133} 134 135declare half @llvm.experimental.constrained.ceil.f16(half, metadata) 136 137define half @ceil_f16(half %a) nounwind strictfp { 138; RV32IZFH-LABEL: ceil_f16: 139; RV32IZFH: # %bb.0: 140; RV32IZFH-NEXT: addi sp, sp, -16 141; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 142; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 143; RV32IZFH-NEXT: call ceilf 144; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 145; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 146; RV32IZFH-NEXT: addi sp, sp, 16 147; RV32IZFH-NEXT: ret 148; 149; RV64IZFH-LABEL: ceil_f16: 150; RV64IZFH: # %bb.0: 151; RV64IZFH-NEXT: addi sp, sp, -16 152; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 153; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 154; RV64IZFH-NEXT: call ceilf 155; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 156; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 157; RV64IZFH-NEXT: addi sp, sp, 16 158; RV64IZFH-NEXT: ret 159; 160; RV32IZHINX-LABEL: ceil_f16: 161; RV32IZHINX: # %bb.0: 162; RV32IZHINX-NEXT: addi sp, sp, -16 163; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 164; RV32IZHINX-NEXT: fcvt.s.h a0, a0 165; RV32IZHINX-NEXT: call ceilf 166; RV32IZHINX-NEXT: fcvt.h.s a0, a0 167; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 168; RV32IZHINX-NEXT: addi sp, sp, 16 169; RV32IZHINX-NEXT: ret 170; 171; RV64IZHINX-LABEL: ceil_f16: 172; RV64IZHINX: # %bb.0: 173; RV64IZHINX-NEXT: addi sp, sp, -16 174; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 175; RV64IZHINX-NEXT: fcvt.s.h a0, a0 176; RV64IZHINX-NEXT: call ceilf 177; RV64IZHINX-NEXT: fcvt.h.s a0, a0 178; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 179; RV64IZHINX-NEXT: addi sp, sp, 16 180; RV64IZHINX-NEXT: ret 181; 182; RV32IZDINXZHINX-LABEL: ceil_f16: 183; RV32IZDINXZHINX: # %bb.0: 184; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 185; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 186; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 187; RV32IZDINXZHINX-NEXT: call ceilf 188; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0 189; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 190; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 191; RV32IZDINXZHINX-NEXT: ret 192; 193; RV64IZDINXZHINX-LABEL: ceil_f16: 194; RV64IZDINXZHINX: # %bb.0: 195; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 196; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 197; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 198; RV64IZDINXZHINX-NEXT: call ceilf 199; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0 200; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 201; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 202; RV64IZDINXZHINX-NEXT: ret 203 %1 = call half @llvm.experimental.constrained.ceil.f16(half %a, metadata !"fpexcept.strict") strictfp 204 ret half %1 205} 206 207declare half @llvm.experimental.constrained.trunc.f16(half, metadata) 208 209define half @trunc_f16(half %a) nounwind strictfp { 210; RV32IZFH-LABEL: trunc_f16: 211; RV32IZFH: # %bb.0: 212; RV32IZFH-NEXT: addi sp, sp, -16 213; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 214; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 215; RV32IZFH-NEXT: call truncf 216; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 217; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 218; RV32IZFH-NEXT: addi sp, sp, 16 219; RV32IZFH-NEXT: ret 220; 221; RV64IZFH-LABEL: trunc_f16: 222; RV64IZFH: # %bb.0: 223; RV64IZFH-NEXT: addi sp, sp, -16 224; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 225; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 226; RV64IZFH-NEXT: call truncf 227; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 228; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 229; RV64IZFH-NEXT: addi sp, sp, 16 230; RV64IZFH-NEXT: ret 231; 232; RV32IZHINX-LABEL: trunc_f16: 233; RV32IZHINX: # %bb.0: 234; RV32IZHINX-NEXT: addi sp, sp, -16 235; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 236; RV32IZHINX-NEXT: fcvt.s.h a0, a0 237; RV32IZHINX-NEXT: call truncf 238; RV32IZHINX-NEXT: fcvt.h.s a0, a0 239; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 240; RV32IZHINX-NEXT: addi sp, sp, 16 241; RV32IZHINX-NEXT: ret 242; 243; RV64IZHINX-LABEL: trunc_f16: 244; RV64IZHINX: # %bb.0: 245; RV64IZHINX-NEXT: addi sp, sp, -16 246; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 247; RV64IZHINX-NEXT: fcvt.s.h a0, a0 248; RV64IZHINX-NEXT: call truncf 249; RV64IZHINX-NEXT: fcvt.h.s a0, a0 250; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 251; RV64IZHINX-NEXT: addi sp, sp, 16 252; RV64IZHINX-NEXT: ret 253; 254; RV32IZDINXZHINX-LABEL: trunc_f16: 255; RV32IZDINXZHINX: # %bb.0: 256; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 257; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 258; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 259; RV32IZDINXZHINX-NEXT: call truncf 260; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0 261; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 262; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 263; RV32IZDINXZHINX-NEXT: ret 264; 265; RV64IZDINXZHINX-LABEL: trunc_f16: 266; RV64IZDINXZHINX: # %bb.0: 267; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 268; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 269; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 270; RV64IZDINXZHINX-NEXT: call truncf 271; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0 272; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 273; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 274; RV64IZDINXZHINX-NEXT: ret 275 %1 = call half @llvm.experimental.constrained.trunc.f16(half %a, metadata !"fpexcept.strict") strictfp 276 ret half %1 277} 278 279declare half @llvm.experimental.constrained.rint.f16(half, metadata, metadata) 280 281define half @rint_f16(half %a) nounwind strictfp { 282; RV32IZFH-LABEL: rint_f16: 283; RV32IZFH: # %bb.0: 284; RV32IZFH-NEXT: addi sp, sp, -16 285; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 286; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 287; RV32IZFH-NEXT: call rintf 288; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 289; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 290; RV32IZFH-NEXT: addi sp, sp, 16 291; RV32IZFH-NEXT: ret 292; 293; RV64IZFH-LABEL: rint_f16: 294; RV64IZFH: # %bb.0: 295; RV64IZFH-NEXT: addi sp, sp, -16 296; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 297; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 298; RV64IZFH-NEXT: call rintf 299; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 300; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 301; RV64IZFH-NEXT: addi sp, sp, 16 302; RV64IZFH-NEXT: ret 303; 304; RV32IZHINX-LABEL: rint_f16: 305; RV32IZHINX: # %bb.0: 306; RV32IZHINX-NEXT: addi sp, sp, -16 307; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 308; RV32IZHINX-NEXT: fcvt.s.h a0, a0 309; RV32IZHINX-NEXT: call rintf 310; RV32IZHINX-NEXT: fcvt.h.s a0, a0 311; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 312; RV32IZHINX-NEXT: addi sp, sp, 16 313; RV32IZHINX-NEXT: ret 314; 315; RV64IZHINX-LABEL: rint_f16: 316; RV64IZHINX: # %bb.0: 317; RV64IZHINX-NEXT: addi sp, sp, -16 318; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 319; RV64IZHINX-NEXT: fcvt.s.h a0, a0 320; RV64IZHINX-NEXT: call rintf 321; RV64IZHINX-NEXT: fcvt.h.s a0, a0 322; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 323; RV64IZHINX-NEXT: addi sp, sp, 16 324; RV64IZHINX-NEXT: ret 325; 326; RV32IZDINXZHINX-LABEL: rint_f16: 327; RV32IZDINXZHINX: # %bb.0: 328; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 329; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 330; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 331; RV32IZDINXZHINX-NEXT: call rintf 332; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0 333; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 334; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 335; RV32IZDINXZHINX-NEXT: ret 336; 337; RV64IZDINXZHINX-LABEL: rint_f16: 338; RV64IZDINXZHINX: # %bb.0: 339; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 340; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 341; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 342; RV64IZDINXZHINX-NEXT: call rintf 343; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0 344; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 345; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 346; RV64IZDINXZHINX-NEXT: ret 347 %1 = call half @llvm.experimental.constrained.rint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp 348 ret half %1 349} 350 351declare half @llvm.experimental.constrained.nearbyint.f16(half, metadata, metadata) 352 353define half @nearbyint_f16(half %a) nounwind strictfp { 354; RV32IZFH-LABEL: nearbyint_f16: 355; RV32IZFH: # %bb.0: 356; RV32IZFH-NEXT: addi sp, sp, -16 357; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 358; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 359; RV32IZFH-NEXT: call nearbyintf 360; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 361; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 362; RV32IZFH-NEXT: addi sp, sp, 16 363; RV32IZFH-NEXT: ret 364; 365; RV64IZFH-LABEL: nearbyint_f16: 366; RV64IZFH: # %bb.0: 367; RV64IZFH-NEXT: addi sp, sp, -16 368; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 369; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 370; RV64IZFH-NEXT: call nearbyintf 371; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 372; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 373; RV64IZFH-NEXT: addi sp, sp, 16 374; RV64IZFH-NEXT: ret 375; 376; RV32IZHINX-LABEL: nearbyint_f16: 377; RV32IZHINX: # %bb.0: 378; RV32IZHINX-NEXT: addi sp, sp, -16 379; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 380; RV32IZHINX-NEXT: fcvt.s.h a0, a0 381; RV32IZHINX-NEXT: call nearbyintf 382; RV32IZHINX-NEXT: fcvt.h.s a0, a0 383; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 384; RV32IZHINX-NEXT: addi sp, sp, 16 385; RV32IZHINX-NEXT: ret 386; 387; RV64IZHINX-LABEL: nearbyint_f16: 388; RV64IZHINX: # %bb.0: 389; RV64IZHINX-NEXT: addi sp, sp, -16 390; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 391; RV64IZHINX-NEXT: fcvt.s.h a0, a0 392; RV64IZHINX-NEXT: call nearbyintf 393; RV64IZHINX-NEXT: fcvt.h.s a0, a0 394; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 395; RV64IZHINX-NEXT: addi sp, sp, 16 396; RV64IZHINX-NEXT: ret 397; 398; RV32IZDINXZHINX-LABEL: nearbyint_f16: 399; RV32IZDINXZHINX: # %bb.0: 400; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 401; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 402; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 403; RV32IZDINXZHINX-NEXT: call nearbyintf 404; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0 405; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 406; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 407; RV32IZDINXZHINX-NEXT: ret 408; 409; RV64IZDINXZHINX-LABEL: nearbyint_f16: 410; RV64IZDINXZHINX: # %bb.0: 411; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 412; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 413; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 414; RV64IZDINXZHINX-NEXT: call nearbyintf 415; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0 416; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 417; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 418; RV64IZDINXZHINX-NEXT: ret 419 %1 = call half @llvm.experimental.constrained.nearbyint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp 420 ret half %1 421} 422 423declare half @llvm.experimental.constrained.round.f16(half, metadata) 424 425define half @round_f16(half %a) nounwind strictfp { 426; RV32IZFH-LABEL: round_f16: 427; RV32IZFH: # %bb.0: 428; RV32IZFH-NEXT: addi sp, sp, -16 429; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 430; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 431; RV32IZFH-NEXT: call roundf 432; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 433; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 434; RV32IZFH-NEXT: addi sp, sp, 16 435; RV32IZFH-NEXT: ret 436; 437; RV64IZFH-LABEL: round_f16: 438; RV64IZFH: # %bb.0: 439; RV64IZFH-NEXT: addi sp, sp, -16 440; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 441; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 442; RV64IZFH-NEXT: call roundf 443; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 444; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 445; RV64IZFH-NEXT: addi sp, sp, 16 446; RV64IZFH-NEXT: ret 447; 448; RV32IZHINX-LABEL: round_f16: 449; RV32IZHINX: # %bb.0: 450; RV32IZHINX-NEXT: addi sp, sp, -16 451; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 452; RV32IZHINX-NEXT: fcvt.s.h a0, a0 453; RV32IZHINX-NEXT: call roundf 454; RV32IZHINX-NEXT: fcvt.h.s a0, a0 455; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 456; RV32IZHINX-NEXT: addi sp, sp, 16 457; RV32IZHINX-NEXT: ret 458; 459; RV64IZHINX-LABEL: round_f16: 460; RV64IZHINX: # %bb.0: 461; RV64IZHINX-NEXT: addi sp, sp, -16 462; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 463; RV64IZHINX-NEXT: fcvt.s.h a0, a0 464; RV64IZHINX-NEXT: call roundf 465; RV64IZHINX-NEXT: fcvt.h.s a0, a0 466; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 467; RV64IZHINX-NEXT: addi sp, sp, 16 468; RV64IZHINX-NEXT: ret 469; 470; RV32IZDINXZHINX-LABEL: round_f16: 471; RV32IZDINXZHINX: # %bb.0: 472; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 473; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 474; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 475; RV32IZDINXZHINX-NEXT: call roundf 476; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0 477; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 478; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 479; RV32IZDINXZHINX-NEXT: ret 480; 481; RV64IZDINXZHINX-LABEL: round_f16: 482; RV64IZDINXZHINX: # %bb.0: 483; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 484; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 485; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 486; RV64IZDINXZHINX-NEXT: call roundf 487; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0 488; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 489; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 490; RV64IZDINXZHINX-NEXT: ret 491 %1 = call half @llvm.experimental.constrained.round.f16(half %a, metadata !"fpexcept.strict") strictfp 492 ret half %1 493} 494 495declare half @llvm.experimental.constrained.roundeven.f16(half, metadata) 496 497define half @roundeven_f16(half %a) nounwind strictfp { 498; RV32IZFH-LABEL: roundeven_f16: 499; RV32IZFH: # %bb.0: 500; RV32IZFH-NEXT: addi sp, sp, -16 501; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 502; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 503; RV32IZFH-NEXT: call roundevenf 504; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 505; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 506; RV32IZFH-NEXT: addi sp, sp, 16 507; RV32IZFH-NEXT: ret 508; 509; RV64IZFH-LABEL: roundeven_f16: 510; RV64IZFH: # %bb.0: 511; RV64IZFH-NEXT: addi sp, sp, -16 512; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 513; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 514; RV64IZFH-NEXT: call roundevenf 515; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 516; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 517; RV64IZFH-NEXT: addi sp, sp, 16 518; RV64IZFH-NEXT: ret 519; 520; RV32IZHINX-LABEL: roundeven_f16: 521; RV32IZHINX: # %bb.0: 522; RV32IZHINX-NEXT: addi sp, sp, -16 523; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 524; RV32IZHINX-NEXT: fcvt.s.h a0, a0 525; RV32IZHINX-NEXT: call roundevenf 526; RV32IZHINX-NEXT: fcvt.h.s a0, a0 527; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 528; RV32IZHINX-NEXT: addi sp, sp, 16 529; RV32IZHINX-NEXT: ret 530; 531; RV64IZHINX-LABEL: roundeven_f16: 532; RV64IZHINX: # %bb.0: 533; RV64IZHINX-NEXT: addi sp, sp, -16 534; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 535; RV64IZHINX-NEXT: fcvt.s.h a0, a0 536; RV64IZHINX-NEXT: call roundevenf 537; RV64IZHINX-NEXT: fcvt.h.s a0, a0 538; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 539; RV64IZHINX-NEXT: addi sp, sp, 16 540; RV64IZHINX-NEXT: ret 541; 542; RV32IZDINXZHINX-LABEL: roundeven_f16: 543; RV32IZDINXZHINX: # %bb.0: 544; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 545; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 546; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 547; RV32IZDINXZHINX-NEXT: call roundevenf 548; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0 549; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 550; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 551; RV32IZDINXZHINX-NEXT: ret 552; 553; RV64IZDINXZHINX-LABEL: roundeven_f16: 554; RV64IZDINXZHINX: # %bb.0: 555; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 556; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 557; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 558; RV64IZDINXZHINX-NEXT: call roundevenf 559; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0 560; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 561; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 562; RV64IZDINXZHINX-NEXT: ret 563 %1 = call half @llvm.experimental.constrained.roundeven.f16(half %a, metadata !"fpexcept.strict") strictfp 564 ret half %1 565} 566 567declare iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half, metadata, metadata) 568 569define iXLen @lrint_f16(half %a) nounwind strictfp { 570; RV32IZFH-LABEL: lrint_f16: 571; RV32IZFH: # %bb.0: 572; RV32IZFH-NEXT: fcvt.w.h a0, fa0 573; RV32IZFH-NEXT: ret 574; 575; RV64IZFH-LABEL: lrint_f16: 576; RV64IZFH: # %bb.0: 577; RV64IZFH-NEXT: fcvt.l.h a0, fa0 578; RV64IZFH-NEXT: ret 579; 580; RV32IZHINX-LABEL: lrint_f16: 581; RV32IZHINX: # %bb.0: 582; RV32IZHINX-NEXT: fcvt.w.h a0, a0 583; RV32IZHINX-NEXT: ret 584; 585; RV64IZHINX-LABEL: lrint_f16: 586; RV64IZHINX: # %bb.0: 587; RV64IZHINX-NEXT: fcvt.l.h a0, a0 588; RV64IZHINX-NEXT: ret 589; 590; RV32IZDINXZHINX-LABEL: lrint_f16: 591; RV32IZDINXZHINX: # %bb.0: 592; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0 593; RV32IZDINXZHINX-NEXT: ret 594; 595; RV64IZDINXZHINX-LABEL: lrint_f16: 596; RV64IZDINXZHINX: # %bb.0: 597; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0 598; RV64IZDINXZHINX-NEXT: ret 599 %1 = call iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp 600 ret iXLen %1 601} 602 603declare iXLen @llvm.experimental.constrained.lround.iXLen.f16(half, metadata) 604 605define iXLen @lround_f16(half %a) nounwind strictfp { 606; RV32IZFH-LABEL: lround_f16: 607; RV32IZFH: # %bb.0: 608; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm 609; RV32IZFH-NEXT: ret 610; 611; RV64IZFH-LABEL: lround_f16: 612; RV64IZFH: # %bb.0: 613; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm 614; RV64IZFH-NEXT: ret 615; 616; RV32IZHINX-LABEL: lround_f16: 617; RV32IZHINX: # %bb.0: 618; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rmm 619; RV32IZHINX-NEXT: ret 620; 621; RV64IZHINX-LABEL: lround_f16: 622; RV64IZHINX: # %bb.0: 623; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rmm 624; RV64IZHINX-NEXT: ret 625; 626; RV32IZDINXZHINX-LABEL: lround_f16: 627; RV32IZDINXZHINX: # %bb.0: 628; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rmm 629; RV32IZDINXZHINX-NEXT: ret 630; 631; RV64IZDINXZHINX-LABEL: lround_f16: 632; RV64IZDINXZHINX: # %bb.0: 633; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0, rmm 634; RV64IZDINXZHINX-NEXT: ret 635 %1 = call iXLen @llvm.experimental.constrained.lround.iXLen.f16(half %a, metadata !"fpexcept.strict") strictfp 636 ret iXLen %1 637} 638 639declare i64 @llvm.experimental.constrained.llrint.i64.f16(half, metadata, metadata) 640 641define i64 @llrint_f16(half %a) nounwind strictfp { 642; RV32IZFH-LABEL: llrint_f16: 643; RV32IZFH: # %bb.0: 644; RV32IZFH-NEXT: addi sp, sp, -16 645; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 646; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 647; RV32IZFH-NEXT: call llrintf 648; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 649; RV32IZFH-NEXT: addi sp, sp, 16 650; RV32IZFH-NEXT: ret 651; 652; RV64IZFH-LABEL: llrint_f16: 653; RV64IZFH: # %bb.0: 654; RV64IZFH-NEXT: fcvt.l.h a0, fa0 655; RV64IZFH-NEXT: ret 656; 657; RV32IZHINX-LABEL: llrint_f16: 658; RV32IZHINX: # %bb.0: 659; RV32IZHINX-NEXT: addi sp, sp, -16 660; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 661; RV32IZHINX-NEXT: fcvt.s.h a0, a0 662; RV32IZHINX-NEXT: call llrintf 663; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 664; RV32IZHINX-NEXT: addi sp, sp, 16 665; RV32IZHINX-NEXT: ret 666; 667; RV64IZHINX-LABEL: llrint_f16: 668; RV64IZHINX: # %bb.0: 669; RV64IZHINX-NEXT: fcvt.l.h a0, a0 670; RV64IZHINX-NEXT: ret 671; 672; RV32IZDINXZHINX-LABEL: llrint_f16: 673; RV32IZDINXZHINX: # %bb.0: 674; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 675; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 676; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 677; RV32IZDINXZHINX-NEXT: call llrintf 678; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 679; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 680; RV32IZDINXZHINX-NEXT: ret 681; 682; RV64IZDINXZHINX-LABEL: llrint_f16: 683; RV64IZDINXZHINX: # %bb.0: 684; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0 685; RV64IZDINXZHINX-NEXT: ret 686 %1 = call i64 @llvm.experimental.constrained.llrint.i64.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp 687 ret i64 %1 688} 689 690declare i64 @llvm.experimental.constrained.llround.i64.f16(half, metadata) 691 692define i64 @llround_f16(half %a) nounwind strictfp { 693; RV32IZFH-LABEL: llround_f16: 694; RV32IZFH: # %bb.0: 695; RV32IZFH-NEXT: addi sp, sp, -16 696; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 697; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 698; RV32IZFH-NEXT: call llroundf 699; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 700; RV32IZFH-NEXT: addi sp, sp, 16 701; RV32IZFH-NEXT: ret 702; 703; RV64IZFH-LABEL: llround_f16: 704; RV64IZFH: # %bb.0: 705; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm 706; RV64IZFH-NEXT: ret 707; 708; RV32IZHINX-LABEL: llround_f16: 709; RV32IZHINX: # %bb.0: 710; RV32IZHINX-NEXT: addi sp, sp, -16 711; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 712; RV32IZHINX-NEXT: fcvt.s.h a0, a0 713; RV32IZHINX-NEXT: call llroundf 714; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 715; RV32IZHINX-NEXT: addi sp, sp, 16 716; RV32IZHINX-NEXT: ret 717; 718; RV64IZHINX-LABEL: llround_f16: 719; RV64IZHINX: # %bb.0: 720; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rmm 721; RV64IZHINX-NEXT: ret 722; 723; RV32IZDINXZHINX-LABEL: llround_f16: 724; RV32IZDINXZHINX: # %bb.0: 725; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 726; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 727; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 728; RV32IZDINXZHINX-NEXT: call llroundf 729; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 730; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 731; RV32IZDINXZHINX-NEXT: ret 732; 733; RV64IZDINXZHINX-LABEL: llround_f16: 734; RV64IZDINXZHINX: # %bb.0: 735; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0, rmm 736; RV64IZDINXZHINX-NEXT: ret 737 %1 = call i64 @llvm.experimental.constrained.llround.i64.f16(half %a, metadata !"fpexcept.strict") strictfp 738 ret i64 %1 739} 740 741define half @ldexp_f16(half %x, i32 signext %y) nounwind { 742; RV32IZFH-LABEL: ldexp_f16: 743; RV32IZFH: # %bb.0: 744; RV32IZFH-NEXT: addi sp, sp, -16 745; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 746; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 747; RV32IZFH-NEXT: call ldexpf 748; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 749; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 750; RV32IZFH-NEXT: addi sp, sp, 16 751; RV32IZFH-NEXT: ret 752; 753; RV64IZFH-LABEL: ldexp_f16: 754; RV64IZFH: # %bb.0: 755; RV64IZFH-NEXT: addi sp, sp, -16 756; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 757; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 758; RV64IZFH-NEXT: call ldexpf 759; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 760; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 761; RV64IZFH-NEXT: addi sp, sp, 16 762; RV64IZFH-NEXT: ret 763; 764; RV32IZHINX-LABEL: ldexp_f16: 765; RV32IZHINX: # %bb.0: 766; RV32IZHINX-NEXT: addi sp, sp, -16 767; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 768; RV32IZHINX-NEXT: fcvt.s.h a0, a0 769; RV32IZHINX-NEXT: call ldexpf 770; RV32IZHINX-NEXT: fcvt.h.s a0, a0 771; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 772; RV32IZHINX-NEXT: addi sp, sp, 16 773; RV32IZHINX-NEXT: ret 774; 775; RV64IZHINX-LABEL: ldexp_f16: 776; RV64IZHINX: # %bb.0: 777; RV64IZHINX-NEXT: addi sp, sp, -16 778; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 779; RV64IZHINX-NEXT: fcvt.s.h a0, a0 780; RV64IZHINX-NEXT: call ldexpf 781; RV64IZHINX-NEXT: fcvt.h.s a0, a0 782; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 783; RV64IZHINX-NEXT: addi sp, sp, 16 784; RV64IZHINX-NEXT: ret 785; 786; RV32IZDINXZHINX-LABEL: ldexp_f16: 787; RV32IZDINXZHINX: # %bb.0: 788; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 789; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill 790; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 791; RV32IZDINXZHINX-NEXT: call ldexpf 792; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0 793; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload 794; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 795; RV32IZDINXZHINX-NEXT: ret 796; 797; RV64IZDINXZHINX-LABEL: ldexp_f16: 798; RV64IZDINXZHINX: # %bb.0: 799; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 800; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill 801; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 802; RV64IZDINXZHINX-NEXT: call ldexpf 803; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0 804; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload 805; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 806; RV64IZDINXZHINX-NEXT: ret 807 %z = call half @llvm.experimental.constrained.ldexp.f16.i32(half %x, i32 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp 808 ret half %z 809} 810