1615d71d9SWu Xinlong; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2615d71d9SWu Xinlong; RUN: llc -mtriple=riscv64 -mattr=+zksh -verify-machineinstrs < %s \ 3615d71d9SWu Xinlong; RUN: | FileCheck %s -check-prefix=RV64ZKSH 4615d71d9SWu Xinlong 5*a64b3e92SCraig Topperdeclare i32 @llvm.riscv.sm3p0(i32); 6615d71d9SWu Xinlong 7*a64b3e92SCraig Topperdefine signext i32 @sm3p0_i32(i32 signext %a) nounwind { 8*a64b3e92SCraig Topper; RV64ZKSH-LABEL: sm3p0_i32: 9615d71d9SWu Xinlong; RV64ZKSH: # %bb.0: 10615d71d9SWu Xinlong; RV64ZKSH-NEXT: sm3p0 a0, a0 11615d71d9SWu Xinlong; RV64ZKSH-NEXT: ret 12*a64b3e92SCraig Topper %val = call i32 @llvm.riscv.sm3p0(i32 signext %a) 13*a64b3e92SCraig Topper ret i32 %val 14615d71d9SWu Xinlong} 15615d71d9SWu Xinlong 16*a64b3e92SCraig Topperdeclare i32 @llvm.riscv.sm3p1(i32); 17615d71d9SWu Xinlong 18*a64b3e92SCraig Topperdefine signext i32 @sm3p1_i32(i32 signext %a) nounwind { 19*a64b3e92SCraig Topper; RV64ZKSH-LABEL: sm3p1_i32: 20615d71d9SWu Xinlong; RV64ZKSH: # %bb.0: 21615d71d9SWu Xinlong; RV64ZKSH-NEXT: sm3p1 a0, a0 22615d71d9SWu Xinlong; RV64ZKSH-NEXT: ret 23*a64b3e92SCraig Topper %val = call i32 @llvm.riscv.sm3p1(i32 signext %a) 24*a64b3e92SCraig Topper ret i32 %val 25615d71d9SWu Xinlong} 26