xref: /llvm-project/llvm/test/CodeGen/RISCV/rv64d-double-convert.ll (revision cbc7812565b0b0d60c0dadbd3743650f863237d4) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
3; RUN:   -target-abi=lp64d | FileCheck %s -check-prefix=RV64ID
4; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \
5; RUN:   -target-abi=lp64 | FileCheck %s -check-prefix=RV64IDINX
6
7; This file exhaustively checks double<->i32 conversions. In general,
8; fcvt.l[u].d can be selected instead of fcvt.w[u].d because poison is
9; generated for an fpto[s|u]i conversion if the result doesn't fit in the
10; target type.
11
12define i32 @aext_fptosi(double %a) nounwind {
13; RV64ID-LABEL: aext_fptosi:
14; RV64ID:       # %bb.0:
15; RV64ID-NEXT:    fcvt.w.d a0, fa0, rtz
16; RV64ID-NEXT:    ret
17;
18; RV64IDINX-LABEL: aext_fptosi:
19; RV64IDINX:       # %bb.0:
20; RV64IDINX-NEXT:    fcvt.w.d a0, a0, rtz
21; RV64IDINX-NEXT:    ret
22  %1 = fptosi double %a to i32
23  ret i32 %1
24}
25
26define signext i32 @sext_fptosi(double %a) nounwind {
27; RV64ID-LABEL: sext_fptosi:
28; RV64ID:       # %bb.0:
29; RV64ID-NEXT:    fcvt.w.d a0, fa0, rtz
30; RV64ID-NEXT:    ret
31;
32; RV64IDINX-LABEL: sext_fptosi:
33; RV64IDINX:       # %bb.0:
34; RV64IDINX-NEXT:    fcvt.w.d a0, a0, rtz
35; RV64IDINX-NEXT:    ret
36  %1 = fptosi double %a to i32
37  ret i32 %1
38}
39
40define zeroext i32 @zext_fptosi(double %a) nounwind {
41; RV64ID-LABEL: zext_fptosi:
42; RV64ID:       # %bb.0:
43; RV64ID-NEXT:    fcvt.w.d a0, fa0, rtz
44; RV64ID-NEXT:    slli a0, a0, 32
45; RV64ID-NEXT:    srli a0, a0, 32
46; RV64ID-NEXT:    ret
47;
48; RV64IDINX-LABEL: zext_fptosi:
49; RV64IDINX:       # %bb.0:
50; RV64IDINX-NEXT:    fcvt.w.d a0, a0, rtz
51; RV64IDINX-NEXT:    slli a0, a0, 32
52; RV64IDINX-NEXT:    srli a0, a0, 32
53; RV64IDINX-NEXT:    ret
54  %1 = fptosi double %a to i32
55  ret i32 %1
56}
57
58define i32 @aext_fptoui(double %a) nounwind {
59; RV64ID-LABEL: aext_fptoui:
60; RV64ID:       # %bb.0:
61; RV64ID-NEXT:    fcvt.wu.d a0, fa0, rtz
62; RV64ID-NEXT:    ret
63;
64; RV64IDINX-LABEL: aext_fptoui:
65; RV64IDINX:       # %bb.0:
66; RV64IDINX-NEXT:    fcvt.wu.d a0, a0, rtz
67; RV64IDINX-NEXT:    ret
68  %1 = fptoui double %a to i32
69  ret i32 %1
70}
71
72define signext i32 @sext_fptoui(double %a) nounwind {
73; RV64ID-LABEL: sext_fptoui:
74; RV64ID:       # %bb.0:
75; RV64ID-NEXT:    fcvt.wu.d a0, fa0, rtz
76; RV64ID-NEXT:    ret
77;
78; RV64IDINX-LABEL: sext_fptoui:
79; RV64IDINX:       # %bb.0:
80; RV64IDINX-NEXT:    fcvt.wu.d a0, a0, rtz
81; RV64IDINX-NEXT:    ret
82  %1 = fptoui double %a to i32
83  ret i32 %1
84}
85
86define zeroext i32 @zext_fptoui(double %a) nounwind {
87; RV64ID-LABEL: zext_fptoui:
88; RV64ID:       # %bb.0:
89; RV64ID-NEXT:    fcvt.lu.d a0, fa0, rtz
90; RV64ID-NEXT:    ret
91;
92; RV64IDINX-LABEL: zext_fptoui:
93; RV64IDINX:       # %bb.0:
94; RV64IDINX-NEXT:    fcvt.lu.d a0, a0, rtz
95; RV64IDINX-NEXT:    ret
96  %1 = fptoui double %a to i32
97  ret i32 %1
98}
99
100define double @uitofp_aext_i32_to_f64(i32 %a) nounwind {
101; RV64ID-LABEL: uitofp_aext_i32_to_f64:
102; RV64ID:       # %bb.0:
103; RV64ID-NEXT:    fcvt.d.wu fa0, a0
104; RV64ID-NEXT:    ret
105;
106; RV64IDINX-LABEL: uitofp_aext_i32_to_f64:
107; RV64IDINX:       # %bb.0:
108; RV64IDINX-NEXT:    fcvt.d.wu a0, a0
109; RV64IDINX-NEXT:    ret
110  %1 = uitofp i32 %a to double
111  ret double %1
112}
113
114define double @uitofp_sext_i32_to_f64(i32 signext %a) nounwind {
115; RV64ID-LABEL: uitofp_sext_i32_to_f64:
116; RV64ID:       # %bb.0:
117; RV64ID-NEXT:    fcvt.d.wu fa0, a0
118; RV64ID-NEXT:    ret
119;
120; RV64IDINX-LABEL: uitofp_sext_i32_to_f64:
121; RV64IDINX:       # %bb.0:
122; RV64IDINX-NEXT:    fcvt.d.wu a0, a0
123; RV64IDINX-NEXT:    ret
124  %1 = uitofp i32 %a to double
125  ret double %1
126}
127
128define double @uitofp_zext_i32_to_f64(i32 zeroext %a) nounwind {
129; RV64ID-LABEL: uitofp_zext_i32_to_f64:
130; RV64ID:       # %bb.0:
131; RV64ID-NEXT:    fcvt.d.wu fa0, a0
132; RV64ID-NEXT:    ret
133;
134; RV64IDINX-LABEL: uitofp_zext_i32_to_f64:
135; RV64IDINX:       # %bb.0:
136; RV64IDINX-NEXT:    fcvt.d.wu a0, a0
137; RV64IDINX-NEXT:    ret
138  %1 = uitofp i32 %a to double
139  ret double %1
140}
141
142define double @sitofp_aext_i32_to_f64(i32 %a) nounwind {
143; RV64ID-LABEL: sitofp_aext_i32_to_f64:
144; RV64ID:       # %bb.0:
145; RV64ID-NEXT:    fcvt.d.w fa0, a0
146; RV64ID-NEXT:    ret
147;
148; RV64IDINX-LABEL: sitofp_aext_i32_to_f64:
149; RV64IDINX:       # %bb.0:
150; RV64IDINX-NEXT:    fcvt.d.w a0, a0
151; RV64IDINX-NEXT:    ret
152  %1 = sitofp i32 %a to double
153  ret double %1
154}
155
156define double @sitofp_sext_i32_to_f64(i32 signext %a) nounwind {
157; RV64ID-LABEL: sitofp_sext_i32_to_f64:
158; RV64ID:       # %bb.0:
159; RV64ID-NEXT:    fcvt.d.w fa0, a0
160; RV64ID-NEXT:    ret
161;
162; RV64IDINX-LABEL: sitofp_sext_i32_to_f64:
163; RV64IDINX:       # %bb.0:
164; RV64IDINX-NEXT:    fcvt.d.w a0, a0
165; RV64IDINX-NEXT:    ret
166  %1 = sitofp i32 %a to double
167  ret double %1
168}
169
170define double @sitofp_zext_i32_to_f64(i32 zeroext %a) nounwind {
171; RV64ID-LABEL: sitofp_zext_i32_to_f64:
172; RV64ID:       # %bb.0:
173; RV64ID-NEXT:    fcvt.d.w fa0, a0
174; RV64ID-NEXT:    ret
175;
176; RV64IDINX-LABEL: sitofp_zext_i32_to_f64:
177; RV64IDINX:       # %bb.0:
178; RV64IDINX-NEXT:    fcvt.d.w a0, a0
179; RV64IDINX-NEXT:    ret
180  %1 = sitofp i32 %a to double
181  ret double %1
182}
183