1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+zbc -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV32ZBC-ZBKC 4; RUN: llc -mtriple=riscv32 -mattr=+zbkc -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s -check-prefix=RV32ZBC-ZBKC 6 7declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b) 8 9define i32 @clmul32(i32 %a, i32 %b) nounwind { 10; RV32ZBC-ZBKC-LABEL: clmul32: 11; RV32ZBC-ZBKC: # %bb.0: 12; RV32ZBC-ZBKC-NEXT: clmul a0, a0, a1 13; RV32ZBC-ZBKC-NEXT: ret 14 %tmp = call i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b) 15 ret i32 %tmp 16} 17 18declare i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b) 19 20define i32 @clmul32h(i32 %a, i32 %b) nounwind { 21; RV32ZBC-ZBKC-LABEL: clmul32h: 22; RV32ZBC-ZBKC: # %bb.0: 23; RV32ZBC-ZBKC-NEXT: clmulh a0, a0, a1 24; RV32ZBC-ZBKC-NEXT: ret 25 %tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b) 26 ret i32 %tmp 27} 28