xref: /llvm-project/llvm/test/CodeGen/RISCV/riscv-codegen-prepare-atp.ll (revision abaa53199ed03b2e9de9fd373cbcfcc88e5348ff)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' < %s -S | FileCheck %s
3
4target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
5target triple = "riscv64"
6
7%struct.match_state = type { i64, i64  }
8
9; %add is also promoted by forking an extra sext.
10define void @promoteTwoOne(i32 %i, i32 %j, ptr %P1, ptr %P2 ) {
11; CHECK-LABEL: define void @promoteTwoOne(
12; CHECK-SAME: i32 [[I:%.*]], i32 [[J:%.*]], ptr [[P1:%.*]], ptr [[P2:%.*]]) {
13; CHECK-NEXT:  entry:
14; CHECK-NEXT:    [[S2:%.*]] = sext i32 [[I]] to i64
15; CHECK-NEXT:    [[PROMOTED2:%.*]] = sext i32 [[J]] to i64
16; CHECK-NEXT:    [[S:%.*]] = add nsw i64 [[S2]], [[PROMOTED2]]
17; CHECK-NEXT:    [[ADDR1:%.*]] = getelementptr inbounds i64, ptr [[P1]], i64 [[S]]
18; CHECK-NEXT:    store i64 [[S]], ptr [[ADDR1]], align 8
19; CHECK-NEXT:    [[ADDR2:%.*]] = getelementptr inbounds i64, ptr [[P2]], i64 [[S2]]
20; CHECK-NEXT:    store i64 [[S2]], ptr [[ADDR2]], align 8
21; CHECK-NEXT:    ret void
22;
23entry:
24  %add = add nsw i32 %i, %j
25  %s = sext i32 %add to i64
26  %addr1 = getelementptr inbounds i64, ptr %P1, i64 %s
27  store i64 %s, ptr %addr1
28  %s2 = sext i32 %i to i64
29  %addr2 = getelementptr inbounds i64, ptr %P2, i64 %s2
30  store i64 %s2, ptr %addr2
31  ret void
32}
33
34; Both %add1 and %add2 are promoted by forking extra sexts.
35define void @promoteTwoTwo(i32 %i, i32 %j, i32 %k, ptr %P1, ptr %P2) {
36; CHECK-LABEL: define void @promoteTwoTwo(
37; CHECK-SAME: i32 [[I:%.*]], i32 [[J:%.*]], i32 [[K:%.*]], ptr [[P1:%.*]], ptr [[P2:%.*]]) {
38; CHECK-NEXT:  entry:
39; CHECK-NEXT:    [[PROMOTED3:%.*]] = sext i32 [[J]] to i64
40; CHECK-NEXT:    [[PROMOTED4:%.*]] = sext i32 [[I]] to i64
41; CHECK-NEXT:    [[S:%.*]] = add nsw i64 [[PROMOTED3]], [[PROMOTED4]]
42; CHECK-NEXT:    [[ADDR1:%.*]] = getelementptr inbounds i64, ptr [[P1]], i64 [[S]]
43; CHECK-NEXT:    store i64 [[S]], ptr [[ADDR1]], align 8
44; CHECK-NEXT:    [[PROMOTED2:%.*]] = sext i32 [[K]] to i64
45; CHECK-NEXT:    [[S2:%.*]] = add nsw i64 [[PROMOTED3]], [[PROMOTED2]]
46; CHECK-NEXT:    [[ADDR2:%.*]] = getelementptr inbounds i64, ptr [[P2]], i64 [[S2]]
47; CHECK-NEXT:    store i64 [[S2]], ptr [[ADDR2]], align 8
48; CHECK-NEXT:    ret void
49;
50entry:
51  %add1 = add nsw i32 %j, %i
52  %s = sext i32 %add1 to i64
53  %addr1 = getelementptr inbounds i64, ptr %P1, i64 %s
54  store i64 %s, ptr %addr1
55  %add2 = add nsw i32 %j, %k
56  %s2 = sext i32 %add2 to i64
57  %addr2 = getelementptr inbounds i64, ptr %P2, i64 %s2
58  store i64 %s2, ptr %addr2
59  ret void
60}
61
62define i64 @promoteGEPSunk(i1 %cond, ptr %base, i32 %i) {
63; CHECK-LABEL: define i64 @promoteGEPSunk(
64; CHECK-SAME: i1 [[COND:%.*]], ptr [[BASE:%.*]], i32 [[I:%.*]]) {
65; CHECK-NEXT:  entry:
66; CHECK-NEXT:    [[PROMOTED1:%.*]] = sext i32 [[I]] to i64
67; CHECK-NEXT:    [[S:%.*]] = add nsw i64 [[PROMOTED1]], 1
68; CHECK-NEXT:    [[ADDR:%.*]] = getelementptr inbounds i64, ptr [[BASE]], i64 [[S]]
69; CHECK-NEXT:    [[S2:%.*]] = add nsw i64 [[PROMOTED1]], 2
70; CHECK-NEXT:    [[ADDR2:%.*]] = getelementptr inbounds i64, ptr [[BASE]], i64 [[S2]]
71; CHECK-NEXT:    br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_THEN2:%.*]]
72; CHECK:       if.then:
73; CHECK-NEXT:    [[V:%.*]] = load i64, ptr [[ADDR]], align 8
74; CHECK-NEXT:    [[V2:%.*]] = load i64, ptr [[ADDR2]], align 8
75; CHECK-NEXT:    [[R:%.*]] = add i64 [[V]], [[V2]]
76; CHECK-NEXT:    ret i64 [[R]]
77; CHECK:       if.then2:
78; CHECK-NEXT:    ret i64 0
79;
80entry:
81  %add = add nsw i32 %i, 1
82  %s = sext i32 %add to i64
83  %addr = getelementptr inbounds i64, ptr %base, i64 %s
84  %add2 = add nsw i32 %i,  2
85  %s2 = sext i32 %add2 to i64
86  %addr2 = getelementptr inbounds i64, ptr %base, i64 %s2
87  br i1 %cond, label %if.then, label %if.then2
88if.then:
89  %v = load i64, ptr %addr
90  %v2 = load i64, ptr %addr2
91  %r = add i64 %v, %v2
92  ret i64 %r
93if.then2:
94  ret i64 0;
95}
96