xref: /llvm-project/llvm/test/CodeGen/RISCV/readcyclecounter.ll (revision b2c9eed0d7d77ade740839eebe8c6c8ebe7e1ce2)
1*b2c9eed0SSam Elliott; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2*b2c9eed0SSam Elliott; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3*b2c9eed0SSam Elliott; RUN:   | FileCheck -check-prefix=RV32I %s
4*b2c9eed0SSam Elliott; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5*b2c9eed0SSam Elliott; RUN:   | FileCheck -check-prefix=RV64I %s
6*b2c9eed0SSam Elliott
7*b2c9eed0SSam Elliott; Verify that we lower @llvm.readcyclecounter() correctly.
8*b2c9eed0SSam Elliott
9*b2c9eed0SSam Elliottdeclare i64 @llvm.readcyclecounter()
10*b2c9eed0SSam Elliott
11*b2c9eed0SSam Elliottdefine i64 @test_builtin_readcyclecounter() nounwind {
12*b2c9eed0SSam Elliott; RV32I-LABEL: test_builtin_readcyclecounter:
13*b2c9eed0SSam Elliott; RV32I:       # %bb.0:
14*b2c9eed0SSam Elliott; RV32I-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
15*b2c9eed0SSam Elliott; RV32I-NEXT:    rdcycleh a1
16*b2c9eed0SSam Elliott; RV32I-NEXT:    rdcycle a0
17*b2c9eed0SSam Elliott; RV32I-NEXT:    rdcycleh a2
18*b2c9eed0SSam Elliott; RV32I-NEXT:    bne a1, a2, .LBB0_1
19*b2c9eed0SSam Elliott; RV32I-NEXT:  # %bb.2:
20*b2c9eed0SSam Elliott; RV32I-NEXT:    ret
21*b2c9eed0SSam Elliott;
22*b2c9eed0SSam Elliott; RV64I-LABEL: test_builtin_readcyclecounter:
23*b2c9eed0SSam Elliott; RV64I:       # %bb.0:
24*b2c9eed0SSam Elliott; RV64I-NEXT:    rdcycle a0
25*b2c9eed0SSam Elliott; RV64I-NEXT:    ret
26*b2c9eed0SSam Elliott  %1 = tail call i64 @llvm.readcyclecounter()
27*b2c9eed0SSam Elliott  ret i64 %1
28*b2c9eed0SSam Elliott}
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