xref: /llvm-project/llvm/test/CodeGen/RISCV/pr96366.ll (revision d5c9ffd545ebf171346ac69b15fafeee469f0b3c)
1*d5c9ffd5SYingwei Zheng; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2*d5c9ffd5SYingwei Zheng; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
3*d5c9ffd5SYingwei Zheng
4*d5c9ffd5SYingwei Zhengdeclare void @use(i32)
5*d5c9ffd5SYingwei Zheng
6*d5c9ffd5SYingwei Zhengdefine i32 @f(i32 %x) nounwind {
7*d5c9ffd5SYingwei Zheng; CHECK-LABEL: f:
8*d5c9ffd5SYingwei Zheng; CHECK:       # %bb.0:
9*d5c9ffd5SYingwei Zheng; CHECK-NEXT:    addi sp, sp, -16
10*d5c9ffd5SYingwei Zheng; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
11*d5c9ffd5SYingwei Zheng; CHECK-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
12*d5c9ffd5SYingwei Zheng; CHECK-NEXT:    mv s0, a0
13*d5c9ffd5SYingwei Zheng; CHECK-NEXT:    negw a0, a0
14*d5c9ffd5SYingwei Zheng; CHECK-NEXT:    call use
15*d5c9ffd5SYingwei Zheng; CHECK-NEXT:    li a0, 4
16*d5c9ffd5SYingwei Zheng; CHECK-NEXT:    subw a0, a0, s0
17*d5c9ffd5SYingwei Zheng; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
18*d5c9ffd5SYingwei Zheng; CHECK-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
19*d5c9ffd5SYingwei Zheng; CHECK-NEXT:    addi sp, sp, 16
20*d5c9ffd5SYingwei Zheng; CHECK-NEXT:    ret
21*d5c9ffd5SYingwei Zheng  %sub1 = sub nuw i32 0, %x
22*d5c9ffd5SYingwei Zheng  call void @use(i32 %sub1)
23*d5c9ffd5SYingwei Zheng  %sub2 = sub i32 1, %x
24*d5c9ffd5SYingwei Zheng  %sub3 = sub i32 3, %x
25*d5c9ffd5SYingwei Zheng  %mul = mul i32 %x, 1
26*d5c9ffd5SYingwei Zheng  %add1 = add i32 %sub2, %mul
27*d5c9ffd5SYingwei Zheng  %add2 = add i32 %add1, %sub3
28*d5c9ffd5SYingwei Zheng  ret i32 %add2
29*d5c9ffd5SYingwei Zheng}
30