125af23f5SSimon Pilgrim; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 225af23f5SSimon Pilgrim; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefix=RV32I %s 325af23f5SSimon Pilgrim; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefix=RV64I %s 425af23f5SSimon Pilgrim 525af23f5SSimon Pilgrim; regression due to creation of temporary i32 avgfloors node 625af23f5SSimon Pilgrimdefine signext i64 @PR95284(i32 signext %0) { 725af23f5SSimon Pilgrim; RV32I-LABEL: PR95284: 825af23f5SSimon Pilgrim; RV32I: # %bb.0: # %entry 9*9fb4bc5bSSimon Pilgrim; RV32I-NEXT: addi a1, a0, -1 10*9fb4bc5bSSimon Pilgrim; RV32I-NEXT: seqz a0, a0 11*9fb4bc5bSSimon Pilgrim; RV32I-NEXT: slli a2, a0, 31 1225af23f5SSimon Pilgrim; RV32I-NEXT: srli a1, a1, 1 13*9fb4bc5bSSimon Pilgrim; RV32I-NEXT: or a1, a1, a2 14*9fb4bc5bSSimon Pilgrim; RV32I-NEXT: addi a1, a1, 1 15*9fb4bc5bSSimon Pilgrim; RV32I-NEXT: seqz a2, a1 16*9fb4bc5bSSimon Pilgrim; RV32I-NEXT: sub a2, a2, a0 17*9fb4bc5bSSimon Pilgrim; RV32I-NEXT: andi a0, a1, -2 18*9fb4bc5bSSimon Pilgrim; RV32I-NEXT: slli a1, a2, 1 19*9fb4bc5bSSimon Pilgrim; RV32I-NEXT: srli a1, a1, 1 2025af23f5SSimon Pilgrim; RV32I-NEXT: ret 2125af23f5SSimon Pilgrim; 2225af23f5SSimon Pilgrim; RV64I-LABEL: PR95284: 2325af23f5SSimon Pilgrim; RV64I: # %bb.0: # %entry 2425af23f5SSimon Pilgrim; RV64I-NEXT: addi a0, a0, -1 2525af23f5SSimon Pilgrim; RV64I-NEXT: srli a0, a0, 1 2625af23f5SSimon Pilgrim; RV64I-NEXT: addi a0, a0, 1 2776c5158aSSimon Pilgrim; RV64I-NEXT: andi a0, a0, -2 2825af23f5SSimon Pilgrim; RV64I-NEXT: ret 2925af23f5SSimon Pilgrimentry: 3025af23f5SSimon Pilgrim %1 = zext nneg i32 %0 to i64 3125af23f5SSimon Pilgrim %2 = add nsw i64 %1, -1 3225af23f5SSimon Pilgrim %3 = lshr i64 %2, 1 3325af23f5SSimon Pilgrim %4 = add nuw nsw i64 %3, 1 3425af23f5SSimon Pilgrim %5 = and i64 %4, 9223372036854775806 3525af23f5SSimon Pilgrim ret i64 %5 3625af23f5SSimon Pilgrim} 37