1c8dc21d7SFroster; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2c8dc21d7SFroster; RUN: llc < %s -mtriple=riscv32-- -mattr=+v | FileCheck -check-prefix=RV32I %s 3c8dc21d7SFroster; RUN: llc < %s -mtriple=riscv64-- -mattr=+v | FileCheck -check-prefix=RV64I %s 4*3de76e4fSCraig Topper; RUN: llc < %s -mtriple=riscv32-- -mattr=+zve32x,+zvl128b | FileCheck -check-prefix=RV32I %s 5*3de76e4fSCraig Topper; RUN: llc < %s -mtriple=riscv64-- -mattr=+zve32x,+zvl128b | FileCheck -check-prefix=RV64I %s 6c8dc21d7SFroster 7c8dc21d7SFrosterdefine <8 x i16> @PR94265(<8 x i32> %a0) #0 { 8c8dc21d7SFroster; RV32I-LABEL: PR94265: 9c8dc21d7SFroster; RV32I: # %bb.0: 10c8dc21d7SFroster; RV32I-NEXT: vsetivli zero, 8, e32, m2, ta, ma 11c8dc21d7SFroster; RV32I-NEXT: vsra.vi v10, v8, 31 12c8dc21d7SFroster; RV32I-NEXT: vsrl.vi v10, v10, 26 13c8dc21d7SFroster; RV32I-NEXT: vadd.vv v8, v8, v10 14c8dc21d7SFroster; RV32I-NEXT: vsetvli zero, zero, e16, m1, ta, ma 15c8dc21d7SFroster; RV32I-NEXT: vnsrl.wi v10, v8, 6 16c8dc21d7SFroster; RV32I-NEXT: vsll.vi v8, v10, 10 17c8dc21d7SFroster; RV32I-NEXT: ret 18c8dc21d7SFroster; 19c8dc21d7SFroster; RV64I-LABEL: PR94265: 20c8dc21d7SFroster; RV64I: # %bb.0: 21c8dc21d7SFroster; RV64I-NEXT: vsetivli zero, 8, e32, m2, ta, ma 22c8dc21d7SFroster; RV64I-NEXT: vsra.vi v10, v8, 31 23c8dc21d7SFroster; RV64I-NEXT: vsrl.vi v10, v10, 26 24c8dc21d7SFroster; RV64I-NEXT: vadd.vv v8, v8, v10 25c8dc21d7SFroster; RV64I-NEXT: vsetvli zero, zero, e16, m1, ta, ma 26c8dc21d7SFroster; RV64I-NEXT: vnsrl.wi v10, v8, 6 27c8dc21d7SFroster; RV64I-NEXT: vsll.vi v8, v10, 10 28c8dc21d7SFroster; RV64I-NEXT: ret 29c8dc21d7SFroster %t1 = sdiv <8 x i32> %a0, <i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64> 30c8dc21d7SFroster %t2 = trunc <8 x i32> %t1 to <8 x i16> 31c8dc21d7SFroster %t3 = shl <8 x i16> %t2, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10> 32c8dc21d7SFroster ret <8 x i16> %t3 33c8dc21d7SFroster} 34