1*4ab2ac22SPatrick O'Neill; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2*4ab2ac22SPatrick O'Neill; RUN: llc -mtriple=riscv64-unknown-linux-gnu < %s | FileCheck %s 3*4ab2ac22SPatrick O'Neill; RUN: llc -mtriple=riscv32-unknown-linux-gnu < %s | FileCheck %s 4*4ab2ac22SPatrick O'Neill 5*4ab2ac22SPatrick O'Neill; Dag-combine used to improperly combine a vector vselect of 0 and 2 into 6*4ab2ac22SPatrick O'Neill; 2 + condition(0/1) because one of the two args was transformed from an i32->i64. 7*4ab2ac22SPatrick O'Neill 8*4ab2ac22SPatrick O'Neilldefine i16 @foo() { 9*4ab2ac22SPatrick O'Neill; CHECK-LABEL: foo: 10*4ab2ac22SPatrick O'Neill; CHECK: # %bb.0: # %entry 11*4ab2ac22SPatrick O'Neill; CHECK-NEXT: li a0, 0 12*4ab2ac22SPatrick O'Neill; CHECK-NEXT: ret 13*4ab2ac22SPatrick O'Neillentry: 14*4ab2ac22SPatrick O'Neill %insert.0 = insertelement <4 x i16> zeroinitializer, i16 2, i64 0 15*4ab2ac22SPatrick O'Neill %all.two = shufflevector <4 x i16> %insert.0, <4 x i16> zeroinitializer, <4 x i32> zeroinitializer 16*4ab2ac22SPatrick O'Neill %sel.0 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i16> zeroinitializer, <4 x i16> %all.two 17*4ab2ac22SPatrick O'Neill %mul.0 = call i16 @llvm.vector.reduce.mul.v4i16(<4 x i16> %sel.0) 18*4ab2ac22SPatrick O'Neill ret i16 %mul.0 19*4ab2ac22SPatrick O'Neill} 20*4ab2ac22SPatrick O'Neill 21*4ab2ac22SPatrick O'Neilldeclare i16 @llvm.vector.reduce.mul.v4i32(<4 x i16>) 22