1*2647bd73SYingwei Zheng; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2*2647bd73SYingwei Zheng; RUN: llc < %s -mtriple=riscv64 | FileCheck %s 3*2647bd73SYingwei Zheng 4*2647bd73SYingwei Zhengdefine i1 @test(i64 %x, i1 %cond1, i1 %cond2) { 5*2647bd73SYingwei Zheng; CHECK-LABEL: test: 6*2647bd73SYingwei Zheng; CHECK: # %bb.0: # %entry 7*2647bd73SYingwei Zheng; CHECK-NEXT: addi a3, a0, 1 8*2647bd73SYingwei Zheng; CHECK-NEXT: slt a0, a3, a0 9*2647bd73SYingwei Zheng; CHECK-NEXT: not a1, a1 10*2647bd73SYingwei Zheng; CHECK-NEXT: and a0, a1, a0 11*2647bd73SYingwei Zheng; CHECK-NEXT: or a0, a2, a0 12*2647bd73SYingwei Zheng; CHECK-NEXT: ret 13*2647bd73SYingwei Zhengentry: 14*2647bd73SYingwei Zheng %sadd = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %x, i64 1) 15*2647bd73SYingwei Zheng %ov = extractvalue { i64, i1 } %sadd, 1 16*2647bd73SYingwei Zheng %or = or i1 %cond2, %ov 17*2647bd73SYingwei Zheng %sel = select i1 %cond1, i1 %cond2, i1 %or 18*2647bd73SYingwei Zheng ret i1 %sel 19*2647bd73SYingwei Zheng} 20